Substrate

Abstract

This substrate is provided with: a core substrate having a first surface and a second surface on the opposite side from the first surface, and having an opening therein; at least a plurality of electronic components of the same type provided in the opening, the electronic components having a first electrode in a first direction and a second electrode in a second direction opposite to the first direction; a sealing material provided between the opening and the plurality of electronic components and between the plurality of electronic components, the sealing material having a third surface on the first surface side and a fourth surface on the second surface side; a plurality of first via hole conductors penetrating the third surface of the sealing material and electrically connected to the first electrodes of the plurality of electronic components; and a plurality of second via conductors electrically connected to the second electrodes of the plurality of electronic components, the first electrode having a first end surface located on the first surface side, and when the second surface is disposed horizontally, in a cross-section orthogonal to the second surface, the heights of the first end surfaces of the first electrodes of the plurality of electronic components with respect to a reference surface parallel to the second surface are different from each other.

Description

Technical Field

[0001] The utility model relates to a substrate. Background Art

[0002] Patent Document 1 describes a semiconductor package comprising: a core member; a through hole penetrating the core member; one or more passive components disposed in the through hole; and a sealing material covering at least a portion of the passive component and filling at least a portion of the through hole (for example, see Figure 9 ).

[0003] Patent Document 2 describes a printed wiring board comprising: a core substrate having an opening extending through a core material; a plurality of electronic components housed in the opening; and a resin formed in the opening and fixing the plurality of electronic components to the core substrate (e.g., see Figure 1 ).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 6694931

[0007] Patent Document 2: Japanese Patent Application Publication No. 2019-207978 Utility Model Content

[0008] Problems to be solved by utility models

[0009] However, in the semiconductor package described in Patent Document 1, the passive component's pair of electrodes are arranged parallel to the core member. Therefore, if a typical elongated chip component with a pair of electrodes located at the ends in the longitudinal direction is used as the passive component, the mounting area will increase. In other words, the semiconductor package described in Patent Document 1 has room for improvement in terms of further increasing the density of passive component placement.

[0010] In addition, in the printed wiring board described in patent document 2, when filling the opening with resin, the resin is heated and pressure is applied from the upper surface to press it into the opening. However, because the heights of multiple electronic components are consistent and there is no deviation, the direction of stress at this time will be relatively consistent, and the stress will tend to concentrate on the edges of the electronic components, etc., which may cause damage to the electronic components. In addition, the direction of residual stress also tends to be consistent. As a result, it is possible to cause warping of the substrate, a decrease in reliability, etc. In addition, in the printed wiring board described in patent document 2, because the pair of electrodes of the electronic component are arranged in a direction perpendicular to the core material, if a slender chip component with a general pair of electrodes located at the end in the long dimension direction is arranged as the passive component, the electrode area to which stress is applied becomes smaller. Therefore, the stress applied to the component when filling with resin becomes greater.

[0011] The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a substrate having excellent reliability that can arrange electronic components at a high density and can reduce warping of the substrate.

[0012] Technical solutions to solve problems

[0013] The substrate of the present invention comprises: a core substrate having a first surface and a second surface opposite to the first surface, and having an opening portion inside; at least a plurality of electronic components of the same type are arranged in the opening portion, having a first electrode in a first direction and a second electrode in a second direction opposite to the first direction, the first direction being a direction orthogonal to the second surface of the core substrate and facing the first surface side; a sealing material is arranged between the opening portion and the plurality of electronic components, and between the plurality of electronic components, and having a second electrode on the first surface side. The sealing material further comprises a first surface and a fourth surface on the side of the second surface; a plurality of first via-hole conductors penetrating the third surface of the sealing material and electrically connected to the first electrodes of the plurality of electronic components; and a plurality of second via-hole conductors electrically connected to the second electrodes of the plurality of electronic components, the first electrode having a first end surface located on the side of the first surface, and when the second surface is arranged horizontally, in a cross-section perpendicular to the second surface, the first end surfaces of the first electrodes of the plurality of electronic components have different heights relative to a reference plane parallel to the second surface.

[0014] Utility model effect

[0015] According to the present invention, it is possible to provide a substrate having excellent reliability in which electronic components can be arranged at a high density and warping of the substrate can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1It is a cross-sectional view schematically showing an example of a substrate according to an embodiment of the present invention, and shows a state in which the second surface of the core substrate is arranged horizontally.

[0017] Figure 2 It is schematically shown Figure 1 A plan view of an example of a core substrate and electronic components included in the substrate shown.

[0018] Figure 3 It is a cross-sectional view schematically showing the state where electronic components of the same type are sealed with a sealing material.

[0019] Figure 4 It shows Figure 1 Another cross-sectional view of the substrate shown is a diagram for explaining the maximum width of the surfaces of the plurality of first via-hole conductors that are in contact with the first electrodes.

[0020] Figure 5 It is schematically shown Figure 1 A cross-sectional view of a modified example of the substrate shown.

[0021] Figure 6 It is schematically shown Figure 1 A cross-sectional view of a modified example of the substrate shown.

[0022] Figure 7 This is a diagram schematically showing an example of a process of attaching an adhesive film for fixing electronic components to a core substrate.

[0023] Figure 8 This is a cross-sectional view schematically showing an example of a process of placing electronic components on an adhesive film.

[0024] Figure 9 This is a cross-sectional view schematically showing an example of a process of placing electronic components and semiconductor chips on an adhesive film.

[0025] Figure 10 It is a cross-sectional view schematically showing an example of a process of filling the opening portion of the core substrate with a sealing material.

[0026] Figure 11 It is a cross-sectional view schematically showing an example of a process of forming a via hole.

[0027] Figure 12 It is a cross-sectional view schematically showing an example of a process of forming a wiring layer.

[0028] Figure 13 It is a cross-sectional view schematically showing an example of a step of forming a deposition layer. DETAILED DESCRIPTION

[0029] Hereinafter, the substrate of the present invention will be described.

[0030] However, the present invention is not limited to the following configurations, and can be appropriately modified and applied within the scope of the gist of the present invention. In addition, a configuration in which two or more of the preferred configurations described below are combined is also the present invention.

[0031] [Substrate]

[0032] Figure 1 It is a cross-sectional view schematically showing an example of a substrate according to an embodiment of the present invention, and shows a state in which the second surface of the core substrate is arranged horizontally. Figure 2 It is schematically shown Figure 1 A top view of an example of a core substrate and an electronic component included in the substrate shown. Figure 1 It is along Figure 2 A cross-sectional view along line XX is shown.

[0033] Figure 1 as well as Figure 2 The substrate 100 shown includes: a core substrate 10 having a first surface 11 and a second surface 12 opposite to the first surface 11, with an opening 13 provided inside; at least a plurality of electronic components 20 of the same type are provided in the opening 13, each having a first electrode 21 in a first direction D1 and a second electrode 22 in a second direction D2 opposite to the first direction D1, wherein the first direction D1 is a direction perpendicular to the second surface 12 of the core substrate 10 and toward the first surface 11; a sealing material 30 is provided between the opening 13 and the electronic component 20, and between the plurality of electronic components 20. It has a third surface 31 on the side of the first surface 11 and a fourth surface 32 on the side of the second surface 12; a plurality of first via conductors 40, which penetrate the third surface 31 of the sealing material 30 and are electrically connected to the first electrodes 21 of the plurality of electronic components 20; a plurality of second via conductors 50, which are electrically connected to the second electrodes 22 of the plurality of electronic components 20; a first buildup layer (rewiring layer) 60, which is arranged on the first surface 11 of the core substrate 10 and the third surface 31 of the sealing material 30; and a second buildup layer (rewiring layer) 70, which is arranged on the second surface 12 of the core substrate 10 and the fourth surface 32 of the sealing material 30.

[0034] The core substrate 10 can be a resin substrate, a glass substrate, a ceramic substrate, or the like. The core substrate 10 may also be a printed wiring board with conductive wiring provided on its surface or internally. Preferably, an insulating support substrate (core material) formed from a resin such as epoxy resin and a reinforcing material such as glass cloth can be used as the core substrate 10. The support substrate may also contain inorganic particles such as silica particles or alumina particles.

[0035] The first surface 11 and the second surface 12 of the core substrate 10 are parallel to each other and constitute a pair of opposing main surfaces of the core substrate 10 .

[0036] The opening 13 of the core substrate 10 penetrates the core substrate 10. The shape of the opening 13 when the core substrate 10 is viewed from above is not particularly limited except that Figure 2 In addition to the rectangle shown, a circle, an ellipse, an oblong, an n-gon (n is an integer greater than or equal to 5), etc. may be used.

[0037] The substrate 100 is a component-embedded substrate in which a plurality of electronic components 20 are embedded. Each electronic component 20 is housed not on the first surface 11 and the second surface 12 of the core substrate 10 but in the opening 13 of the core substrate 10 .

[0038] The electronic component 20 can be Figure 2 The electronic components 20 may be arranged two-dimensionally in the opening 13 as shown, or may be arranged one-dimensionally in the opening 13. In the former case, the electronic components 20 may be arranged in a matrix ( Figure 2 ), can also be arranged in a zigzag pattern.

[0039] The electronic component 20 is not particularly limited, and examples thereof include passive components such as capacitors (eg, multilayer ceramic capacitors (MLCCs)) and inductors. The electronic component 20 is a chip component having an elongated shape such as a rectangular parallelepiped or a cylindrical shape.

[0040] Furthermore, the dimensions of each electronic component 20 are larger in the direction perpendicular to the second surface 12 (the first direction D1 or the second direction D2) than in the direction parallel to the second surface 12 of the core substrate 10. This allows for a higher density arrangement of the electronic components 20. Furthermore, to achieve a high density arrangement of the electronic components 20, the spacing between adjacent electronic components 20 is preferably smaller than the maximum width of the electronic component 20.

[0041] The so-called homogeneous electronic components 20 are components of the same size, standardized using chip component dimensional markings. Dimensional markings are defined by JIS (Japanese Industrial Standards) and EIA (Electronic Industries Alliance). JIS designations include, for example, 0603.

[0042] Furthermore, the electronic components 20 of the same type may be components of the same type among basic components of a circuit, such as capacitors or inductors.

[0043] Furthermore, the electronic components 20 of the same type may be components having the same model number, for example, capacitors or inductors.

[0044] Furthermore, only one type of electronic component 20 may be disposed within the same opening 13, or two or more types of electronic components 20 may be disposed (mixed). In the latter case, however, it suffices that at least a plurality of at least one type of electronic component 20 is disposed, but at least a plurality of each type of electronic component 20 may also be disposed.

[0045] In each electronic component 20, the first electrode 21 has a first end surface 23 located on the first surface 11 side, and the second electrode 22 has a second end surface 24 located on the second surface 12 side. The first electrode 21 and the second electrode 22 are located at one end and the other end, respectively, in the longitudinal direction of the elongated electronic component 20. The first end surface 23 and the second end surface 24 correspond to one end and the other end, respectively, in the longitudinal direction of the elongated electronic component 20. The first end surface 23 and the second end surface 24 are typically planar, but may also be curved (e.g., convex).

[0046] Sealing material 30 is a member for sealing electronic components 20 in opening 13, and is filled around each electronic component 20 in opening 13. Sealing material 30 includes a resin such as epoxy resin and a filler composed of inorganic particles such as silica particles and alumina particles.

[0047] At least one first via conductor 40 is provided for each electronic component 20, and each electronic component 20 is electrically connected to the first buildup layer 60 via the first via conductor 40. Each first via conductor 40 penetrates at least the insulating layer 61 of the first buildup layer 60 closest to the core substrate 10 and the third surface 31 of the sealing material 30, and reaches the first electrode 21 of the corresponding electronic component 20.

[0048] At least one second via-hole conductor 50 is provided for each electronic component 20, and each electronic component 20 is electrically connected to the second buildup layer 70 via the second via-hole conductor 50. Each second via-hole conductor 50 penetrates at least the insulating layer 71 of the second buildup layer 70 closest to the core substrate 10 and reaches the second electrode 22 of the corresponding electronic component 20.

[0049] The first buildup layer 60 electrically connects the electronic components 20 to each other, the electronic components 20 to other components, through-holes, terminals, etc., and is formed by alternately stacking at least one insulating layer 61 and at least one wiring layer 62 .

[0050] The second buildup layer 70 similarly electrically connects the electronic components 20 to each other, the electronic components 20 to other components, through-holes, terminals, etc., and is formed by alternately stacking at least one insulating layer 71 and at least one wiring layer 72 .

[0051] In this embodiment, the first electrode 21 and the second electrode 22 of each electronic component 20 are respectively arranged in the first direction D1 and the second direction D2 orthogonal to the second surface 12 of the core substrate 10, so that the slender electronic component 20, that is, the electronic component (chip component) with a general shape, can be arranged with high density in the opening portion 13 of the substrate 100.

[0052] Figure 3 It is a cross-sectional view schematically showing the state where electronic components of the same type are sealed with a sealing material.

[0053] In addition, if Figure 1 as well as Figure 3 As shown, when the second surface 12 of the core substrate 10 is arranged horizontally, in a cross section perpendicular to the second surface 12 (hereinafter referred to as a "vertical cross section"), the first end faces 23 of the first electrodes 21 of the plurality of electronic components (i.e., electronic components of the same type) 20 have different heights H1 relative to a reference plane P parallel to the second surface 12. Figure 3 As shown, when the electronic component 20 is sealed with the uncured film 81 used to form the sealing material, the direction of the stress becomes random, making it less likely to cause stress concentration, thereby reducing the damage applied to the electronic component 20. As a result, the reliability of the substrate 100 can be improved. In addition, the residual stress can be reduced, and its direction also becomes random, thereby suppressing the warping of the substrate 100. Furthermore, due to the deviation in the height H1, the adhesion between the sealing material 30 and the electronic component 20 is increased through the anchoring effect. This also helps to improve the reliability of the substrate 100.

[0054] In addition, in this embodiment, the heights H1 of the plurality of first end faces 23 may be different from each other as described above in at least one type of electronic component 20 arranged in the same opening portion 13, but preferably, the heights H1 of the plurality of first end faces 23 may be different from each other as described above in electronic components 20 of different types (including only one type) arranged in the same opening portion 13.

[0055] Furthermore, in addition to the above, multiple electronic components of the same type having first end faces of the first electrodes at substantially the same height may be disposed within the opening 13, but such electronic components are preferably not disposed. Specifically, preferably, only multiple electronic components 20 of the same type (either one type or two or more types) having first end faces 23 at different heights H1 are disposed within the same opening 13.

[0056] The height H1 of the first end surface 23 corresponds to the distance from the reference plane P to the point of the first end surface 23 that is farthest from the reference plane P. Figure 1As shown, the reference plane P may be located on the same plane as the second surface 12 of the core substrate 10 .

[0057] Preferably, when the second surface 12 of the core substrate 10 is horizontal, the height H1 of the first end surface 23 of the first electrode 21 of multiple electronic components (of the same type) 20 relative to the reference plane P deviates by at least -10% and at most +10% relative to their average height in a vertical cross-section. This improves the processability of the via holes for the first via conductors 40. Specifically, via holes can be processed within the typical processing tolerances of laser processing, eliminating the need to adjust processing conditions for each via or reduce processing speed to achieve a safer tolerance. On the other hand, if the height H1 of the multiple first end surfaces 23 deviates by more than ±10% relative to their average height, the processability of the via holes for the first via conductors 40 deteriorates, potentially reducing the processing speed during laser processing or causing damage to the first electrodes 21. Furthermore, the area of ​​the surface of the first via conductor 40 in contact with the first electrode 21 can vary significantly, resulting in significant variation in electrical resistance (contact resistance), potentially leading to poor performance. However, as will be described later, the area (maximum width) of the surface of the first via-hole conductor 40 in contact with the first electrode 21 may vary to some extent.

[0058] Preferably, when the second surface 12 of the core substrate 10 is arranged horizontally, the first end surfaces 23 of the first electrodes 21 of the plurality of electronic components (the same type of electronic components) 20 in a vertical cross-section have a height H1 that deviates by 10 μm or more relative to the reference plane P. The deviation in height H1 of each first end surface 23 is defined as the difference between the maximum and minimum heights of the plurality of electronic components 20 in the cross-section.

[0059] The first electrode 21 and the second electrode 22 preferably contain at least one Group 11 element and its alloys, more preferably copper and its alloys. Group 11 elements have a low absorption rate for light near a wavelength of 10 μm, the wavelength of a CO2 laser. Therefore, a relatively high-output CO2 laser can be used to process the via holes for the first via conductor 40. As a result, the via holes for the first via conductor 40 are easily processed and can be processed at high speed, thereby achieving cost reduction. Furthermore, copper and its alloys are cost-effective compared to other Group 11 elements and their alloys.

[0060] In this embodiment, when the second surface 12 of the core substrate 10 is configured horizontally, in the vertical section, the deviation of the height H1 of the first end surface 23 of the first electrode 21 of multiple electronic components (electronic components of the same type) 20 relative to the reference plane P is greater than the deviation of the height of the second end surface 24 of the second electrode 22 of these electronic components 20 relative to the reference plane P.

[0061] The height of the second end surface 24 corresponds to the distance from the reference plane P to the point of the second end surface 24 that is farthest from the reference plane P. Figure 1 As shown, when the reference plane P is set on the same plane as the second surface 12 of the core substrate 10, the height of each second end surface 24 may be substantially 0. That is, each second end surface 24 may be located on the reference plane P.

[0062] Figure 4 It shows Figure 1 Another cross-sectional view of the substrate shown is a diagram for explaining the maximum width of the surfaces of the plurality of first via-hole conductors that are in contact with the first electrodes.

[0063] like Figure 4 As shown, the maximum width W1 of the surface of the first via-hole conductors 40 in contact with the first electrode 21 may be different from one another. This allows laser drilling of the via holes for the first via-hole conductors 40 to be performed under the same conditions, thereby improving the processability of the via holes for the first via-hole conductors 40. More specifically, the via holes are mortar-shaped, so the deeper the via holes, the smaller the bottom area. Therefore, the maximum width W1 of the first via-hole conductors 40 may be smaller as the via holes contact the first electrode 21, which has a lower height H1 of the first end face 23.

[0064] On the other hand, the maximum widths of the surfaces of the plurality of second via-hole conductors 50 in contact with the second electrode 22 may be substantially the same.

[0065] The maximum width W1 of the surface of the first via-hole conductor 40 in contact with the first electrode 21 may be the width passing through the center of the surface (eg, a circle). The same applies to the maximum width of the surface of the second via-hole conductor 50 in contact with the second electrode 22.

[0066] like Figure 1 As shown, in this embodiment, the unevenness of the third surface 31 of the sealing material 30 is greater than the unevenness of the fourth surface 32 of the sealing material 30. More specifically, the third surface 31 of the sealing material 30 may have unevenness corresponding to the variation in height H1 of the first end surfaces 23 of the first electrodes 21 of the plurality of electronic components 20, and the fourth surface 32 of the sealing material 30 may be substantially flat and located on substantially the same plane.

[0067] Substrate 100 further includes: first wiring 63, which is provided on the third surface 31 side of sealing material 30 and connected to at least one of the plurality of first via conductors 40; and second wiring 73, which is provided on the fourth surface 32 side of sealing material 30 and connected to at least one of the plurality of second via conductors 50. First wiring 63 is included in wiring layer 62 of first buildup layer 60, and second wiring 73 is included in wiring layer 72 of second buildup layer 70.

[0068] As described above, the fourth surface 32 of the sealing material 30 is flatter than the third surface 31 of the sealing material 30 , and therefore it is preferable to effectively utilize this surface. Specifically, the following aspects are preferable, and in either case, the function of the electronic component 20 can be more effectively utilized.

[0069] That is, the smallest line of the second wiring 73, which has the smallest value among the widths (lines), is preferably thinner than the smallest line of the first wiring 63, which has the smallest value among the widths (lines). This allows for the formation of higher-definition vias and wiring on the fourth surface 32 of the sealing material 30, which is flatter than the third surface 31 of the sealing material 30.

[0070] In addition, when a plurality of wirings are arranged at equal intervals, the distance between wirings is referred to as a gap. It is preferable that the minimum gap of the second wiring 73 is smaller than the minimum gap of the first wiring 63 .

[0071] The line and space are collectively referred to as a line-space. A finer line-space results in a more precise wiring. Because the second wiring 73 can form a highly precise wiring, the minimum line-space of the second wiring 73 is preferably finer than the minimum line-space of the first wiring 63.

[0072] In more detail, preferably, when looking down at the substrate 100, in the area overlapping with the opening portion 13 of the core substrate 10, the minimum value of the line of the second wiring 73 as the redistribution (RDL) arranged on the side of the fourth surface 32 of the sealing material 30 is smaller than the minimum value of the line of the first wiring 63 arranged on the side of the third surface 31 of the sealing material 30.

[0073] In addition, preferably, when looking down at the substrate 100, in the area overlapping with the opening portion 13 of the core substrate 10, the minimum value of the gap of the second wiring 73 serving as the redistribution (RDL) arranged on the fourth surface 32 side of the sealing material 30 is smaller than the minimum value of the gap of the first wiring 63 arranged on the third surface 31 side of the sealing material 30.

[0074] In addition, preferably, when looking down at the substrate 100, in the area overlapping with the opening portion 13 of the core substrate 10, the minimum line-space value of the second wiring 73 as the redistribution (RDL) arranged on the fourth surface 32 side of the sealing material 30 is smaller than the minimum line-space value of the first wiring 63 arranged on the third surface 31 side of the sealing material 30.

[0075] Furthermore, in a plane parallel to second surface 12 of core substrate 10, the wiring density of second wiring 73 is preferably higher than the wiring density of first wiring 63. This allows vias and wiring to be formed at a higher density on fourth surface 32 of sealing material 30, which is flatter than third surface 31 of sealing material 30.

[0076] In more detail, it may also be that when looking down at the substrate 100, in the area overlapping with the opening portion 13 of the core substrate 10, the proportion of the area occupied by the second wiring 73 as the redistribution wiring (RDL) arranged on the fourth surface 32 side of the sealing material 30 is greater than the proportion of the area occupied by the first wiring 63 arranged on the third surface 31 side of the sealing material 30.

[0077] Furthermore, preferably, more wiring layers are provided on the fourth surface 32 side of the sealing material 30 than on the third surface 31 side of the sealing material 30. In other words, the number of wiring layers 72 of the second buildup layer 70 is preferably greater than the number of wiring layers 62 of the first buildup layer 60.

[0078] Figure 5 It is schematically shown Figure 1 A cross-sectional view of a modified example of the substrate shown.

[0079] exist Figure 5 In the illustrated substrate 100, the number of wiring layers 72 provided on the fourth surface 32 side of the sealing material 30 is four, and the number of wiring layers 62 provided on the third surface 31 side of the sealing material 30 is two. In other words, the number of wiring layers 72 is greater than the number of wiring layers 62.

[0080] Figure 6 It is schematically shown Figure 1 A cross-sectional view of a modified example of the substrate shown.

[0081] like Figure 6 As shown, a semiconductor chip 20A, such as an integrated circuit (IC), may be mounted in the opening 13 of the core substrate 10 along with the electronic component 20. In this case, the electronic component 20 and the semiconductor chip 20A are not identical electronic components, and the height relationship between the end faces of the electronic component 20 and the semiconductor chip 20A is not particularly limited.

[0082] [Method for manufacturing substrate]

[0083] The substrate 100 can be manufactured by the following method. Figure 7 This is a diagram schematically showing an example of a process of attaching an adhesive film for fixing electronic components to a core substrate.

[0084] First, if Figure 7 As shown, an opening 13 is formed in the core substrate 10 , and an adhesive film 80 for fixing electronic components is adhered to the second surface 12 of the core substrate 10 .

[0085] Figure 8 This is a cross-sectional view schematically showing an example of a process of placing electronic components on an adhesive film. Figure 9 This is a cross-sectional view schematically showing an example of a process of placing electronic components and semiconductor chips on an adhesive film.

[0086] Then, if Figure 8 As shown in FIG. 1 , the same type of electronic component 20 is placed vertically on the adhesive film 80. That is, the electronic component 20 is placed on the adhesive film 80 so that the first electrode 21 faces upward and the second electrode 22 faces downward. Thus, the second end surface 24 of the second electrode 22 adheres to the adhesive film 80. At this time, as shown in FIG. Figure 9 As shown, the electronic components 20 and the semiconductor chips 20A may be mounted in a mixed manner.

[0087] Figure 10 It is a cross-sectional view schematically showing an example of a process of filling the opening portion of the core substrate with a sealing material.

[0088] Then, if Figure 10 As shown, the electronic component 20 is sealed with a sealing material 30. Specifically, an uncured film containing a thermosetting resin and a filler is stacked on the first surface 11 of the core substrate 10 under vacuum. Then, the film is heated and pressed to soften it, so that the thermosetting resin and the filler are filled around each electronic component 20 in the opening 13. At this time, the height H1 of the first end face 23 of the first electrode 21 of the same electronic component 20 is different from each other, so as described above, stress concentration is less likely to occur, and damage to the electronic component 20 can be reduced. Then, the sealing material 30 is formed by curing the thermosetting resin. The sealing material 30 is flat on the flat surface side where the adhesive film 80 is arranged (the fourth surface 32), but has unevenness on the opposite side (the third surface 31).

[0089] Figure 11 It is a cross-sectional view schematically showing an example of a process of forming a via hole.

[0090] Then, if Figure 11As shown, after the adhesive film 80 is peeled off, the insulating layer 61 is formed on the first surface 11 of the core substrate 10 and the third surface 31 of the sealing material 30, and the insulating layer 71 is formed on the second surface 12 of the core substrate 10 and the fourth surface 32 of the sealing material 30. Furthermore, the adhesive film 80 can be used as it is without being peeled off. Then, a via hole 82 is formed in the insulating layer 61 by a laser or the like to expose the first end surface 23 of the first electrode 21, and a via hole 83 is formed in the insulating layer 71 to expose the second end surface 24 of the second electrode 22. At this time, if a CO2 laser is used, the process can be performed at a high speed.

[0091] Figure 12 It is a cross-sectional view schematically showing an example of a process of forming a wiring layer.

[0092] Then, if Figure 12 As shown, the via holes 82 and 83 are filled with plating (for example, semi-additive process) to form the first via-hole conductor 40 and the second via-hole conductor 50 , and the wiring layers 62 and 72 are formed.

[0093] Figure 13 It is a cross-sectional view schematically showing an example of a step of forming a deposition layer.

[0094] Then, if Figure 13 As shown, additional layers are added as needed to form a first buildup layer 60 and a second buildup layer 70 .

[0095] Through the above, the substrate 100 can be manufactured.

[0096] The following contents are disclosed in this specification.

[0097] <1>

[0098] A substrate comprising:

[0099] a core substrate having a first surface and a second surface opposite to the first surface, and having an opening therein;

[0100] At least a plurality of electronic components of the same type are provided in the opening, each of the electronic components having a first electrode in a first direction and a second electrode in a second direction opposite to the first direction, the first direction being a direction perpendicular to the second surface of the core substrate and facing the first surface;

[0101] a sealing material provided between the opening and the plurality of electronic components and between the plurality of electronic components, and having a third surface on the first surface side and a fourth surface on the second surface side;

[0102] a plurality of first via conductors penetrating the third surface of the sealing material and electrically connected to the first electrodes of the plurality of electronic components; and

[0103] a plurality of second via conductors electrically connected to the second electrodes of the plurality of electronic components;

[0104] The first electrode has a first end surface located on the first surface side.

[0105] When the second surface is arranged horizontally, in a cross section perpendicular to the second surface, the first end surfaces of the first electrodes of the plurality of electronic components have different heights relative to a reference plane parallel to the second surface.

[0106] <2>

[0107] The substrate according to <1>, wherein

[0108] When the second surface is arranged horizontally, in the cross section, the deviation of the heights of the first end surfaces of the first electrodes of the plurality of electronic components relative to the reference plane from their average height is not less than -10% and not more than +10%.

[0109] <3>

[0110] The substrate according to <1>, wherein

[0111] When the second surface is arranged horizontally, in the cross section, the first end surfaces of the first electrodes of the plurality of electronic components have heights that deviate by 10 μm or more from the reference plane.

[0112] <4>

[0113] The substrate according to any one of <1> to <3>, wherein

[0114] The first electrode and the second electrode include at least one of a Group 11 element and an alloy thereof.

[0115] <5>

[0116] The substrate according to <4>, wherein

[0117] The first electrode and the second electrode include at least one of copper and an alloy thereof.

[0118] <6>

[0119] The substrate according to any one of <1> to <5>, wherein

[0120] The second electrode has a second end surface located on the second surface side,

[0121] When the second surface is configured horizontally, in the cross-section, the deviation in height of the first end surface of the first electrode of the plurality of electronic components relative to the reference plane is greater than the deviation in height of the second end surface of the second electrode of the plurality of electronic components relative to the reference plane.

[0122] <7>

[0123] The substrate according to <6>, wherein

[0124] The maximum widths of the surfaces of the plurality of first via-hole conductors in contact with the first electrode are different from each other.

[0125] <8>

[0126] The substrate according to <6> or <7>, wherein

[0127] The unevenness of the third surface of the sealing material is larger than the unevenness of the fourth surface of the sealing material.

[0128] <9>

[0129] The substrate according to <8>, wherein

[0130] The substrate further comprises:

[0131] a first wiring provided on the third surface side of the sealing material and connected to at least one of the plurality of first via-hole conductors; and

[0132] The second wiring is provided on the fourth surface side of the sealing material and is connected to at least one of the plurality of second via-hole conductors.

[0133] <10>

[0134] The substrate according to <9>, wherein

[0135] The smallest line of the second wiring is thinner than the smallest line of the first wiring, or the smallest gap of the second wiring is thinner than the smallest gap of the first wiring.

[0136] <11>

[0137] The substrate according to <9> or <10>, wherein

[0138] In a plane parallel to the second surface, a wiring density of the second wiring is higher than a wiring density of the first wiring.

[0139] <12>

[0140] The substrate according to any one of <9> to <11>, wherein

[0141] A larger number of wiring layers are provided on the fourth surface side of the sealing material than on the third surface side of the sealing material.

[0142] Description of Reference Numerals

[0143] 10: Core substrate;

[0144] 11: Page 1;

[0145] 12: Page 2;

[0146] 13: opening;

[0147] 20: electronic components;

[0148] 20A: semiconductor chip;

[0149] 21: 1st electrode;

[0150] 22: second electrode;

[0151] 23: 1st end face;

[0152] 24: 2nd end face;

[0153] 30: Sealing material;

[0154] 31: Page 3;

[0155] 32: Page 4;

[0156] 40: 1st via conductor;

[0157] 50: second via conductor;

[0158] 60: 1st accumulation layer;

[0159] 61: insulation layer;

[0160] 62: wiring layer;

[0161] 63: 1st wiring;

[0162] 70: 2nd accumulation layer;

[0163] 71: insulation layer;

[0164] 72: wiring layer;

[0165] 73: 2nd wiring;

[0166] 80: Adhesive film;

[0167] 81: Uncured film;

[0168] 82, 83: vias;

[0169] 100: substrate;

[0170] D1: direction 1;

[0171] D2: direction 2;

[0172] P: datum plane;

[0173] H1: height of the first end face;

[0174] W1: Maximum width of the surface of the first via-hole conductor in contact with the first electrode.

Claims

1. A substrate, characterized in that have: a core substrate having a first surface and a second surface opposite to the first surface, and having an opening therein; At least a plurality of electronic components of the same type are provided in the opening, each of the electronic components having a first electrode in a first direction and a second electrode in a second direction opposite to the first direction, the first direction being a direction perpendicular to the second surface of the core substrate and facing the first surface; a sealing material provided between the opening and the plurality of electronic components and between the plurality of electronic components, and having a third surface on the first surface side and a fourth surface on the second surface side; a plurality of first via conductors penetrating the third surface of the sealing material and electrically connected to the first electrodes of the plurality of electronic components; as well as a plurality of second via conductors electrically connected to the second electrodes of the plurality of electronic components; The first electrode has a first end surface located on the first surface side. When the second surface is arranged horizontally, in a cross section perpendicular to the second surface, the first end surfaces of the first electrodes of the plurality of electronic components have different heights relative to a reference plane parallel to the second surface.

2. The substrate according to claim 1, wherein When the second surface is arranged horizontally, in the cross section, the heights of the first end surfaces of the first electrodes of the plurality of electronic components relative to the reference plane deviate from their average height by not less than -10% and not more than +10%.

3. The substrate according to claim 1, wherein When the second surface is arranged horizontally, in the cross section, the first end surfaces of the first electrodes of the plurality of electronic components may have a height deviation of 10 μm or more relative to the reference plane.

4. The substrate according to any one of claims 1 to 3, wherein The first electrode and the second electrode are composed of a Group 11 element or an alloy of a Group 11 element.

5. The substrate according to claim 4, wherein The first electrode and the second electrode are made of copper or a copper alloy.

6. The substrate according to any one of claims 1 to 3, wherein The second electrode has a second end surface located on the second surface side, When the second surface is configured horizontally, in the cross-section, the deviation in height of the first end surface of the first electrode of the plurality of electronic components relative to the reference plane is greater than the deviation in height of the second end surface of the second electrode of the plurality of electronic components relative to the reference plane.

7. The substrate according to claim 6, characterized in that The maximum widths of the surfaces of the plurality of first via-hole conductors in contact with the first electrode are different from each other.

8. The substrate according to claim 6, wherein The unevenness of the third surface of the sealing material is larger than the unevenness of the fourth surface of the sealing material.

9. The substrate according to claim 8, characterized in that The substrate further comprises: a first wiring provided on the third surface side of the sealing material and connected to at least one of the plurality of first via-hole conductors; and The second wiring is provided on the fourth surface side of the sealing material and is connected to at least one of the plurality of second via-hole conductors.

10. The substrate according to claim 9, wherein The smallest line of the second wiring is thinner than the smallest line of the first wiring, or the smallest gap of the second wiring is thinner than the smallest gap of the first wiring.

11. The substrate according to claim 9 or 10, characterized in that In a plane parallel to the second surface, a wiring density of the second wiring is higher than a wiring density of the first wiring.

12. The substrate according to claim 9 or 10, characterized in that A larger number of wiring layers are provided on the fourth surface side of the sealing material than on the third surface side of the sealing material.

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