Infrared focal plane detector chip structure with suspension verification structure
By preparing the suspension verification structure and inverted trapezoidal etching pit inner infrared reflective layer on the ROIC wafer, the problem of difficulty in verification of ROIC and MEMS chips in the prior art is solved, and an independent verification and high response rate infrared focal plane detector chip is realized.
Patent Information
- Application Number
- CN202422390440.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-09-29
AI Technical Summary
The problem of the existing technology that it is difficult to effectively verify ROIC and MEMS chips separately on the same wafer leads to verification difficulties, waste of funds and time, and the MEMS process has an impact on ROIC performance.
Prepare a suspension verification structure on the ROIC wafer, including a dielectric layer and a resistor layer, which is divided into heating resistors and alternative cell resistances, realizing independent verification of MEMS and ROIC, and using inverted trapezoidal etching pits to prepare infrared reflective layers to ensure the independence and high response rate of the MEMS chip.
The problem of separately verifying ROIC and MEMS chips on the same wafer is realized, saving money and time costs, and improving the response rate of infrared focal plane detectors and the electrical and thermal performance of the cells.
Smart Images
Figure CN223295531U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of micro-electromechanical system (MEMS) design and manufacturing in semiconductor technology, in particular to an infrared focal plane detector chip structure with a suspension verification structure. Background Art
[0002] MEMS uncooled infrared detectors, implemented using CMOS technology, have been widely used in military and commercial fields, such as night vision, mineral exploration, autonomous driving, and fire prevention and control. The detector chip mainly consists of two parts: a MEMS chip with a high response rate and a ROIC chip directly connected to the MEMS chip. The working principle of an uncooled infrared detector is that external infrared radiation irradiates the thermistor layer of the chip, causing the temperature of the thermistor layer to rise. Since the thermistor material itself has a certain temperature coefficient of resistance, the temperature rise causes the resistance of the thermistor material to change. Using the ROIC chip, a certain electrical bias is applied to both ends of the thermistor material to read the resistance change of the thermistor material caused by external infrared radiation. Through certain calibration methods, the resistance change is then mapped to the external temperature change, completing the infrared temperature measurement and imaging functions.
[0003] The main function of the above-mentioned ROIC chip is to integrate the photocurrent signal generated by the MEMS chip into a voltage signal according to a reasonable timing, and perform signal processing operations such as amplification, sampling, and output drive, thereby acting as a bridge between the detector array photoelectric signal and the system signal processing circuit.
[0004] Typically, the ROIC circuit is fabricated using a standard semiconductor process, and then the MEMS chip is taped onto the ROIC to form a complete IRFPA chip. The final output signal contains both external radiation information collected by the MEMS chip and additional information from the ROIC chip's processing. Verifying that a problem with the IRFPA's overall output signal originates from the MEMS or the ROIC is generally difficult, and it can even be impossible to determine the source of the problem. This requires extensive wafer batch testing to troubleshoot the problem, incurring significant costs and time. Existing IRFPA chips are not adequately designed to verify the source of chip problems. Another existing technique involves taping out the MEMS and ROIC chips separately on two wafers to verify the source of the problem. This approach has the disadvantage that the structure and performance of the MEMS chip fabricated on the bare wafer differs from that of the ROIC. For example, when processing the MEMS chip on the ROIC, the heat generated during the MEMS process can affect the performance of the underlying ROIC. Furthermore, the thermal conductivity of the ROIC chip wafer differs from that of the bare wafer, causing the temperature to affect the MEMS process and, consequently, MEMS performance. Both existing technologies cannot complete the verification work well, but this verification work is very necessary. Differentiating the problems and improving the design or process adjustment of the problem chips will save engineering time and financial investment. Utility Model Content
[0005] The main purpose of this utility model is to propose an infrared focal plane detector chip structure with a suspended verification structure, aiming to separately verify the adverse problems caused by ROIC and MEMS, improve the response rate of the infrared focal plane detector pixel, and not affect the thermal and electrical parameters of the pixel.
[0006] To achieve the above objectives, the present invention provides an infrared focal plane detector chip structure with a suspension verification structure, the infrared focal plane detector chip structure with a suspension verification structure comprising an ROIC wafer, a suspension verification structure, a pixel bridge deck layer, and an infrared absorption umbrella layer, wherein the suspension verification structure is arranged on the surface of the ROIC wafer, the pixel bridge deck layer is arranged on the suspension verification structure, and the infrared absorption umbrella layer is arranged on the pixel bridge deck layer;
[0007] The suspension verification structure includes a dielectric layer and a resistance layer. The resistance layer is divided into two parts, one part is the heating resistor of the suspension verification structure, and the other part is the replacement pixel resistance structure.
[0008] A further technical solution of the present invention is that the pixel bridge deck layer includes a first dielectric insulating layer, a thermally sensitive layer, a second dielectric insulating layer, an electrical conductive layer and a dielectric protective layer which are sequentially arranged from bottom to top.
[0009] A further technical solution of the present invention is that the infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance.
[0010] A further technical solution of the present invention is that the resistance layer of the suspension verification structure is a single-layer or multi-layer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polysilicon.
[0011] A further technical solution of the present invention is that the material of the dielectric layer of the suspension verification structure includes Si3N4 or SiO2.
[0012] The beneficial effects of the infrared focal plane detector chip structure with a suspension verification structure of the utility model are:
[0013] 1. By sequentially fabricating ROIC and MEMS chips on the same ROIC wafer, and with a suspended verification structure, the MEMS chip can verify defects generated by ROIC and MEMS separately, saving money and time costs;
[0014] 2. The utility model uses an inverted trapezoidal etched pit to prepare an infrared reflective layer. Compared with a flat reflective layer, the inverted trapezoidal reflective layer has a better light-gathering effect and improves the response rate of the infrared focal plane detector pixel;
[0015] 3. The suspended verification structure prepared by the utility model has no effect on the electrical parameters and thermal parameters of the pixel structure, ensuring that the pixel structure has a high response rate. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.
[0017] Figure 1 This is a schematic diagram of the overall structure of the infrared focal plane detector chip structure with a suspension verification structure and an inverted trapezoidal etched pit in the utility model;
[0018] Figures 2 to 8 This is a schematic diagram of the preparation process of the infrared focal plane detector chip structure with a suspension verification structure having an inverted trapezoidal etched pit in the utility model;
[0019] Figure 9 This is a schematic diagram of the overall structure of the infrared focal plane detector chip structure with a suspension verification structure without inverted trapezoidal etching pits of the utility model;
[0020] Figures 10 to 16 It is a schematic diagram of the preparation process of the infrared focal plane detector chip structure with a suspension verification structure without inverted trapezoidal etching pits of the present invention.
[0021] Description of Figure Numbers:
[0022] ROIC wafer 1; suspended verification structure 2; pixel bridge layer 3; infrared absorption umbrella layer 4; dielectric layer 5; pixel electrode 6; reflective layer 7; heating resistor 8; alternative pixel resistor structure 9; suspended verification structure electrode 10; first dielectric insulating layer 11; thermal sensitive layer 12; second dielectric insulating layer 13; electrical conductive layer 14; dielectric protective layer 15.
[0023] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0025] This utility model proposes an infrared focal plane detector chip structure with a suspension verification structure, please refer to Figures 1 to 16 A preferred embodiment of the infrared focal plane detector chip structure with a suspended verification structure of the present invention includes a ROIC wafer 1, a suspended verification structure 2, a pixel bridge deck layer 3 and an infrared absorption umbrella layer 4, wherein the suspended verification structure 2 is arranged on the surface of the ROIC wafer 1, the pixel bridge deck layer 3 is arranged on the suspended verification structure 2, and the infrared absorption umbrella layer 4 is arranged on the pixel bridge deck layer 3.
[0026] It should be noted that the "suspension" in this embodiment means that the main body of the structure has no physical connection between the upper and lower parts, and only the electrodes are connected to the ROIC wafer 1 below. After the chip is packaged, the upper and lower parts of this structure are vacuum.
[0027] The suspended verification structure 2 includes a dielectric layer 5 and a resistor layer. The resistor layer is divided into two parts. One part is the heating resistor 8 of the suspended verification structure 2 , and the other part is the replacement pixel resistor structure 9 .
[0028] Specifically, in this embodiment, the pixel bridge deck layer 3 includes a first dielectric insulating layer 11 , a thermally sensitive layer 12 , a second dielectric insulating layer 13 , an electrical conductive layer 14 and a dielectric protective layer 15 , which are sequentially arranged from bottom to top.
[0029] The infrared absorption umbrella layer 4 is composed of a dielectric and a conductive layer with a certain resistance.
[0030] The resistance layer of the suspension verification structure 2 is a single layer or multilayer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polysilicon.
[0031] The material of the dielectric layer 5 of the suspended verification structure 2 includes Si 3 N 4 or SiO 2 .
[0032] The preparation process of a conventional IRFPA chip is as follows: after completing the ROIC chip process, the first sacrificial layer is first prepared on the chip. The sacrificial layer material is generally PI (polyimide), and a photolithography process is used on the PI to form the bridge pier holes of the microbridge structure. Then, other structures such as the support layer, the thermal layer 12, and the electrical connection layer are prepared on the PI layer, and the layers are patterned by photolithography. Finally, the PI is removed by release to form a microbridge structure pixel. Before removing the first layer of PI, the chip using a double-layer or even multi-layer process will continue to prepare a second or more layers of PI and a patterned functional film layer on the first microbridge layer, and finally release all the PI in one step to form a multi-layer structure pixel.
[0033] In the preparation process of the infrared focal plane detector chip structure with a suspension verification structure in this embodiment, in addition to the above-mentioned conventional IRFPA preparation process, a suspension layer PI-0 is also prepared on the ROIC wafer 1; a suspension verification layer is prepared on the suspension layer PI-0, and the suspension verification layer is photolithographically etched to form a suspension verification structure 2 connected to the ROIC electrode.
[0034] In this embodiment, two chips, ROIC and MEMS, are sequentially prepared on the same ROIC wafer 1. The MEMS chip is provided with a suspended verification structure 2, which can verify the defects caused by the ROIC and MEMS separately, saving money and time costs. In particular, the suspended verification structure 2 of the present invention includes both a heating resistor 8 structure and a replacement pixel resistor structure 9, eliminating the IRFPA blind pixel problem.
[0035] In this embodiment, the suspension verification structure 2 includes at least one set of heating resistors 8 and a set of replacement pixel resistors 9. The heating resistors 8 operate by applying a constant power of heat, P0, to the two electrodes of the suspension verification structure 2 via the ROIC chip. This heat is then radiated to the thermosensitive layer 12. The resulting resistance change signal, generated by the temperature rise of the thermosensitive layer 12, is processed by the other two electrodes of the ROIC, generating a voltage signal, V0, corresponding to P0. By comparing the different P0 and V0 signals, the MEMS pixel's function can be determined. The replacement pixel resistors 9 function similarly to the thermosensitive layer 12. If the thermosensitive layer 12 fails, the ROIC control software reads the output signals of the pixels surrounding the failed thermosensitive layer 12, interpolates the output signal at the location of the failed pixel, and feeds this back to the control terminal of the ROIC heating resistors 8. This ensures that the output signal of the replacement pixel resistors, as measured by the ROIC, matches the interpolated signal, thus replacing the failed pixel. The ROIC chip incorporates a verification structure isolated from the MEMS, enabling ROIC chip verification. In summary, the purpose of first preparing the ROIC chip and then preparing the MEMS chip on the same wafer and then verifying the ROIC and MEMS chips separately is achieved.
[0036] One approach to creating the suspended verification structure 2 involves first performing deep silicon etching on the ROIC wafer 1 to form inverted trapezoidal etched pits. An infrared reflective layer 7 is then formed on the inner surface of the inverted trapezoidal shape. A suspension layer, PI-0, is then formed, and the suspended verification structure 2 is formed on top of the suspension layer. The infrared reflective layer 7 formed within the inverted trapezoidal etched pits provides a better light-gathering effect than a flat reflective layer, thereby improving the responsivity of the infrared focal plane detector pixels.
[0037] In this embodiment, the suspended verification structure 2 can be prepared under the bridge deck layer or above the bridge deck layer. The suspended verification structure 2 has no contact thermal isolation with the pixel structure. The prepared suspended verification structure 2 has no effect on the electrical parameters and thermal parameters of the pixel structure, ensuring that the pixel structure has a high response rate.
[0038] Please refer to Figures 1 to 16 The method for preparing the infrared focal plane detector chip structure with a suspension verification structure of the utility model comprises the following steps:
[0039] Step S10, preparing a suspended PI-0 layer on the ROIC wafer 1. After the preparation of the suspended PI-0 layer is completed, the suspended PI-0 layer is photoetched to expose the suspended verification structure electrode 10 of the ROIC wafer 1;
[0040] Step S20: preparing a dielectric layer 5 and a resistor layer on the suspended PI-0 layer, and performing photolithography and etching to form a suspended verification structure 2 with a certain resistance. The resistor layer is divided into two parts: one part is the heating resistor 8 of the suspended verification structure 2, and the other part is the replacement pixel resistor structure 9;
[0041] Step S30, preparing a PI-1 layer on the suspended verification structure 2, and photolithographically etching to form a PI-1 hole structure connecting the pixel structure and the pixel electrode 6 of the ROIC wafer 1;
[0042] Step S40, preparing a first dielectric insulating layer 11 and a heat-sensitive layer 12 on the PI-1 layer, and performing photolithography and etching on them to form a suitable structure;
[0043] Step S50: Forming a second dielectric insulating layer 13 and an electrically conductive layer 14 on the thermal layer 12, wherein one end of the electrically conductive layer 14 is connected to the thermal layer 12, and the other end is connected to the pixel electrode 6 of the ROIC wafer 1; forming a dielectric layer 5 on the electrically conductive layer 14 to form a protective layer; the first dielectric insulating layer 11, the thermal layer 12, the second dielectric insulating layer 13, the electrically conductive layer 14, and the dielectric protective layer 15 formed on the PI-1 layer together constitute the pixel bridge layer 3;
[0044] Step S60: Prepare a PI-2 layer on the pixel bridge deck layer 3, photolithographically etch a contact hole penetrating the dielectric protection layer 15, and prepare an infrared absorption umbrella layer 4 on the PI-2 layer. The infrared absorption umbrella layer 4 is composed of a dielectric and a conductive layer with a certain resistance.
[0045] Step S70 , releasing all PI layers through a plasma process to form a pixel structure having a suspended verification structure 2 .
[0046] In this embodiment, in step S10, the step of preparing a suspended PI-0 layer on the ROIC wafer 1 includes:
[0047] Deep silicon etching is performed on the ROIC wafer 1 to form an inverted trapezoidal etch pit, an infrared reflective layer 7 is prepared on the inner surface of the inverted trapezoidal etch pit, and then a suspended PI-0 layer is prepared on the infrared reflective layer 7, or a suspended PI-0 layer is directly prepared on the ROIC wafer 1.
[0048] In this embodiment, before step S10, the following steps are further included:
[0049] The ROIC wafer 1 is cleaned and dried to remove surface impurities and moisture.
[0050] The beneficial effects of the infrared focal plane detector chip structure with the suspension verification structure 2 of the utility model are:
[0051] 1. By sequentially fabricating ROIC and MEMS chips on the same ROIC wafer 1, and with a suspended verification structure 2 on the MEMS chip, defects generated by the ROIC and MEMS can be verified separately, saving money and time costs.
[0052] 2. The present invention adopts an inverted trapezoidal etched pit to prepare an infrared reflective layer 7. Compared with a flat reflective layer 7, the inverted trapezoidal reflective layer 7 has a better light-gathering effect and improves the response rate of the infrared focal plane detector pixel;
[0053] 3. The suspended verification structure 2 prepared by the present invention has no effect on the electrical parameters and thermal parameters of the pixel structure, ensuring that the pixel structure has a high response rate.
[0054] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made based on the contents of the present invention specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present invention.
Claims
1. An infrared focal plane detector chip structure with a suspension verification structure, characterized in that: The infrared focal plane detector chip structure with a suspension verification structure includes an ROIC wafer, a suspension verification structure, a pixel bridge deck layer and an infrared absorption umbrella layer, wherein the suspension verification structure is arranged on the surface of the ROIC wafer, the pixel bridge deck layer is arranged on the suspension verification structure, and the infrared absorption umbrella layer is arranged on the pixel bridge deck layer; The suspension verification structure includes a dielectric layer and a resistance layer, and the resistance layer is divided into two parts, one part is the heating resistor of the suspension verification structure, and the other part is the replacement pixel resistance structure; The dielectric layer of the suspended verification structure is made of Si 3 N 4 or SiO 2 .
2. The infrared focal plane detector chip structure with a suspension verification structure according to claim 1, characterized in that: The pixel bridge deck layer includes a first dielectric insulating layer, a heat-sensitive layer, a second dielectric insulating layer, an electrical conductive layer and a dielectric protective layer which are sequentially arranged from bottom to top.
3. The infrared focal plane detector chip structure with a suspension verification structure according to claim 2, characterized in that: The infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance.
4. The infrared focal plane detector chip structure with a suspension verification structure according to claim 3, characterized in that: The resistance layer of the suspension verification structure is a single-layer or multi-layer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polysilicon.