Hall circuit based on vertical Hall device
Through the Hall circuit based on vertical Hall devices, combined with rotation current modulation and related dual sampling demodulation technology, the offset and 1/f noise problems of vertical Hall devices are solved, and efficient amplification and error elimination of Hall signals are achieved.
Patent Information
- Application Number
- CN202422438376.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-10-10
AI Technical Summary
The magnetic field sensitivity of vertical Hall devices is low and the offset is severe, and the prior art is difficult to effectively eliminate the offset and 1/f noise of Hall devices.
The Hall circuit based on vertical Hall devices is adopted, combined with 2-phase rotation current modulation and related double sampling demodulation technology, and the rotation current modulation of the X-axis and Y-axis Hall devices is controlled through a four-phase sequential clock circuit, and offset and 1/f noise are eliminated using the related double sampling demodulation circuit.
Effectively eliminates offset and 1/f noise from Hall devices and amplifiers, ensuring consistent amplification of X-axis and Y-axis Hall signals, reducing the area and power consumption of the circuit.
Smart Images
Figure CN223296125U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a Hall circuit based on a vertical Hall device. Background Art
[0002] Vertical Hall-effect devices can detect magnetic fields along the X and Y axes parallel to the device plane. Because Hall-effect devices have very low magnetic field sensitivity and significant offset, subsequent signal conditioning circuitry is required to eliminate the offset and amplify the weak Hall-effect signal. Currently, the main offset cancellation techniques include auto-zeroing, correlated double sampling, and spinning current. Auto-zeroing and correlated double sampling are commonly used to eliminate the amplifier's own offset, but they cannot directly eliminate the offset of the Hall-effect device. The spinning current method, on the other hand, can eliminate the offset and 1 / f noise generated by the Hall-effect device, as well as the amplifier's own offset, and has been widely used in horizontal Hall-effect sensors. However, due to the shallow N-wells provided by the CMOS process and the high impurity concentration and Gaussian distribution of the N-well, vertical Hall-effect devices have lower magnetic field sensitivity than horizontal Hall-effect devices, necessitating a circuit design tailored to vertical Hall-effect devices. Utility Model Content
[0003] The technical problem to be solved by the present invention is: in order to overcome the above technical problems, the present invention provides a Hall circuit based on a vertical Hall device.
[0004] The utility model solves the technical problem thereof by adopting the following technical solution: a Hall circuit based on a vertical Hall device, comprising a low-pass filter, an amplifier, a clock circuit, a high-pass filter, a correlated double sampling demodulation circuit, a sample-and-hold circuit, and four vertical Hall devices, wherein the four vertical Hall devices are respectively two X-axis vertical Hall devices and two Y-axis vertical Hall devices, the two X-axis vertical Hall devices and the two Y-axis vertical Hall devices are respectively connected to a rotating current modulation circuit, the four vertical Hall devices are connected to the input end of the amplifier through the rotating current modulation circuits connected thereto, the clock circuit is a four-phase sequential clock circuit, the timing of the rotating current modulation of the X-axis vertical Hall device and the Y-axis vertical Hall device with the rotating current modulation circuit is controlled by the clock circuit, the output end of the amplifier is connected to the input end of the correlated double sampling demodulation circuit through the high-pass filter, the output end of the correlated double sampling demodulation circuit is connected to two sample-and-hold circuits, and the two sample-and-hold circuits are respectively connected to the low-pass filter.
[0005] The rotating current modulation circuit includes eight NMOS tubes, namely, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube. The vertical Hall device includes an A terminal, a B terminal, a C terminal and a D terminal. The gates of the first NMOS tube and the second NMOS tube are connected in series, the gates of the third NMOS tube and the fourth NMOS tube are connected in series, the gates of the fifth NMOS tube and the sixth NMOS tube are connected in series, and the gates of the seventh NMOS tube and the eighth NMOS tube are connected in series. The gates of the eight NMOS tubes are controlled by the clock circuit. The source and substrate of the first NMOS tube are connected to the A terminal of the vertical Hall device. The drain of the first NMOS tube is connected to the voltage source V DD The source and substrate of the second NMOS tube are connected to the ground, the drain of the second NMOS tube is connected to the C end of the vertical Hall device, the source and substrate of the third NMOS tube are connected to the B end of the vertical Hall device, the drain of the third NMOS tube is the V1 output end, the source and substrate of the fourth NMOS tube are connected to the D end of the vertical Hall device, the drain of the fourth NMOS tube is the V2 output end, the source and substrate of the fifth NMOS tube are connected to the B end of the vertical Hall device, and the drain of the fifth NMOS tube is connected to the voltage source V DD The source and substrate of the sixth NMOS tube are grounded, the drain of the sixth NMOS tube is connected to the D end of the vertical Hall device, the source and substrate of the seventh NMOS tube are connected to the A end of the vertical Hall device, the drain of the seventh NMOS tube is connected in series with the drain of the third NMOS tube, the source and substrate of the eighth NMOS tube are connected to the C end of the vertical Hall device, and the drain of the eighth NMOS tube is connected in series with the drain of the fourth NMOS tube.
[0006] The correlated double sampling demodulation circuit is a switched capacitor circuit, which includes an operational amplifier and a switch tube, and the switch tube is controlled by the clock circuit.
[0007] The amplifier is a differential-differential amplifier.
[0008] A second-stage amplifier is connected between the high-pass filter and the amplifier.
[0009] The beneficial effect of the present invention is that the present invention is a Hall circuit based on a vertical Hall device, which adopts a combination of two-phase rotating current modulation and correlated double sampling demodulation technology to effectively eliminate the offset and 1 / f noise of the Hall device and the amplifier; at the same time, multiplexed signals are used to perform the same amplification processing on the Hall signals of the X-axis and the Y-axis, thereby avoiding errors caused by inconsistent amplification of the two-axis Hall signals. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0011] Figure 1 This is a circuit block diagram of a Hall circuit based on a vertical Hall device of the present invention.
[0012] Figure 2 It is a timing diagram of the clock circuit of the present utility model.
[0013] Figure 3 It is a circuit diagram of the rotating current modulation circuit of the utility model.
[0014] Figure 4 The utility model is a circuit diagram of a correlated double sampling demodulation circuit. DETAILED DESCRIPTION
[0015] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.
[0016] The utility model discloses a Hall circuit based on a vertical Hall device, comprising a low-pass filter, an amplifier, a clock circuit, a high-pass filter, a correlated double sampling demodulation circuit, a sample-and-hold circuit, and four vertical Hall devices, wherein the four vertical Hall devices are two X-axis vertical Hall devices H X1 、H X2 and two Y-axis vertical Hall devices H Y1 、H Y2 , two X-axis vertical Hall devices H X1 、H X2 and two Y-axis vertical Hall devices H Y1 、H Y2 Each of the four vertical Hall devices H is connected to a rotating current modulation circuit. X1 、H X2 、H Y1 、H Y2 The respective rotating current modulation circuits are connected to the input end of the amplifier, and the amplifier is a differential-differential amplifier.
[0017] The two vertical Hall devices on the X and Y axes are simultaneously modulated by rotating currents. The two Hall signals, mixed with offset and 1 / f low-frequency noise, are input to the two pairs of differential inputs of a differential-differential amplifier for amplification. The rotating current modulation circuit shifts the Hall signal spectrum from low frequency to high frequency, causing the polarity of the Hall signal to change with the clock signal, thus separating the Hall signal from the DC offset and 1 / f low-frequency noise, which have constant polarity.
[0018] In order to ensure the same amplification gain for the X-axis and Y-axis Hall signals and reduce the circuit area and power consumption, the clock circuit is a four-phase sequential clock circuit. The X-axis vertical Hall device and the Y-axis vertical Hall device are controlled by the clock circuit and the timing of the rotating current modulation circuit. Specifically, a four-phase sequential clock clk x1 、clk x2 and clk y1 、clk y2 The X-axis and Y-axis Hall signals are controlled separately to generate two-phase rotating currents. During the first and second phases of the four-phase sequential clock, the two vertical Hall devices on the X-axis simultaneously modulate the two-phase rotating currents. During the third and fourth phases of the four-phase sequential clock, the two vertical Hall devices on the Y-axis simultaneously modulate the two-phase rotating currents. Therefore, the X-axis and Y-axis Hall signals are staggered in timing. After amplification by a differential-differential amplifier, the two Hall signals are multiplexed into a single output signal. Since the offset voltage polarity of coaxial Hall devices can be opposite, the Hall offset can be reduced by simultaneously feeding the two coaxial Hall signals, mixed with the offset signal, into the two pairs of differential inputs of the differential-differential amplifier.
[0019] The output of the amplifier is connected to the input of a correlated double sampling demodulation circuit via a high-pass filter. The correlated double sampling demodulation circuit performs two sampling operations and subtracts the first sampling value from the second sampling value, thereby eliminating offset and 1 / f noise while restoring the Hall signal to a low frequency. The output of the correlated double sampling demodulation circuit is connected to two sample-and-hold circuits, each of which is connected to a low-pass filter. A second-stage amplifier is connected between the high-pass filter and the amplifier.
[0020] The rotating current modulation circuit includes eight NMOS transistors, a vertical Hall device H, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7 and an eighth NMOS transistor M8. The vertical Hall device H includes an A terminal, a B terminal, a C terminal and a D terminal. The gates of the first NMOS transistor M1 and the second NMOS transistor M2 are connected in series, the gates of the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected in series, the gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are connected in series, and the gates of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 are connected in series. The gates of the eight NMOS transistors are controlled by the clock circuit. The source and substrate of the first NMOS transistor M1 are connected to the A terminal of the vertical Hall device H. The drain of the first NMOS transistor M1 is connected to the voltage source V DDThe source and substrate of the second NMOS tube M2 are grounded, the drain of the second NMOS tube M2 is connected to the C end of the vertical Hall device H, the source and substrate of the third NMOS tube M3 are connected to the B end of the vertical Hall device H, the drain of the third NMOS tube M3 is the V1 output end, the source and substrate of the fourth NMOS tube M4 are connected to the D end of the vertical Hall device H, the drain of the fourth NMOS tube M4 is the V2 output end, the source and substrate of the fifth NMOS tube M5 are connected to the B end of the vertical Hall device H, and the drain of the fifth NMOS tube M5 is connected to the voltage source V DD The source and substrate of the sixth NMOS transistor M6 are connected to the ground, the drain of the sixth NMOS transistor M6 is connected to the D terminal of the vertical Hall device H, the source and substrate of the seventh NMOS transistor M7 are connected to the A terminal of the vertical Hall device H, the drain of the seventh NMOS transistor M7 is connected in series with the drain of the third NMOS transistor, the source and substrate of the eighth NMOS transistor M8 are connected to the C terminal of the vertical Hall device H, the drain of the eighth NMOS transistor M8 is connected in series with the drain of the fourth NMOS transistor M4, V DD is the voltage source, and GND is the ground terminal.
[0021] clk x1 and clk x2 The clock signal is used to control the rotation current of the two Hall devices on the X axis. y1 、clk y2 The clock signal is used to control the rotation current of the two Hall devices on the Y axis. The four control clocks form a four-phase sequential pulse. x1 When the level is high, NMOS tubes M1 and M2 are turned on, and the bias current I flows from the A terminal of the Hall device to the C terminal, and a Hall voltage is generated between the B terminal and the D terminal. At this time, NMOS tubes M3 and M4 are on clk x1 When clk x2 When the level is high, NMOS tubes M5 and M6 are turned on, and the bias current I flows from the B end of the Hall device to the D end, and a Hall voltage is generated between the A end and the C end. At this time, NMOS tubes M7 and M8 are on clk x2 When the clock signal clk x1 and clk x2 When the current in the Hall device rotates from 0° to 90°, the output Hall voltage V H The polarity changes periodically, and the Hall signal is modulated from low frequency to high frequency. OP The polarity of remains unchanged during the rotating current process, and it is superimposed on the input offset voltage of the differential-differential amplifier and can be eliminated by the subsequent high-pass filtering and correlated double sampling demodulation circuit.
[0022] When the clock signal clky1 and clk y2 When the voltages change to high level sequentially over time, the two vertical Hall devices on the Y-axis perform rotating current modulation at the same time, and the working conditions are exactly the same as those in the above case.
[0023] The correlated double sampling demodulation circuit is a switched capacitor circuit, which includes an operational amplifier A and a switch tube, and the switch tube is controlled by the clock circuit. C1 and C2 are sampling capacitors, M a 、M b 、M c It is an NMOS switch tube. a 、M b 、M c It is controlled by two complementary clocks clk1 and clk2. The waveforms of clk1 and clk2 are as follows Figure 2 As shown in Figure 1, it is related to the 4-phase sequential clock in the rotating current modulation circuit. When clk1 is high and clk2 is low, the switch M a and M c Closed, M b Disconnected, the input signal charges and discharges capacitors C1 and C2. in is the input terminal, V out For the output terminal, V DD is the voltage source, and GND is the ground terminal.
[0024] The correlated double sampling circuit outputs twice the Hall voltage in the second phase of the clock clk1, and can effectively eliminate the Hall offset and the offset of the op amp itself. Therefore, in the subsequent sampling and holding circuits of the X-axis and Y-axis signals, clk is used. x2 and clk y2 By sampling the high level of the X axis and the Y axis, the amplified Hall signals can be obtained respectively. Finally, the sampled and held signals are sent to a low-pass filter to remove the high-frequency components and obtain a low-distortion Hall voltage.
[0025] The differential-differential amplifier, high-pass filter, sample-and-hold circuit, and low-pass filter circuits in the present invention may all adopt conventional circuits, which will not be described in detail here.
[0026] Based on the above-mentioned ideal embodiment of the present invention, and in accordance with the above description, relevant personnel can make various changes and modifications without departing from the technical scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, but must be determined according to the scope of the claims.
Claims
1. A Hall circuit based on a vertical Hall device, characterized in that: The invention comprises a low-pass filter, an amplifier, a clock circuit, a high-pass filter, a correlated double sampling demodulation circuit, a sample-and-hold circuit, and four vertical Hall devices. The four vertical Hall devices are respectively two X-axis vertical Hall devices and two Y-axis vertical Hall devices. The two X-axis vertical Hall devices and the two Y-axis vertical Hall devices are respectively connected to a rotating current modulation circuit. The four vertical Hall devices are connected to the input end of the amplifier through the rotating current modulation circuits connected to them. The clock circuit is a four-phase sequential clock circuit. The timing of the rotating current modulation of the X-axis vertical Hall device and the Y-axis vertical Hall device is controlled by the clock circuit. The output end of the amplifier is connected to the input end of the correlated double sampling demodulation circuit through the high-pass filter. The output end of the correlated double sampling demodulation circuit is connected to two sample-and-hold circuits. The two sample-and-hold circuits are respectively connected to the low-pass filter.
2. The Hall circuit based on a vertical Hall device according to claim 1, wherein: The rotating current modulation circuit includes eight NMOS tubes, namely, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube. The vertical Hall device includes an A terminal, a B terminal, a C terminal and a D terminal. The gates of the first NMOS tube and the second NMOS tube are connected in series, the gates of the third NMOS tube and the fourth NMOS tube are connected in series, the gates of the fifth NMOS tube and the sixth NMOS tube are connected in series, and the gates of the seventh NMOS tube and the eighth NMOS tube are connected in series. The gates of the eight NMOS tubes are controlled by the clock circuit. The source and substrate of the first NMOS tube are connected to the A terminal of the vertical Hall device. The drain of the first NMOS tube is connected to the voltage source V DD The source and substrate of the second NMOS tube are connected to the ground, the drain of the second NMOS tube is connected to the C end of the vertical Hall device, the source and substrate of the third NMOS tube are connected to the B end of the vertical Hall device, the drain of the third NMOS tube is the V1 output end, the source and substrate of the fourth NMOS tube are connected to the D end of the vertical Hall device, the drain of the fourth NMOS tube is the V2 output end, the source and substrate of the fifth NMOS tube are connected to the B end of the vertical Hall device, and the drain of the fifth NMOS tube is connected to the voltage source V DD The source and substrate of the sixth NMOS tube are grounded, the drain of the sixth NMOS tube is connected to the D end of the vertical Hall device, the source and substrate of the seventh NMOS tube are connected to the A end of the vertical Hall device, the drain of the seventh NMOS tube is connected in series with the drain of the third NMOS tube, the source and substrate of the eighth NMOS tube are connected to the C end of the vertical Hall device, and the drain of the eighth NMOS tube is connected in series with the drain of the fourth NMOS tube.
3. The Hall circuit based on a vertical Hall device according to claim 1, wherein: The correlated double sampling demodulation circuit is a switched capacitor circuit, which includes an operational amplifier and a switch tube, and the switch tube is controlled by the clock circuit.
4. The Hall circuit based on a vertical Hall device according to claim 1, wherein: The amplifier is a differential-differential amplifier.
5. The Hall circuit based on a vertical Hall device according to claim 1, wherein: A second-stage amplifier is connected between the high-pass filter and the amplifier.