Power management circuit, chip and USB-OTG equipment

Abstract

The utility model discloses a power supply management circuit, a chip and USB-OTG equipment, and relates to the technical field of USB interfaces, the power supply management circuit comprises a detection circuit and an on-off circuit; the detection circuit is respectively connected with the USB detection port and the on-off circuit, and the on-off circuit is respectively connected with the power supply and the USB power supply port; the detection circuit is used for generating and sending a cut-off signal to the on-off circuit when the insertion of the USB peripheral is not detected; and the on-off circuit is used for cutting off the connection between the power supply and the USB peripheral when receiving the cut-off signal. When the detection circuit provided by the utility model detects that no USB peripheral is inserted, the detection circuit sends the cut-off signal to the on-off circuit, and the on-off circuit cuts off the connection between the USB power interface and the power supply when receiving the cut-off signal, so that the problem of electric leakage of the exposed USB interface is solved, and meanwhile, the interface resource of the main control chip is not occupied.

Description

Technical Field

[0001] The utility model relates to the technical field of USB interfaces, and in particular to a power management circuit, a chip and a USB-OTG device. Background Art

[0002] Existing Universal Serial Bus On-The-Go (USB-OTG) power supply methods mostly rely on the device directly outputting 5V power to the Universal Serial Bus (USB) peripheral. This power supply method has the following drawbacks: the USB interface power supply always outputs 5V, and the USB terminal is exposed to the outside of the device, posing a risk of leakage. Another power supply method uses the USB terminal's "USB_ID" to connect to an I / O port on the main control chip as a detection port for the USB-OTG peripheral. The main control chip reads this voltage level to control whether the 5V power supply is supplied to the USB port. However, this power management method requires two I / O ports on the main control chip.

[0003] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Utility Model Content

[0004] The main purpose of the utility model is to propose a power management circuit, chip and USB-OTG device, aiming to solve the leakage risk problem of USB-OTG peripherals.

[0005] To achieve the above-mentioned purpose, the present invention proposes a power management circuit, which includes: a detection circuit and an on-off circuit;

[0006] Wherein, the detection circuit is connected to the USB detection port and the on-off circuit respectively, and the on-off circuit is connected to the power supply and the USB power port respectively;

[0007] The detection circuit is used to generate and send a cutoff signal to the on-off circuit when no USB peripheral device is detected to be inserted;

[0008] The on-off circuit is used to cut off the connection between the power supply and the USB peripheral device when receiving the cut-off signal.

[0009] In one embodiment, the power management circuit further includes: a driving circuit;

[0010] Wherein, the driving circuit is connected to the detection circuit and the on-off circuit respectively;

[0011] The detection circuit is configured to generate and send the cutoff signal to the driving circuit when no USB peripheral device is detected to be inserted;

[0012] The driving circuit is used to cut off the power supply circuit of the on-off circuit when receiving the cut-off signal.

[0013] In one embodiment, the power management circuit further includes: a clamping circuit;

[0014] Wherein, the clamping circuit is connected to the on-off circuit and the power supply respectively;

[0015] The clamping circuit is used to clamp the voltage of the control terminal of the on-off circuit when the power supply circuit of the on-off circuit is cut off;

[0016] The on-off circuit is further configured to cut off the connection between the power supply and the USB peripheral device when the voltage difference between the power supply and the control terminal of the on-off circuit is less than or equal to a preset threshold.

[0017] In one embodiment, the detection circuit includes: a first resistor, a second resistor and a PNP transistor;

[0018] Among them, one end of the first resistor is connected to the USB power port, the other end of the first resistor is connected to the second resistor and the base of the PNP transistor respectively, the other end of the second resistor is connected to the power supply, the emitter of the PNP transistor is connected to the power supply, and the collector of the PNP transistor is connected to the drive circuit.

[0019] In one embodiment, the driving circuit includes: a third resistor, a fourth resistor and an NPN transistor;

[0020] Among them, one end of the third resistor is grounded, the other end of the third resistor is respectively connected to the fourth resistor and the collector of the PNP transistor, the other end of the fourth resistor is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, and the collector of the NPN transistor is connected to the clamping circuit.

[0021] In one embodiment, the clamping circuit includes: a fifth resistor and a sixth resistor;

[0022] Among them, one end of the fifth resistor is connected to the collector of the NPN transistor, the other end of the fifth resistor is respectively connected to the sixth resistor and the control end of the on-off circuit, and the other end of the sixth resistor is respectively connected to the on-off circuit and the power supply.

[0023] In one embodiment, the on-off circuit includes: a MOS transistor;

[0024] The gate of the MOS transistor is connected to the fifth resistor and the sixth resistor respectively, the drain of the MOS transistor is connected to the USB power port, and the source of the MOS transistor is connected to the power supply and the sixth resistor respectively.

[0025] In one embodiment, the detection circuit is further configured to generate and send a conduction signal to the on-off circuit when detecting that the USB peripheral device is inserted;

[0026] The on-off circuit is further configured to conduct the connection between the USB power port and the power source when receiving the on-signal.

[0027] The present invention also provides a power management chip, which includes the power management circuit described above.

[0028] The present invention also provides a USB-OTG device, which includes the power management circuit described above.

[0029] The technical solution of the present invention solves the problem of leakage of the USB peripheral interface by adopting a power management circuit. The power management circuit includes: a detection circuit and an on-off circuit; the detection circuit is respectively connected to the USB detection port and the on-off circuit, and the on-off circuit is respectively connected to the power supply and the USB power port; the detection circuit is used to generate and send a conduction signal to the on-off circuit when no USB peripheral is detected to be inserted; the on-off circuit is used to conduct the connection between the power supply and the USB peripheral when receiving the conduction signal; the detection circuit provided by the utility model sends a cut-off signal to the on-off circuit when detecting that no USB peripheral is inserted, and the on-off circuit disconnects the USB power interface and the power supply when receiving the cut-off signal, thereby solving the problem of leakage of the exposed USB interface and eliminating the need to occupy the interface resources of the main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a module of an embodiment of a power management circuit provided by the present utility model;

[0032] Figure 2 This is a diagram of OTG cable connection;

[0033] Figure 3 A schematic diagram of a module of a first embodiment of a power management circuit provided by the present utility model;

[0034] Figure 4 This is a circuit structure diagram of an embodiment of a power management circuit provided by the present utility model.

[0035] Description of Figure Numbers:

[0036] Label name Label name 100 On-off circuit VCC power supply 200 Detection circuit Q1 PNP transistor 300 USB interface Q2 NPN transistor 400 power supply Q3 MOS tube 500 Drive circuit R1~R6 The first to sixth resistors 600 Clamping circuit

[0037] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0038] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0040] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0041] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme in which A and B are satisfied at the same time. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] Existing Universal Serial Bus On-The-Go (USB-OTG) power supply methods mostly rely on the device directly outputting 5V power to the USB peripheral. This power supply method has the following drawbacks: the USB interface power supply always outputs 5V, and the USB terminal is exposed to the outside of the device, posing a risk of leakage. Another power supply method uses the USB terminal's "USB_ID" to connect to an I / O port on the main control chip as a detection port for the USB-OTG peripheral. The main control chip reads this voltage level to control whether the 5V power supply is supplied to the USB port. However, this power management method requires two I / O ports on the main control chip.

[0043] The utility model provides a power management circuit.

[0044] See also Figure 1 In one embodiment of the present invention, the power management circuit includes: a detection circuit 200 and an on-off circuit 100; the detection circuit is connected to the USB300 detection port and the on-off circuit 100 respectively, and the on-off circuit 100 is connected to the power supply 400 and the USB300 power port respectively; the detection circuit 200 is used to generate and send a conduction signal to the on-off circuit 100 when no USB peripheral device is detected to be inserted; the on-off circuit 100 is used to conduct the connection between the power supply 400 and the USB peripheral when receiving the conduction signal; the detection circuit 200 provided by the utility model sends a cut-off signal to the on-off circuit 100 when it detects that no USB peripheral is inserted, and the on-off circuit 100 disconnects the connection between the USB300 power interface and the power supply 400 when receiving the cut-off signal, thereby solving the problem of leakage of the exposed USB interface without occupying the interface resources of the main control chip.

[0045] The detection circuit 200 is also used to generate and send the conduction signal to the on-off circuit 100 when it detects that the USB peripheral is inserted; the on-off circuit 100 is also used to conduct the connection between the USB300 power port and the power supply 400 when receiving the conduction signal.

[0046] It should be noted that the Universal Serial Bus (USB) is a serial bus standard and a technical specification for input and output interfaces. It is widely used in information communication products such as personal computers and mobile devices. This embodiment takes Micro USB as an example.

[0047] It should be understood that if Figure 2As shown in the functional wiring diagram of an OTG data cable, its internal core has four wires, connecting the USB Type-A port to the Micro USB connector. These four wires are two data lines (usually green and white, corresponding to D+ and D-), one power line (VBUS, usually red), and one ground line (GND, usually black). We can see that the Micro USB connector has an additional ID pin. Connecting this pin to the ground line with a wire creates a USB-OTG data cable.

[0048] Taking a computer as an example, there are many USB interfaces on the computer host. These USB interfaces are used to insert USB-OTG data cables to connect mobile phones, mice, keyboards, etc. The power port Vcc of these USB interfaces on the computer is directly connected to the computer power supply 400. When no USB-OTG data cable is inserted, the USB interface on the computer is exposed, and there may be a risk of leakage.

[0049] In this embodiment, the detection circuit 200 is connected to the ID detection port of the USB300 interface on the computer. When no USB-OTG data cable is inserted, the pin of the detection port is suspended. The detection circuit 200 generates and sends a cut-off signal to the on-off circuit 100. The on-off circuit 100 disconnects the connection between the computer power supply 400 and the Vcc power port on the USB300 interface on the computer. At this time, the USB300 interface on the computer has no voltage and no risk of leakage. When the USB-OTG data cable is inserted, according to the internal structure of the above-mentioned USB-OTG data cable, the "USB_ID" pin of the USB-OTG data cable is connected to "GND" because the Micro The USB connector is inserted into the USB interface of the computer, so the ID detection port of the USB interface on the computer is also grounded. When the detection circuit 200 detects that the ID detection port of the USB interface on the computer is grounded, it sends a conduction signal to the on-off circuit 100. The on-off circuit 100 connects the USB interface on the computer and the power supply 400. Because the USB-OTG data cable is inserted into the USB300 interface of the computer, the computer supplies power to the USB-OTG data cable peripheral.

[0050] It should be understood that the specific structures of the detection module 200 and the on-off module 100 are not limited in this embodiment; for example, transistors, MOS transistors, integrated circuits, etc. may be used. The power management circuit is not limited to computers; devices with USB 300 ports, such as cameras, televisions, and mobile phones, can also use this technical solution.

[0051] Figure 3 This is a functional module diagram of the first embodiment of the chip protection circuit proposed in the embodiment of the present utility model.

[0052] The power management circuit also includes: a clamping circuit 600; wherein the clamping circuit 600 is connected to the on-off circuit 100 and the power supply 400 respectively; the clamping circuit 600 is used to clamp the voltage of the control end of the on-off circuit 100 when the power supply circuit of the on-off circuit 100 is cut off; the on-off circuit 100 is also used to cut off the connection between the power supply 400 and the control end of the on-off circuit 100 when the voltage difference between the power supply 400 and the control end of the on-off circuit 100 is less than or equal to a preset threshold.

[0053] It should be noted that the on-off circuit 100 is used to disconnect the connection between the power supply 400 and the USB peripheral device when receiving the cut-off signal, and the clamping circuit 600 is used to control the voltage difference between the input end and the control end of the on-off circuit 100. When the driving circuit 500 turns on the power supply circuit of the on-off circuit 100, the clamping circuit 600 controls the voltage difference between the input end and the control end of the on-off circuit 100 on the one hand, and protects the components of the on-off circuit 100 on the other hand. When the voltage difference in the on-off circuit 100 is greater than 0V, the on-off circuit 100 is turned on. When the driving circuit 500 disconnects the power supply circuit of the on-off circuit 100, the control end of the on-off circuit 100 is also connected to the power supply 400. The clamping circuit 600 controls the voltages of the input end and the control end of the on-off circuit 100 to be equal, and the on-off circuit 100 is disconnected.

[0054] like Figure 4 As shown, the clamping circuit 600 includes: a fifth resistor R5 and a sixth resistor R6; wherein, one end of the fifth resistor R5 is connected to the collector of the NPN transistor Q2, and the other end of the fifth resistor is respectively connected to the sixth resistor R6 and the control end of the on-off circuit 100, and the other end of the sixth resistor R6 is respectively connected to the on-off circuit 100 and the power supply 400.

[0055] The on-off circuit 100 includes: a MOS transistor Q3; wherein the gate of the MOS transistor Q3 is connected to the fifth resistor and the sixth resistor respectively, the drain of the MOS transistor Q3 is connected to the USB300 power port, and the source of the MOS transistor Q3 is connected to the power supply 400 and the sixth resistor R6 respectively.

[0056] It should be noted that the preset threshold is set according to the specific components of the on-off circuit. The preset threshold is 0V. The MOS tube is a P-channel MOS tube. When no USB-OTG data cable is inserted into the USB interface on the computer, the drive circuit 500 cuts off the loop of the on-off circuit 100, that is, one end of the fifth resistor R5 is suspended. At this time, the gate and source of the MOS tube are connected to the power supply 400, and the power supply 400 and the fifth resistor R5 and the sixth resistor R6 cannot form a loop. Therefore, there is no voltage drop between the gate and source of the MOS tube, so the MOS tube Q3 is cut off, and the power supply 400 is disconnected from the power port of the USB300 interface on the computer. At this time, when no peripheral device is inserted, the USB300 interface will not have leakage problems. When the USB-OTG data cable is inserted into the USB interface on the computer, the driving circuit 500 turns on the loop of the on-off circuit 100, that is, one end of the fifth resistor R5 is grounded. At this time, the fifth resistor and the sixth resistor form a clamping circuit 600, which controls the voltage difference between the gate and the source of the MOS tube, and the voltage difference between the gate voltage and the source is less than 0V. The MOS tube is turned on, and the power supply 400 is connected to the power port of the USB300 interface on the computer to continuously supply power to the USB-OTG data cable peripherals.

[0057] Specifically, the clamping circuit 600 is used to control the voltage difference between the gate and source of the MOS tube and to protect the MOS tube. When the power supply voltage is too high, if there is no voltage divider between the fifth resistor and the sixth resistor, the limit voltage of the MOS tube may be exceeded, and the MOS tube may be burned.

[0058] Optionally, the fifth and sixth resistors may be replaced by sliding rheostats or voltage-stabilizing diodes. The MOS transistor may be replaced by a PNP transistor, with the gate of the MOS transistor Q3 serving as the base of the transistor, the drain of the MOS transistor Q3 serving as the collector of the transistor, and the source of the MOS transistor Q3 serving as the emitter of the transistor. The MOS transistor Q3 may also be replaced by an integrated chip having the same operating principle.

[0059] It can be understood that when the driving circuit 500 changes from conducting the loop of the on-off circuit 100 to cutting off the loop of the on-off circuit 100, the fifth resistor R5 is suspended. At this time, the gate and source of the MOS tube are connected to the power supply 400, and the power supply 400 and the fifth resistor R5 and the sixth resistor R6 cannot form a loop. Therefore, the voltage drop between the gate and source of the MOS tube becomes 0V, the MOS tube Q3 is cut off, and the power supply 400 is disconnected from the power port of the USB300 interface on the computer. At this time, the power port of the USB300 interface on the computer has no voltage, which solves the leakage problem and does not occupy the pin resources of the computer's main controller.

[0060] like Figure 4 FIG. 2 is a circuit diagram of a second embodiment of a chip protection circuit according to an embodiment of the present invention.

[0061] Based on the above-mentioned first embodiment, a second embodiment of the power management circuit of the present invention is proposed.

[0062] In this embodiment, the detection circuit 200 includes: a first resistor R1, a second resistor R2 and a PNP transistor Q1; wherein, one end of the first resistor is connected to the USB300 power port, the other end of the first resistor R1 is respectively connected to the second resistor and the base of the PNP transistor Q1, the other end of the second resistor is connected to the power supply 400, the emitter of the PNP transistor Q1 is connected to the power supply 400, and the collector of the PNP transistor Q1 is connected to the drive circuit 500.

[0063] It should be noted that the detection circuit 200 is connected to the ID detection port of the USB300 interface on the computer. When the USB-OTG data cable is not inserted, the detection circuit 200 detects that the ID detection port of the USB300 interface on the computer is suspended, and the base of the PNP transistor Q1 is connected to the power supply 400VCC, so the PNP transistor is cut off and the power supply voltage is not transmitted to the drive circuit 500. The collector of the PNP transistor Q1 has no voltage, and the cut-off signal is transmitted to the drive circuit 500; when the USB-OTG data cable is inserted into the USB300 interface on the computer, according to the connection between the ID pin and the GND pin of the USB-OTG data cable, the detection circuit 200 detects that the ID detection port of the USB interface on the computer is grounded. After the voltage division of the first resistor R1 and the second resistor R2, the voltage of the emitter of the PNP transistor is greater than the base, and the PNP transistor Q1 is turned on, and the power supply voltage is output to the drive circuit 500, that is, the turn-on signal is sent to the drive circuit 500.

[0064] Optionally, the first resistor and the second resistor may be adjustable resistors, and the PNP transistor Q1 may be replaced by a MOS transistor, where the gate of the MOS transistor serves as the base of the transistor, the drain of the MOS transistor serves as the collector of the transistor, and the source of the MOS transistor serves as the emitter of the transistor. The PNP transistor Q1 may also be replaced by an integrated chip having the same operating principle.

[0065] It is understood that when the user unplugs the USB-OTG data cable, the detection circuit 200 detects that the ID detection port of the USB300 interface on the computer is floating. The voltage difference between the base and emitter of the PNP transistor becomes 0V, and the PNP transistor changes from on to off. The collector of the PNP transistor has no voltage, and a cutoff signal is transmitted to the driving circuit 500. When the user unplugs the USB-OTG data cable from the computer's USB300 port, the detection circuit 200 immediately changes the transmission signal without delay and responds quickly; the same is true when the user plugs the USB-OTG data cable into the computer's USB300 port.

[0066] like Figure 4 FIG. 2 is a circuit structure diagram of a third embodiment of a chip protection circuit according to an embodiment of the present invention.

[0067] Based on the above second embodiment, a third embodiment of the power management circuit of the present invention is proposed.

[0068] The power management circuit also includes: a drive circuit 500; wherein the drive circuit 500 is connected to the detection circuit 200 and the on-off circuit 100 respectively; the detection circuit 200 is used to generate and send the cutoff signal to the drive circuit 500 when no USB peripheral is detected to be inserted; the drive circuit 500 is used to cut off the power supply circuit of the on-off circuit 100 when receiving the cutoff signal.

[0069] It can be understood that the driving circuit 500 is used to disconnect the power supply circuit of the control end of the on-off circuit 100 when receiving the cut-off signal, so that the on-off circuit 100 disconnects the connection between the USB300 interface on the computer and the power supply 400, and when receiving the on-signal, turns on the power supply circuit of the on-off circuit 100, so that the on-off circuit 100 turns on the connection between the USB300 interface on the computer and the power supply 400.

[0070] In this embodiment, the driving circuit 500 includes: a third resistor R3, a fourth resistor R4 and an NPN transistor Q2; wherein, one end of the third resistor R3 is grounded, and the other end of the third resistor R3 is respectively connected to the fourth resistor R4 and the collector of the PNP transistor Q2, the other end of the fourth resistor is connected to the base of the NPN transistor Q2, the emitter of the NPN transistor Q2 is grounded, and the collector of the NPN transistor Q2 is connected to the clamping circuit 600.

[0071] It should be noted that when the USB-OTG data cable is not inserted into the USB300 interface of the computer, the detection circuit 200 transmits a cut-off signal to the drive circuit 500. The cut-off signal is that there is no voltage at the collector of the PNP transistor. At this time, the third resistor R3 and the fourth resistor R4 are grounded, the base voltage of the NPN transistor Q2 is 0V, the emitter of the NPN transistor is also grounded, and the voltage is also 0V. The voltage difference between the base and emitter of the NPN transistor is 0V, the NPN transistor Q2 is cut off, and one end of the fifth resistor R5 is left floating. The on-off circuit 100 cannot form a complete power supply circuit. -When the OTG data cable is inserted into the USB300 interface of the computer, the detection circuit 200 transmits a conduction signal to the driving circuit 500. The conduction signal means that the driving circuit 500 is connected to the power supply 400. At this time, the third resistor R3 and the fourth resistor R4 are connected to the power supply, the base voltage of the NPN transistor Q2 is the power supply voltage 5V, the emitter of the NPN transistor is also grounded, and the voltage is 0V. The voltage difference between the base and emitter of the NPN transistor Q2 is 5V, the NPN transistor Q2 is turned on, one end of the fifth resistor is grounded, and the on-off circuit 100 and the power supply 400 form a complete power supply circuit.

[0072] Specifically, the third resistor and the fourth resistor are used to protect the NPN transistor, and the NPN transistor is used to conduct the connection between the control end of the on-off circuit 100 and GND. The driving circuit 500 can be replaced by a MOS tube or an integrated chip with the same function.

[0073] It is understood that when the user unplugs the USB-OTG data cable, the base of the NPN transistor receives the signal from the detection circuit 200 that the power supply 400 is cut off, and the base is grounded. The driver circuit 500 also immediately cuts off the power supply 400 to the on-off circuit 100 and the clamping circuit 600. When the user unplugs the USB-OTG data cable from the computer's USB 300 port, the driver circuit 500 immediately switches to conducting the power supply circuit of the on-off circuit 100; the same is true when the user plugs the USB-OTG data cable into the computer's USB 300 port. This ensures that the computer's USB port does not leak electricity while not affecting the user's use.

[0074] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0075] The present utility model also proposes a power management chip, which includes a power management circuit. The specific structure of the power management circuit refers to the above-mentioned embodiment. Since the power management chip adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be described one by one here.

[0076] The present invention also proposes a USB-OTG device, which includes a power management circuit. The specific structure of the power management circuit refers to the above embodiment. Since the present USB-OTG device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0077] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A power management circuit, characterized in that: The power management circuit includes: a detection circuit and an on-off circuit; Wherein, the detection circuit is connected to the USB detection port and the on-off circuit respectively, and the on-off circuit is connected to the power supply and the USB power port respectively; The detection circuit is used to generate and send a cutoff signal to the on-off circuit when no USB peripheral device is detected to be inserted; The on-off circuit is used to cut off the connection between the power supply and the USB peripheral device when receiving the cut-off signal.

2. The power management circuit according to claim 1, wherein: The power management circuit further includes: a driving circuit; Wherein, the driving circuit is connected to the detection circuit and the on-off circuit respectively; The detection circuit is configured to generate and send the cutoff signal to the driving circuit when no USB peripheral device is detected to be inserted; The driving circuit is used to cut off the power supply circuit of the on-off circuit when receiving the cut-off signal.

3. The power management circuit according to claim 2, wherein: The power management circuit further includes: a clamping circuit; Wherein, the clamping circuit is connected to the on-off circuit and the power supply respectively; The clamping circuit is used to clamp the voltage of the control terminal of the on-off circuit when the power supply circuit of the on-off circuit is cut off; The on-off circuit is further configured to cut off the connection between the power supply and the USB peripheral device when the voltage difference between the power supply and the control terminal of the on-off circuit is less than or equal to a preset threshold.

4. The power management circuit according to claim 3, wherein: The detection circuit includes: a first resistor, a second resistor and a PNP transistor; Among them, one end of the first resistor is connected to the USB power port, the other end of the first resistor is connected to the second resistor and the base of the PNP transistor respectively, the other end of the second resistor is connected to the power supply, the emitter of the PNP transistor is connected to the power supply, and the collector of the PNP transistor is connected to the drive circuit.

5. The power management circuit according to claim 4, wherein: The driving circuit includes: a third resistor, a fourth resistor and an NPN transistor; Among them, one end of the third resistor is grounded, the other end of the third resistor is respectively connected to the fourth resistor and the collector of the PNP transistor, the other end of the fourth resistor is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, and the collector of the NPN transistor is connected to the clamping circuit.

6. The power management circuit according to claim 5, wherein: The clamping circuit includes: a fifth resistor and a sixth resistor; Among them, one end of the fifth resistor is connected to the collector of the NPN transistor, the other end of the fifth resistor is respectively connected to the sixth resistor and the control end of the on-off circuit, and the other end of the sixth resistor is respectively connected to the on-off circuit and the power supply.

7. The power management circuit according to claim 6, wherein: The on-off circuit includes: a MOS tube; The gate of the MOS transistor is connected to the fifth resistor and the sixth resistor respectively, the drain of the MOS transistor is connected to the USB power port, and the source of the MOS transistor is connected to the power supply and the sixth resistor respectively.

8. The power management circuit according to any one of claims 1 to 7, wherein: The detection circuit is further configured to generate and send a conduction signal to the on-off circuit when detecting that the USB peripheral device is inserted; The on-off circuit is further configured to conduct the connection between the USB power port and the power source when receiving the on-signal.

9. A power management chip, characterized in that: The power management chip includes the power management circuit according to any one of claims 1 to 8.

10. A USB-OTG device, characterized in that: The USB-OTG device comprises the power management circuit according to any one of claims 1 to 8.

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