Optical fiber transceiver and communication system

Abstract

The utility model discloses an optical fiber transceiver and a communication system, and belongs to the technical field of communication. The optical fiber transceiver comprises an FPGA, an optical module, a PHY chip and at least one network port connector. The FPGA comprises an IO interface unit and an SERDES interface unit; a transceiving interface of the optical module is connected with the SERDES interface unit, and a configuration interface of the optical module is connected with the IO interface unit; a transceiving interface of the PHY chip is connected with the SERDES interface unit, and a configuration interface of the PHY chip is connected with the IO interface unit; and each network port connector is connected with the PHY chip. According to the embodiment of the utility model, the data transmission rate of the optical fiber transceiver can be improved, and the communication efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of communications, in particular to an optical fiber transceiver and a communication system. Background Art

[0002] A fiber optic transceiver is a device that performs photoelectric conversion, converting electrical signals into optical signals for transmission, and similarly, converting optical signals into electrical signals for communication. Currently, fiber optic transceivers are widely used in the communications industry due to their low price and reliable communication capabilities, playing a vital role. Industries such as LED displays are facing an increasing amount of data, but the limited data transmission rate of gigabit network cables hinders communication efficiency. Utility Model Content

[0003] The utility model provides an optical fiber transceiver and a communication system to increase the data transmission rate of the optical fiber transceiver and improve communication efficiency.

[0004] In a first aspect, an embodiment of the present invention provides a fiber optic transceiver, comprising:

[0005] FPGA, including IO interface unit and SERDES interface unit;

[0006] An optical module, wherein the transceiver interface of the optical module is connected to the SERDES interface unit, and the configuration interface of the optical module is connected to the IO interface unit;

[0007] A PHY chip, wherein the transceiver interface of the PHY chip is connected to the SERDES interface unit, and the configuration interface of the PHY chip is connected to the IO interface unit;

[0008] At least one network port connector, each of the network port connectors is connected to the PHY chip.

[0009] Optionally, the model of the FPGA is: PH1A90SBG484.

[0010] Optionally, the model of the PHY chip is: YT8618C.

[0011] Optionally, the PHY chip includes a plurality of the transceiver interfaces; the plurality of the transceiver interfaces include: at least one QSGMII interface; the plurality of the transceiver interfaces further include: at least one COPPER interface or at least one COMBO interface;

[0012] The PHY chip also includes: a transmission mode configuration interface; the transmission mode configuration interface includes at least one mode configuration pin, and the PHY chip is used to determine the type and number of the transceiver interfaces for data interaction with the FPGA based on the potential of each mode configuration pin.

[0013] Optionally, the configuration interface of the PHY chip includes: a clock management pin, a data input and output management pin, an interrupt pin and a reset pin; the clock management pin, the data input and output management pin, the interrupt pin and the reset pin are respectively connected to different pins in the IO interface unit.

[0014] Optionally, the SERDES interface unit includes a first interface group and a second interface group; the first interface group is connected to a first reference clock, and the second interface group is connected to a second reference clock; the first interface group and the second interface group are respectively used to connect the transceiver interface of the optical module and the transceiver interface of the PHY chip.

[0015] Optionally, the transceiver interface of the optical module includes: a first receiving pin, a second receiving pin, a first transmitting pin, and a second transmitting pin; the first receiving pin, the second receiving pin, the first transmitting pin, and the second transmitting pin are respectively connected to different pins in the SERDES interface unit;

[0016] The configuration interface of the optical module includes: a transmission shutdown pin, a first transmission rate pin, a second transmission rate pin, a reception signal loss pin, a transmission fault pin and a module configuration pin; the transmission shutdown pin, the first transmission rate pin, the second transmission rate pin, the reception signal loss pin, the transmission fault pin and the module configuration pin are respectively connected to different pins in the IO interface unit.

[0017] Optionally, the optical module is an SFP+ optical module.

[0018] Optionally, the network port connector includes: a network transformer and a network interface, and the network transformer is connected between the PHY chip and the network interface; wherein the network transformer and the network interface are separately or integrated; and the network interface is an RJ45 interface.

[0019] In a second aspect, an embodiment of the present invention further provides a communication system, comprising: the optical fiber transceiver provided by any embodiment of the present invention.

[0020] The fiber optic transceiver provided in the embodiments of the present invention is provided with an FPGA, an optical module, a PHY chip, and at least one network port connector. The FPGA is provided with a SERDES interface unit, and the transceiver interface of the optical module and the transceiver interface of the PHY chip are both connected to the SERDES interface unit. Data transmission can be implemented based on the SERDES protocol, fully utilizing the communication channel capacity and improving transmission speed. Therefore, the embodiments of the present invention can increase the data transmission rate of the fiber optic transceiver and improve communication efficiency.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a structural diagram of a fiber optic transceiver provided by an embodiment of the present utility model;

[0024] Figure 2 This is a signal flow diagram of a fiber optic transceiver provided by an embodiment of the present utility model;

[0025] Figure 3 This is a schematic diagram of the connection relationship between an optical module and an FPGA provided by an embodiment of the present utility model;

[0026] Figure 4 This is a schematic diagram of the on-board status configuration of an optical module provided by an embodiment of the present utility model;

[0027] Figure 5 This is a schematic diagram of a mode configuration of a PHY chip provided by an embodiment of the present utility model;

[0028] Figure 6 This is a schematic diagram of the configuration of the transceiver interface and configuration interface of a PHY chip provided by an embodiment of the present utility model;

[0029] Figure 7 This is a structural diagram of a network port connector provided by an embodiment of the present utility model;

[0030] Figure 8 This is a structural diagram of an IO interface unit of an FPGA provided by an embodiment of the utility model;

[0031] Figure 9 This is a structural diagram of a SERDES interface unit of an FPGA provided by an embodiment of the present utility model;

[0032] Figure 10 This is a structural diagram of a reference clock circuit provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0033] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," and so on, in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0035] An embodiment of the utility model provides an optical fiber transceiver. Figure 1 This is a schematic diagram of the structure of a fiber optic transceiver provided by an embodiment of the present utility model. Figure 1 The optical fiber transceiver includes: an FPGA (Field Programmable Gate Array) 10, an optical module 30, a PHY (Port Physical Layer) chip 20 and at least one network port connector 40.

[0036] Among them, the FPGA 10 includes an IO interface unit 110 and a SERDES (Serializer / Deserializer) interface unit 120. The transceiver interface of the optical module 30 is connected to the SERDES interface unit 120, and the configuration interface of the optical module 30 is connected to the IO interface unit 110. The transceiver interface of the PHY chip 20 is connected to the SERDES interface unit 120, and the configuration interface of the PHY chip 20 is connected to the IO interface unit 110. Each network port connector 40 is connected to the PHY chip 20. Among them, the optical module 30 can be connected to an optical fiber for photoelectric conversion; the network port connector 40 can be connected to an electronic device that needs to be connected to the Internet; the FPGA 10 configures the working status of the optical module 30 and the PHY chip 20 through the IO interface unit 110 with a common IO interface, and transmits data through the SERDES interface unit 120 that supports the SERDES protocol.

[0037] The working principle of the fiber optic transceiver can be found in Figure 2 , the black arrows and the blue arrows respectively indicate the two signal flows. Specifically, referring to the black arrow, the analog signal is transmitted from the network port connector 40 to the PHY chip 20 and converted into an electrical signal, and then transmitted to the FPGA 10 through the SERDES protocol, and then transmitted to the optical module 30 through the SERDES protocol and converted into an optical signal. Referring to the blue arrow, the optical signal is converted into an electrical signal by the optical module 30 and then transmitted to the FPGA 10 through the SERDES protocol, and then transferred out through the SERDES protocol and transmitted to the PHY chip 20 and the network port connector 40 in sequence, and output as an analog signal. Among them, the analog signal can be a gigabit analog signal. It can be understood that the optical transceiver can be powered by any existing power supply solution, and the power supply-related structure is not limited here.

[0038] The optical fiber transceiver provided by the embodiment of the present invention is provided with an FPGA 10, an optical module 30, a PHY chip 20, and at least one network port connector 40. The FPGA 10 is provided with a SERDES interface unit 120. The transceiver interface of the optical module 30 and the transceiver interface of the PHY chip 20 are both connected to the SERDES interface unit 120. Data transmission can be implemented based on the SERDES protocol, fully utilizing the communication channel capacity and improving the transmission speed. Therefore, the embodiment of the present invention can increase the data transmission rate of the optical fiber transceiver and improve communication efficiency.

[0039] Based on the above embodiments, the FPGA 10 model can optionally be PH1A90SBG484. The PHY chip 20 model can optionally be YT8618C. Using domestic chips to build a fiber optic transceiver can effectively reduce costs and improve the security of the fiber optic transceiver.

[0040] Based on the above embodiments, the optical module 30 can optionally be an SFP (Small Form-factor Pluggable) optical module or an SFP+ (10Gigabit Small Form-factor Pluggable) optical module, and the specific model is not limited here. Among them, the optical module 30 is preferably an SFP+ optical module to improve the data transmission rate.

[0041] Based on the above embodiments, the network port connector 40 may optionally include a network transformer and a network interface, wherein the network transformer is connected between the PHY chip 20 and the network interface. The network transformer and the network interface may be provided separately or integrated. The network interface may be an RJ45 interface, and the specific model is not limited here.

[0042] The following combination Figure 3-10 , which provides an example of the specific connection relationship between the modules, but does not serve as a limitation to the present invention.

[0043] See also Figure 3 The transceiver interface of the optical module 30 includes a first receive pin SPF1_RX_P and a second receive pin SPF1_RX_N, forming a differential receive pin pair; and a first transmit pin SPF1_TX_P and a second transmit pin SPF1_TX_N, forming a differential transmit pin pair. The first receive pin SPF1_RX_P, the second receive pin SPF1_RX_N, and the first transmit pin SPF1_TX_P and the second transmit pin SPF1_TX_N are connected to different pins in the SERDES interface unit 120.

[0044] The configuration interface of the optical module 30 may include: a transmission shutdown pin SPF1_TX_DIS, a first transmission rate pin SPF1_TX_RS0, a second transmission rate pin SPF1_TX_RS1, a reception signal loss pin SPF1_RX_LOS, a transmission fault pin SPF1_TX_FLT, and a module configuration pin SPF1_MOD_ABS. Among them, the transmission shutdown pin SPF1_TX_DIS, the first transmission rate pin SPF1_TX_RS0, the second transmission rate pin SPF1_TX_RS1, the reception signal loss pin SPF1_RX_LOS, the transmission fault pin SPF1_TX_FLT, and the module configuration pin SPF1_MOD_ABS are respectively connected to different pins in the IO interface unit. It is understandable that other functional interfaces in the optical module 30 and the PHY chip 20 except the configuration interface can also be connected through the IO interface unit 110 when they need to be connected to the FPGA 10. For example, see Figure 3The optical module 30 may further include a clock pin SPF1_SCL and a data pin SPF1_SDA, which are respectively connected to different pins in the IO interface unit 110 to implement communication based on the I2C protocol.

[0045] In summary, the transceiver interface in the optical module 30 is connected to the SERDES interface unit 120 in the FPGA 10 that supports the SERDES protocol, and the remaining pins are connected to the IO interface unit. It is understandable that the pins connected to the IO interface unit in the optical module 30 can be configured to be pulled up or down according to the needs. The specific configuration method in the FPGA 10 and the optical module 30 can be found in Figure 3 and Figure 4 ,For example Figure 4 Each pin shown can be pulled up to the power supply signal VDD_3V3_SFP through a resistor within the optical module 30. For example, the optical module 30 can be composed of components such as a CDR (Clock and Data Recovery) unit 31, a laser driver 32, and an amplifier 33, the specific structure of which is not limited here.

[0046] On the basis of the above embodiments, optionally, the PHY chip 20 includes multiple transceiver interfaces, including: at least one QSGMII (Quad Small Form-factor Pluggable Gigabit Media Independent Interface) interface, and the multiple transceiver interfaces may also include: at least one COPPER interface (an electrical interface connected by a twisted pair) or at least one COMBO interface (an optoelectronic multiplexing interface). In addition, the PHY chip 20 also includes: a transmission mode configuration interface. The transmission mode configuration interface includes at least one mode configuration pin, and the PHY chip 20 is used to determine the type and number of transceiver interfaces for data interaction with the FPGA 10 according to the potential of each mode configuration pin. Among them, Figure 5 It is exemplified in that the transmission mode configuration interface may include three mode configuration pins, namely APHY_MODE0, APHY_MODE1 and APHY_MODE2.

[0047] In actual applications, various transceiver interfaces set on the PHY chip 20, such as various QSGMII interfaces, various COPPER interfaces and various COMBO interfaces, can be connected to the FPGA 10, specifically to the SERDES interface unit 120 or other required interface units, and then the pull-up and pull-down structures of each mode configuration pin are set according to the designed number of network port connectors and transmission bandwidth, as well as transmission rate requirements to select the appropriate transmission mode and determine the type and number of transceiver interfaces that ultimately interact with the FPGA 10 for data. Figure 6The connection relationship between two sets of differential QSGMII interfaces and FPGA is given as an example. Figure 6 In the figure, the black network labels represent the relevant pins on the PHY chip 20, and the red network labels represent the relevant pins on the FPGA 10 (the corresponding relationship between the red network labels and the FPGA can be seen in Figure 8 and Figure 9 ); Pins AS0TXP, AS0TXN, AS0RXP, and AS0RXN constitute a set of differential QSGMII interfaces, and pins AS1TXP, AS1TXN, AS1RXP, and AS1RXN constitute another set of differential QSGMII interfaces; each pin in the two sets of QSGMII interfaces is connected to a corresponding pin in the SERDES interface unit 120 of the FPGA 10 through a capacitor.

[0048] In one embodiment, Figure 5 The chip transmission mode configuration relationship corresponding to the three mode configuration pins under different pull-up and pull-down combinations can be found in Table 1. In Table 1, RESERVED indicates that the transceiver interface is a reserved interface. The specific transmission mode between the PHY chip 20 and the FPGA 10 can be configured by the user according to the needs. Figure 5 The case where APHY_MODE[2:0] is configured as "100" is given as an example.

[0049] Table 1

[0050] APHY_MODE[2:0] Transmission Mode 3'b000 RESERVED 3'b001 RESERVED 3'b010 QSGMII×1&SGMII×1+COPPER×5 3'b011 SGMII×2+COPPER×2 3'b100 QSGMII×2+COPPER×8 3'b101 QSGMII×2+COPPER×8 3'b110 SGMII×1+COMBO×1 3'b111 QSGMII×1+COPPER×3&COMBO×1

[0051] Continue to see Figure 6 Based on the above embodiments, optionally, the configuration interface of the PHY chip 20 includes: a clock management pin APHY_MDC, a data input / output management pin APHY_MDIO, an interrupt pin APHYINT, and a reset pin AnRESET. The clock management pin APHY_MDC, the data input / output management pin APHY_MDIO, the interrupt pin APHYINT, and the reset pin AnRESET are respectively connected to different pins in the IO interface unit 110, for example, connected to corresponding pins in the IO interface unit 110 through resistors. Figure 5 The interrupt pin APHYINT and the data input and output management pin APHY_MDIO can also be pulled high through a pull-up resistor; and the PHY chip 20 can also include an enable pin AEN_PHY, which is pulled high through a pull-up resistor.

[0052] The structure of the network port connector 40 can be found in Figure 7 , Figure 7The red box in the middle shows the pins connecting the network transformer to the PHY chip 20. Here, the PHY chip 20 is shown as providing eight network ports. The differential signal pins associated with each network port are connected to a network connector 40, such as an RJ45 connector connected to the network transformer or an integrated network transformer. Pins APiMDIAP, APiMDIAN, APiMDIBP, APiMDIBN, APiMDICP, APiMDICN, APiMDIDP, and APiMDIDN constitute the differential signal pins associated with one of the network ports, where i = 0, 1, 2, 3, 4, 5, 6, or 7.

[0053] In summary, for the design of the PHY chip 20: the appropriate transmission mode can be selected according to the number of designed network ports and transmission bandwidth. This embodiment takes 8 network ports and 10G bandwidth as an example, providing Figure 5-7 The configuration shown. The PHY chip 20 can be equipped with an external 25MHz crystal oscillator to provide a clock. When the FPGA 10 is connected to multiple PHY chips 20, the address bits of each PHY chip 20 can be properly configured. The address bits of each PHY chip 20 are different and unique to ensure correct data transmission. The transceiver interface in the PHY chip 20 needs to be connected to a SERDES interface unit 120 that supports the SERDES protocol. The signals / pins of the configuration part can be connected to the IO interface unit 110 with ordinary IO in the FPGA 10.

[0054] Figure 8 and Figure 9 The specific structures of the IO interface unit 110 and the SERDES interface unit 120 are respectively given. Figure 8 and Figure 9 , FPGA 10 mainly processes the information transmitted from the optical module 30 and the PHY chip 20. The basic configuration of FPGA 10 is not limited here, and it can be configured according to the specific usage. Among them, the configuration interface of the optical module 30 and the configuration interface of the PHY chip 20 are both connected to the IO interface unit 110 with ordinary IO pins. Figure 8 As shown, the red box represents the connection with the relevant pins in the optical module 30, and the green box represents the connection with the relevant pins in the PHY chip 20. The transceiver interface of the optical module 30 and the transceiver interface of the PHY chip 20 are both connected to the SERDES interface unit 120, that is, the signal pins using the SERDES protocol need to be connected to the SERDES interface unit 120 that supports the protocol. Figure 9As shown, the SERDES interface unit 120 includes a first interface group BANK82 and a second interface group BANK83; the first interface group BANK82 and the second interface group BANK83 are respectively used to connect the transceiver interface of the optical module 30 and the transceiver interface of the PHY chip 20. For example, the first interface group BANK82 is used to connect to the transceiver interface of the PHY chip 20, and the second interface group BANK83 is used to connect to the transceiver interface of the optical module 30.

[0055] Based on the above embodiments, each pair of SERDES (or each interface group) may optionally need to input a set of differential reference clocks, the specific selection of which depends on the relevant configuration. For example, the first interface group BANK82 is connected to the first reference clock, and the first interface group BANK82 includes a set of pins for receiving differential signals: REFCLKP_82 and REFCLKN_82; the second interface group BANK83 is connected to the second reference clock, and the first interface group BANK82 includes a set of pins for receiving differential signals: REFCLKP_83 and REFCLKN_83. The two sets of reference clocks can be provided by a reference clock circuit, specifically, see Figure 10 Reference clock circuit 50 includes a first clock circuit 51 and a second clock circuit 52. First clock circuit 51 includes a first differential crystal oscillator XT5 and its peripheral circuits for providing a first reference clock. Second clock circuit 52 includes a second differential crystal oscillator XT6 and its peripheral circuits for providing a second reference clock. Exemplarily, both first and second differential crystal oscillators XT5 and XT6 are 125 MHz differential crystal oscillators.

[0056] In summary, the embodiment of the present invention provides a hardware application circuit for a fiber optic transceiver with a simple structure and low cost. It adopts PH1A90SBG484 in combination with YT8618C and uses the SERDES protocol for data transmission, so that the fiber optic transceiver can be used in scenarios with high transmission rate requirements, such as in the LED industry.

[0057] An embodiment of the present invention further provides a communication system, including the optical fiber transceiver provided by any embodiment of the present invention, which has corresponding beneficial effects.

[0058] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A fiber optic transceiver, characterized in that: include: FPGA, including IO interface unit and SERDES interface unit; An optical module, wherein the transceiver interface of the optical module is connected to the SERDES interface unit, and the configuration interface of the optical module is connected to the IO interface unit; A PHY chip, wherein the transceiver interface of the PHY chip is connected to the SERDES interface unit, and the configuration interface of the PHY chip is connected to the IO interface unit; At least one network port connector, each of the network port connectors is connected to the PHY chip.

2. The optical fiber transceiver according to claim 1, wherein: The model of the FPGA is: PH1A90SBG484.

3. The optical fiber transceiver according to claim 1 or 2, characterized in that: The model of the PHY chip is: YT8618C.

4. The optical fiber transceiver according to claim 1, wherein: The PHY chip includes a plurality of transceiver interfaces; The plurality of transceiver interfaces include: at least one QSGMII interface; the plurality of transceiver interfaces also include: at least one COPPER interface or at least one COMBO interface; The PHY chip also includes: a transmission mode configuration interface; the transmission mode configuration interface includes at least one mode configuration pin, and the PHY chip is used to determine the type and number of the transceiver interfaces for data interaction with the FPGA based on the potential of each mode configuration pin.

5. The optical fiber transceiver according to claim 1, wherein: The configuration interface of the PHY chip includes: a clock management pin, a data input and output management pin, an interrupt pin and a reset pin; the clock management pin, the data input and output management pin, the interrupt pin and the reset pin are respectively connected to different pins in the IO interface unit.

6. The optical fiber transceiver according to claim 1, wherein: The SERDES interface unit includes a first interface group and a second interface group; the first interface group is connected to a first reference clock, and the second interface group is connected to a second reference clock; the first interface group and the second interface group are respectively used to connect the transceiver interface of the optical module and the transceiver interface of the PHY chip.

7. The optical fiber transceiver according to claim 1, wherein: The transceiver interface of the optical module includes: a first receiving pin, a second receiving pin, a first transmitting pin and a second transmitting pin; the first receiving pin, the second receiving pin, the first transmitting pin and the second transmitting pin are respectively connected to different pins in the SERDES interface unit; The configuration interface of the optical module includes: a transmission shutdown pin, a first transmission rate pin, a second transmission rate pin, a reception signal loss pin, a transmission fault pin and a module configuration pin; the transmission shutdown pin, the first transmission rate pin, the second transmission rate pin, the reception signal loss pin, the transmission fault pin and the module configuration pin are respectively connected to different pins in the IO interface unit.

8. The optical fiber transceiver according to claim 1, wherein: The optical module is an SFP+ optical module.

9. The optical fiber transceiver according to claim 1, wherein: The network port connector includes: a network transformer and a network interface, wherein the network transformer is connected between the PHY chip and the network interface; wherein the network transformer and the network interface are separately or integratedly provided; and the network interface is an RJ45 interface.

10. A communication system, characterized in that: include: The optical fiber transceiver according to any one of claims 1 to 9.

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