Power MOS tube assembly
By optimizing the structural design of the power MOS tube, the response speed of high-frequency switches is improved and the loss is reduced, and the problems of slow response speed and high loss in the prior art are solved, which extends the application range and improves reliability.
Patent Information
- Application Number
- CN202421687907.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2034-07-16
AI Technical Summary
The existing power MOS tubes have slow response speed and high switching losses in high frequency switching applications, making it difficult to meet the development needs of thin, light and small products.
Using an N-type silicon substrate and an N-type epitaxial layer structure, multiple single cell units are arranged, including P-type well regions and trenches. Using heavily doped N-type source regions and medium-doped N-type contacts, combined with P-type ion columns and insulating layer design, the proportion and depth of P-type well regions and trenches are optimized, and the response speed of high-frequency switching is improved and losses are reduced.
It improves the response speed of high-frequency switches, reduces losses in high-frequency states, expands the application range of MOS transistor components, and improves the reliability of device components.
Smart Images
Figure CN223310188U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of MOS tubes, in particular to a power MOS tube component. Background Art
[0002] Power MOS transistor components offer advantages such as high integration, low on-resistance, fast switching speed, and low switching losses. They have completely replaced planar power trench MOS devices in low- and medium-voltage applications and are widely used in various power management and switching circuits. The current trend in power trench MOS devices is to achieve high-performance and high-reliability products using fewer photolithography steps and simpler process flows.
[0003] Especially as product applications develop towards thinness, lightness and smallness, to achieve the above goals, it is necessary to increase the switching frequency of the entire system. This leads to increasingly obvious switching losses in trench power MOS devices. How to improve the response speed of the switch and reduce the switching loss is of great significance. Summary of the Invention
[0004] The purpose of the utility model is to provide a power MOS tube component, which improves the response speed of high-frequency switches and reduces the loss of devices used in high-frequency states, thereby expanding the application range of MOS transistor components.
[0005] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: a power MOS transistor assembly, comprising: an N-type silicon substrate and an N-type epitaxial layer located on the upper surface of the N-type silicon substrate; a heavily doped N-type drain region is provided on the lower surface of the N-type silicon substrate; a first metal layer is provided on the surface of the heavily doped N-type drain region opposite to the N-type silicon substrate;
[0006] At least two unit cells are spaced apart in the N-type epitaxial layer. The unit cells further include a P-type well region and a trench. The P-type well region is located in an upper portion of the N-type epitaxial layer. A trench in the P-type well region extends from the P-type well region into the N-type epitaxial layer. A heavily doped N-type source region is located in an upper portion of the P-type well region and around the trench. A gate portion is located in the trench, and an insulating layer is provided between the gate portion and an inner wall of the trench.
[0007] The heavily doped N-type source region is covered with a medium-doped N-type contact portion at the periphery and below the end of the trench, wherein the upper end of the medium-doped N-type contact portion is flush with the upper end of the P-type well region and contacts a second metal layer, and the area below the medium-doped N-type contact portion is the P-type well region;
[0008] The P-type well region between adjacent unit cells has a P-type ion column, the upper end of which is in contact with the second insulating dielectric layer, and the lower end extends to the N-type epitaxial layer. A first insulating dielectric layer is located above the trench and covers the gate portion, and the second metal layer is located on the insulating dielectric layer and the heavily doped N-type source region.
[0009] The further improved scheme in the above technical scheme is as follows:
[0010] 1. In the above solution, the depth ratio of the P-type well region to the mid-doped N-type contact portion is 10:6-8.
[0011] 2. In the above solution, the depth of the P-type ion column is lower than the depth of the groove.
[0012] 3. In the above solution, the insulating layer is a silicon dioxide layer.
[0013] 4. In the above solution, the height ratio of the P-type well region to the trench is 1:3-4.
[0014] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0015] 1. In the power MOS transistor assembly of the present invention, a heavily doped N-type source region is covered with a medium-doped N-type contact portion away from the periphery and below one end of the trench. The upper end of the medium-doped N-type contact portion is flush with the upper end of the P-type well region and contacts a second metal layer. The area below the medium-doped N-type contact portion is the P-type well region, which improves the response speed of high-frequency switching and reduces the loss of the device in high-frequency state, thereby expanding the application range of the MOS transistor assembly.
[0016] 2. In the power MOS tube assembly of the present invention, at least two unit cells are arranged at intervals in its N-type epitaxial layer. The unit cells further include a P-type well region and a trench. The P-type well region is located on the upper part of the N-type epitaxial layer. The P-type well region between adjacent unit cells has a P-type ion column. The upper end of the P-type ion column contacts the second insulating dielectric layer, and the lower end extends to the N-type epitaxial layer. When in reverse bias, the leakage current of the device assembly is reduced, thereby further improving the reliability of the device assembly. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Attachment Figure 1 This is a schematic structural diagram of the power MOS tube assembly of the utility model.
[0018] In the above figures: 1. N-type silicon substrate; 2. N-type epitaxial layer; 3. First metal layer; 4. P-type well region; 5. Trench; 6. Gate portion; 7. Insulating layer; 8. Heavy-doped N-type source region; 91. First insulating dielectric layer; 92. Second insulating dielectric layer; 10. Second metal layer; 11. Heavy-doped N-type drain region; 12. Medium-doped N-type contact portion; 13. Unit cell; 14. P-type ion column. DETAILED DESCRIPTION
[0019] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.
[0020] Embodiment 1: A power MOS transistor assembly, comprising: an N-type silicon substrate 1 and an N-type epitaxial layer 2 located on the upper surface of the N-type silicon substrate 1; a heavily doped N-type drain region 11 located on the lower surface of the N-type silicon substrate 1; and a first metal layer 3 located on the surface of the heavily doped N-type drain region 11 opposite to the N-type silicon substrate 1.
[0021] At least two unit cells 13 are spaced apart in the N-type epitaxial layer 2. Each unit cell 13 further includes a P-type well region 4 and a trench 5. The P-type well region 4 is located in an upper portion of the N-type epitaxial layer 2. The trench 5 in the P-type well region 4 extends from the P-type well region 4 into the N-type epitaxial layer 2. A heavily doped N-type source region 8 is located in an upper portion of the P-type well region 4 and around the trench 5. A gate portion 6 is located in the trench 5. An insulating layer 7 is provided between the gate portion 6 and an inner wall of the trench 5.
[0022] The heavily doped N-type source region 8 is surrounded by and covered with a medium-doped N-type contact portion 12 at the periphery and below the end away from the trench 5. The upper end of the medium-doped N-type contact portion 12 is flush with the upper end of the P-type well region 4 and contacts a second metal layer 10. The area below the medium-doped N-type contact portion 12 is the P-type well region 4.
[0023] The P-type well region 4 between adjacent unit cells 13 has a P-type ion column 14, the upper end of which is in contact with the second insulating dielectric layer 92, and the lower end extends to the N-type epitaxial layer 2. A first insulating dielectric layer 91 is located above the trench 5 and covers the gate portion 6. The second metal layer 10 is located on the insulating dielectric layer 9 and the heavily doped N-type source region 8.
[0024] The depth ratio of the P-type well region 4 to the medium-doped N-type contact portion 12 is 10:7.
[0025] The depth of the P-type ion column 14 is lower than the depth of the trench 5 , and the insulating layer 7 is a silicon dioxide layer.
[0026] The height ratio of the P-type well region 4 to the trench 5 is 1:3.8.
[0027] The first metal layer 3 and the second metal layer 10 are aluminum metal layers or copper metal layers.
[0028] Example 2: A power MOS transistor assembly, comprising: an N-type silicon substrate 1 and an N-type epitaxial layer 2 located on the upper surface of the N-type silicon substrate 1; a heavily doped N-type drain region 11 is located on the lower surface of the N-type silicon substrate 1; and a first metal layer 3 is located on the surface of the heavily doped N-type drain region 11 opposite to the N-type silicon substrate 1.
[0029] At least two unit cells 13 are spaced apart in the N-type epitaxial layer 2. Each unit cell 13 further includes a P-type well region 4 and a trench 5. The P-type well region 4 is located in an upper portion of the N-type epitaxial layer 2. The trench 5 in the P-type well region 4 extends from the P-type well region 4 into the N-type epitaxial layer 2. A heavily doped N-type source region 8 is located in an upper portion of the P-type well region 4 and around the trench 5. A gate portion 6 is located in the trench 5. An insulating layer 7 is provided between the gate portion 6 and an inner wall of the trench 5.
[0030] The heavily doped N-type source region 8 is surrounded by and covered with a medium-doped N-type contact portion 12 at the periphery and below the end away from the trench 5. The upper end of the medium-doped N-type contact portion 12 is flush with the upper end of the P-type well region 4 and contacts a second metal layer 10. The area below the medium-doped N-type contact portion 12 is the P-type well region 4.
[0031] The P-type well region 4 between adjacent unit cells 13 has a P-type ion column 14, the upper end of which is in contact with the second insulating dielectric layer 92, and the lower end extends to the N-type epitaxial layer 2. A first insulating dielectric layer 91 is located above the trench 5 and covers the gate portion 6. The second metal layer 10 is located on the insulating dielectric layer 9 and the heavily doped N-type source region 8.
[0032] The depth ratio of the P-type well region 4 to the medium-doped N-type contact portion 12 is 10:7.5.
[0033] The depth of the P-type ion column 14 is lower than the depth of the trench 5 , and the insulating layer 7 is a silicon dioxide layer.
[0034] The height ratio of the P-type well region 4 to the trench 5 is 1:3.2.
[0035] The first metal layer 3 and the second metal layer 10 are aluminum metal layers or copper metal layers.
[0036] When the above-mentioned trench-type high-power MOSFET device is used, the response speed of the high-frequency switch is improved, and the loss of the device in the high-frequency state is reduced, thereby expanding the application range of the MOS transistor component; in addition, at least two single-cell units 13 are arranged at intervals in the N-type epitaxial layer 2, and this single-cell unit 13 further includes a P-type well region 4 and a trench 5. The P-type well region 4 is located at the upper part of the N-type epitaxial layer 2. The P-type well region 4 between adjacent single-cell units 13 has a P-type ion column 14. The upper end of this P-type ion column 14 contacts the second insulating dielectric layer 92, and the lower end extends to the N-type epitaxial layer 2. When it is in reverse bias, the leakage current of the device component is reduced, thereby further improving the reliability of the device component.
[0037] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.
Claims
1. A power MOS tube assembly, characterized in that: include: An N-type silicon substrate (1) and an N-type epitaxial layer (2) located on the upper surface of the N-type silicon substrate (1), wherein the lower surface of the N-type silicon substrate (1) has a heavily doped N-type drain region (11), and the surface of the heavily doped N-type drain region (11) opposite to the N-type silicon substrate (1) has a first metal layer (3); At least two single-cell units (13) are arranged at intervals in the N-type epitaxial layer (2), and the single-cell unit (13) further includes a P-type well region (4) and a trench (5), wherein the P-type well region (4) is located at the upper part of the N-type epitaxial layer (2), and the trench (5) located in the P-type well region (4) extends from the P-type well region (4) to the N-type epitaxial layer (2), and a heavily doped N-type source region (8) is provided in the upper part of the P-type well region (4) and around the trench (5), and a gate portion (6) is provided in the trench (5), and an insulating layer (7) is provided between the gate portion (6) and the inner wall of the trench (5); The heavily doped N-type source region (8) is covered with a medium-doped N-type contact portion (12) around and below one end away from the trench (5), wherein the upper end of the medium-doped N-type contact portion (12) is flush with the upper end of the P-type well region (4) and is in contact with a second metal layer (10), and the area below the medium-doped N-type contact portion (12) is the P-type well region (4); The P-type well region (4) between adjacent single-cell units (13) has a P-type ion column (14), the upper end of the P-type ion column (14) is in contact with the second insulating dielectric layer (92), and the lower end extends to the N-type epitaxial layer (2), a first insulating dielectric layer (91) is located above the groove (5) and covers the gate portion (6), and the second metal layer (10) is located on the insulating dielectric layer (9) and the heavily doped N-type source region (8).
2. The power MOS tube assembly according to claim 1, characterized in that: The depth ratio of the P-type well region (4) to the medium-doped N-type contact portion (12) is 10:6-8.
3. The power MOS tube assembly according to claim 1, characterized in that: The depth of the P-type ion column (14) is lower than the depth of the groove (5).
4. The power MOS tube assembly according to claim 1, characterized in that: The insulating layer (7) is a silicon dioxide layer.
5. The power MOS tube assembly according to claim 1, wherein: The height ratio of the P-type well region (4) to the trench (5) is 1:3-4.