SiC device capable of reducing follow current loss

Abstract

The utility model discloses a SiC device for reducing follow current loss, and relates to the technical field of semiconductors. A platform region is formed on a JFET (Junction Field Effect Transistor) region formed between a P-body region and a SiC Drift layer which are arranged at intervals through etching, a P + region is formed on the upper surface through ion implantation, and a JBS diode is integrated inside after Schottky contact is prepared, so that the follow current loss is reduced while the chip area is not increased too much. Moreover, the design also reduces the coupling area of the Poly layer and the gate oxide layer at the gate and the SiC Drift layer, thereby reducing the gate-drain parasitic capacitance Cgd of the device, improving the switching performance of the device, and reducing the switching loss.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC device capable of reducing freewheeling loss. Background Art

[0002] In the field of power electronics, diodes are primarily SBD diodes and PiN diodes. SBD diodes offer excellent forward performance and a low on-state voltage drop (VF), but poor reverse performance, a low breakdown voltage, and high leakage current. PiN diodes, on the other hand, offer the opposite: poor forward performance and a high VF, but excellent reverse performance, a high breakdown voltage, and low leakage current. JBS diodes, a product combining the structures of these two, combine the forward performance of SBDs and the reverse performance of PiN diodes. SiC JBS devices are the primary SiC diode type.

[0003] SiC MOSFET devices benefit from the advantages of the MOSFET unipolar structure and the high physical properties of SiC materials, so their static and dynamic performance are very excellent. In addition, the parasitic body diode integrated inside the SiC MOSFET also reduces the amount of additional diode devices in the external system, making it very competitive. Currently in the industry, the parasitic body diodes of SiCMOFETs are all PN junction diodes, which have the disadvantages of poor forward performance and large freewheeling losses. Therefore, in order to optimize this performance, researchers have integrated SBD diodes into the chip to improve its forward performance, but the disadvantage is that it will sacrifice additional chip area and increase costs. Therefore, how to reduce the freewheeling loss of the parasitic body diode inside the SiC MOSFET without increasing the chip area too much and improve the performance of the chip is a technical problem that needs to be solved urgently. Utility Model Content

[0004] In response to the above problems, the utility model provides a SiC device with reduced freewheeling loss, which reduces the parasitic body diode inside the SiC MOSFET without increasing the chip area too much, improves the switching performance of the device, and reduces the switching loss.

[0005] The technical solution of the utility model is:

[0006] A SiC device with reduced freewheeling loss includes a SiC sub-layer, a SiC drift layer with a platform area on top, a Schottky contact alloy layer, and a front electrode metal layer, arranged sequentially from bottom to top.

[0007] The SiC Drift layer is provided with:

[0008] There are several P-body regions, each extending downward from the top surface of the SiC Drift layer;

[0009] There are a plurality of NP regions, each extending downward from the top surface of the corresponding P-body region;

[0010] There are several PP regions, each extending downward from the top surface of the corresponding P-body region and connected to the side of the NP region;

[0011] There are several P+ regions, each extending downward from the top surface of the platform region at intervals;

[0012] A plurality of gate oxide layers are provided, which are respectively arranged on the top surfaces of the NP region, the P-body region and the SiC Drift layer;

[0013] There are several Poly layers, each of which is disposed on the top surface of the corresponding gate oxide layer;

[0014] an isolation dielectric layer, disposed on the top surface of the Poly layer, with its side extending downward and connected to the NP region and the SiCDrift layer respectively; a side of the isolation dielectric layer is connected to the P+ region;

[0015] an ohmic contact alloy layer, located on a side of the isolation dielectric layer, with a bottom surface connected to the NP region and the PP region respectively;

[0016] a Schottky contact alloy layer, disposed on the top surface of the platform region, with its side portion connected to the isolation dielectric layer, and its bottom surface respectively connected to the P+ region and the SiC Drift layer;

[0017] The front electrode metal layer is provided on the top of the device.

[0018] Specifically, the bottom of the front electrode metal layer is connected to the ohmic contact alloy layer, the isolation dielectric layer and the Schottky contact alloy layer respectively.

[0019] Specifically, the SiC Drift layer has a thickness of 5 μm to 20 μm.

[0020] Specifically, the bottom surface depth of the P-body region is 0.8um-1.2um.

[0021] Specifically, the bottom surface depth of the NP region is 0.3um-0.6um.

[0022] Specifically, the bottom surface depth of the PP region is 0.4um-1um.

[0023] In a SiC MOSFET device, this design etches a terrace region on the JFET region formed between the spaced-apart P-body regions and the SiC Drift layer, then ion-implants a P+ region on the upper surface. This Schottky contact allows for an internally integrated JBS diode, minimizing freewheeling losses without significantly increasing chip area. This design also reduces the coupling area between the gate poly layer and gate oxide layer and the SiC Drift layer, thereby reducing the device's gate-drain parasitic capacitance (Cgd), improving switching performance, and minimizing switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the structure of the SiC MOSFET of the utility model;

[0025] Figure 2 It is a structural diagram of step S100 of the present utility model;

[0026] Figure 3 It is a structural diagram of step S200 of the present utility model;

[0027] Figure 4 It is a structural diagram of step S300 of the present utility model;

[0028] Figure 5 It is a structural diagram of step S400 of the present utility model;

[0029] Figure 6 It is a structural diagram of step S500 of the present utility model;

[0030] Figure 7 It is a structural diagram of step S600 of the present utility model;

[0031] Figure 8 It is a structural diagram of step S800 of the present utility model;

[0032] Figure 9 It is a structural diagram of step S900 of the present utility model;

[0033] Figure 10 It is a structural diagram of step S1000 of the present utility model;

[0034] Figure 11 It is a structural diagram of step S1100 of the present utility model;

[0035] Figure 12 It is a structural diagram of step S1200 of the present utility model;

[0036] Figure 13 It is a structural diagram of step S1300 of the present utility model;

[0037] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the P-body region, 4 is the NP region, 5 is the PP region, 6 is the P+ region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the Ohmic contact alloy layer, 11 is the Schottky contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0039] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0040] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0041] A method for preparing a SiC device with reduced freewheeling loss comprises the following steps:

[0042] S100, homoepitaxially growing a SiC Drift layer 2 on the SiC Sub layer 1;

[0043] The thickness of the SiC Sub layer 1 in step S100 is 150um-450um, and the doping concentration is 1E19cm -2 The thickness of SiC Drift layer 2 is 5um-20um, and the doping concentration is 1E15-5E16cm -2 .

[0044] S200, forming a terrace area on the upper surface of the SiC Drift layer 2 by etching away a portion of the SiC Drift layer;

[0045] The etching depth in step S200 is 0.3um-0.8um.

[0046] S300, preliminarily forming a P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0047] The bottom depth of the P-body region 3 in step S300 is 0.8um-1.2um, and the doping concentration is 1E17-3E18cm -2 .

[0048] S400, preliminarily forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation;

[0049] The bottom depth of the NP region 4 in step S400 is 0.3um-0.6um, and the doping concentration is 1E18-1E19cm -2 .

[0050] S500, preliminarily forming a PP region 5 on the top surface of the P-body region 3 by Al ion implantation;

[0051] The bottom depth of the PP region 5 in step S500 is 0.4um-1um, and the doping concentration is 1E18-1E19cm -2 .

[0052] S600, forming a P+ region 6 on the top surface of the terrace region of the SiC Drift layer 2 by Al ion implantation;

[0053] The bottom depth of the P+ region 6 in step S600 is 0.4um-0.9um, and the doping concentration is 1E18-1E19cm -2 .

[0054] S700, the P-body region 3, the NP region 4, the PP region 5 and the P+ region 6 are activated and formed by high temperature ion activation;

[0055] The high temperature activation annealing temperature in step S700 is between 1600°C and 1900°C.

[0056] S800, forming a gate oxide layer 7 on the top surfaces of the SiC Drift layer 2, the P-body region 3 and the NP region 4 by dry oxygen oxidation;

[0057] The thickness of the gate oxide layer 7 in step S800 is 40 nm to 70 nm.

[0058] S900, forming a Poly layer 8 on the top surface of the gate oxide layer 7 by polysilicon deposition;

[0059] The thickness of the Poly layer 8 in step S900 is 0.5um-1.2um.

[0060] S1000, forming an isolation dielectric layer 9 on the top surface of the SiC Drift layer 2 and the NP region 4 by depositing an oxide layer, which is used as a dielectric to prevent the device gate electrode and source electrode from shorting;

[0061] S1100, forming an ohmic contact alloy layer 10 on the top surfaces of the NP region 4 and the PP region 5 by sputtering Ni metal and then thermal annealing;

[0062] The thickness of the Ni metal in step S1100 is 0.1 um-0.3 um.

[0063] S1200, forming a Schottky contact alloy layer 11 on the top surface of the terrace area of ​​the SiC Drift layer 2 by sputtering Ti metal and then thermal annealing;

[0064] The thickness of the Ti metal in step S1200 is 0.1um-0.3um.

[0065] S1300, forming a front electrode metal layer 12 above the device by sputtering Ti and AlCu metals;

[0066] In step S1300 , the thickness of the Ti metal is 0.1 um to 0.5 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0067] A SiC device for reducing freewheeling loss includes, arranged from bottom to top, a SiC sub-layer 1, a SiC drift layer 2 with a platform region on top, a Schottky contact alloy layer 11, and a front electrode metal layer 12;

[0068] The SiC Drift layer 2 is provided with:

[0069] There are several P-body regions 3, each extending downward from the top surface of the SiC Drift layer 2 and spaced apart from the bottom surface of the SiC Drift layer 2;

[0070] There are several NP regions 4, each extending downward from the top surface of the corresponding P-body region 3 and spaced apart from the bottom surface of the P-body region 3;

[0071] There are several PP regions 5, each extending downward from the top surface of the corresponding P-body region 3 and connected to the side of the NP region 4; a gap is set between the bottom surface of the PP region 5 and the bottom surface of the P-body region 3; the depth of the PP region 5 is not less than the depth of the NP region 4;

[0072] There are several P+ regions 6, each extending downward from the top surface of the platform region;

[0073] There are several gate oxide layers 7, which are respectively arranged on the top surfaces of the NP region 4, the P-body region 3 and the SiC Drift layer 2;

[0074] Poly layer 8, provided with a plurality of layers, respectively disposed on the top surface of the corresponding gate oxide layer 7;

[0075] An isolation dielectric layer 9 is provided on the top surface of the Poly layer 8, with its side extending downward and connected to the NP region 4 and the SiCDrift layer 2 respectively; the side of the isolation dielectric layer 9 is connected to the P+ region 6;

[0076] The ohmic contact alloy layer 10 is located on the side of the isolation dielectric layer 9, and the bottom surface is connected to the NP region 4 and the PP region 5 respectively;

[0077] A Schottky contact alloy layer 11 is provided on the top surface of the platform region, with its side portion connected to the isolation dielectric layer 9 and its bottom surface connected to the P+ region 6 and the SiC Drift layer 2 respectively;

[0078] The front electrode metal layer 12 is disposed on the top of the device.

[0079] The bottom of the front electrode metal layer 12 is connected to the ohmic contact alloy layer 10 , the isolation dielectric layer 9 and the Schottky contact alloy layer 11 respectively.

[0080] The utility model Figure 1 As shown, in the SiC MOSFET device, a platform region is etched on the JFET region formed between the spaced P-body regions 3 and the SiCDrift layer 2, and a P+ region 6 is formed on the upper surface by ion implantation. After preparing the Schottky contact, an internal integrated JBS diode is realized, which reduces the freewheeling loss without increasing the chip area too much.

[0081] Since the JBS diode integrated inside the SiC MOSFET device is in the JFET region, the coupling area between the Poly layer and gate oxide layer at the gate and the SiC Drift layer is reduced, where the capacitance is inversely proportional to the area, thereby reducing the gate-drain parasitic capacitance Cgd of the device, resulting in increased switching performance and reduced switching losses.

Claims

1. A SiC device with reduced freewheeling loss, characterized in that: It comprises a SiC sub layer (1), a SiC drift layer (2) with a platform area on the top, a Schottky contact alloy layer (11), and a front electrode metal layer (12) arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with: A plurality of P-body regions (3) are provided, each extending downward from the top surface of the SiC Drift layer (2); There are a plurality of NP regions (4), each extending downward from the top surface of the corresponding P-body region (3); There are several PP regions (5), each extending downward from the top surface of the corresponding P-body region (3) and connected to the side of the NP region (4); There are several P+ regions (6) extending downward from the top surface of the platform region at intervals; A plurality of gate oxide layers (7) are provided, and are respectively arranged on the top surfaces of the NP region (4), the P-body region (3), and the SiC Drift layer (2); Poly layers (8), provided with a plurality of layers, each of which is disposed on the top surface of the corresponding gate oxide layer (7); An isolation dielectric layer (9) is provided on the top surface of the Poly layer (8), with its side extending downward and connected to the NP region (4) and the SiCDrift layer (2) respectively; the side of the isolation dielectric layer (9) is connected to the P+ region (6); An ohmic contact alloy layer (10), located on the side of the isolation dielectric layer (9), with its bottom surface connected to the NP region (4) and the PP region (5) respectively; A Schottky contact alloy layer (11) is provided on the top surface of the platform region, its side portion is connected to the isolation dielectric layer (9), and its bottom surface is respectively connected to the P+ region (6) and the SiC Drift layer (2); A front electrode metal layer (12) is provided on the top of the device.

2. The SiC device for reducing freewheeling loss according to claim 1, characterized in that: The bottom of the front electrode metal layer (12) is respectively connected to the ohmic contact alloy layer (10), the isolation dielectric layer (9) and the Schottky contact alloy layer (11).

3. The SiC device for reducing freewheeling loss according to claim 1, wherein: The SiC Drift layer (2) has a thickness of 5um-20um.

4. The SiC device for reducing freewheeling loss according to claim 1, wherein: The bottom surface depth of the P-body region (3) is 0.8um-1.2um.

5. The SiC device for reducing freewheeling loss according to claim 1, wherein: The bottom surface depth of the NP region (4) is 0.3um-0.6um.

6. The SiC device for reducing freewheeling loss according to claim 1, characterized in that: The bottom surface depth of the PP region (5) is 0.4um-1um.

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