Image sensor

Abstract

The utility model provides an image sensor comprising a first integrated circuit (IC) bare chip stacked with a second IC bare chip. The first IC die includes a plurality of light detectors disposed within the first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and includes a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate below the first capacitor electrode. The plurality of light detectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

Description

Technical Field

[0001] The utility model relates to an image sensor. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras, cell phones, and the like. Types of image sensors include complementary metal-oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Utility Model Content

[0003] The present application provides an image sensor comprising: a first integrated circuit (IC) die including a plurality of photodetectors disposed within a first substrate; a second IC die stacked vertically with the first IC die, wherein the second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate, wherein the semiconductor capacitor includes: a first capacitor electrode overlying the second substrate and including a protrusion disposed in the second substrate; a capacitor dielectric layer disposed between the first capacitor electrode and the second substrate; and a doped capacitor region disposed within the second substrate and underlying the first capacitor electrode, wherein the plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

[0004] The present application provides an image sensor comprising: a plurality of photodetectors and floating diffusion nodes disposed within a first substrate, wherein the floating diffusion nodes are disposed between the plurality of photodetectors; a plurality of pixel transistors disposed on a second substrate below the first substrate, wherein the plurality of pixel transistors includes a first pixel transistor having a first source / drain region directly electrically coupled to the floating diffusion node; and a semiconductor capacitor disposed on the second substrate, wherein the semiconductor capacitor includes a doped capacitor region disposed on the second substrate, a first capacitor electrode disposed above the doped capacitor region, and a capacitor dielectric layer directly between the doped capacitor region and the first capacitor electrode, wherein the first capacitor electrode includes a plurality of protrusions disposed in the second substrate, wherein the doped capacitor region continuously wraps laterally around the plurality of protrusions, and wherein the semiconductor capacitor is directly electrically coupled to the second source / drain region of the first pixel transistor.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A schematic diagram illustrating some embodiments of an image sensor including pixels disposed across a first integrated circuit (IC) die and a second IC die, and a semiconductor capacitor disposed within the second IC die.

[0008] Figure 2 Show Figure 1 A circuit diagram of some embodiments of an image sensor is shown, wherein the image sensor further includes a third IC die electrically coupled to the second IC die.

[0009] Figure 3 A cross-sectional view of some embodiments of an image sensor is shown having a first IC die, a second IC die, and a third IC die stacked vertically on top of each other, where the second IC die includes a semiconductor capacitor.

[0010] Figures 4 to 7 Show Figure 3 Cross-sectional views of some other embodiments of image sensors are shown.

[0011] Figure 8A and Figure 8B Show Figure 3 Cross-sectional and top views of some embodiments of semiconductor capacitors are shown.

[0012] Figure 9A and Figure 9B Show Figure 4 Cross-sectional and top views of some embodiments of semiconductor capacitors are shown.

[0013] Figure 10A and Figure 10B Show Figure 5 Cross-sectional and top views of some embodiments of semiconductor capacitors are shown.

[0014] Figures 11 to 37 Various cross-sectional views are shown of some embodiments of a method of forming an image sensor including a pixel having a semiconductor capacitor disposed on a substrate.

[0015] Figures 38 to 43 Various cross-sectional views are shown of some other embodiments of methods of forming an image sensor including a pixel having a semiconductor capacitor disposed on a substrate.

[0016] Figures 44 to 47 Various cross-sectional views of some embodiments of a method of forming a doped capacitor region of a semiconductor capacitor of a pixel by epitaxy are shown.

[0017] Figure 48 A flow chart is shown according to some embodiments of a method for forming an image sensor including a pixel having a semiconductor capacitor disposed on a substrate.

[0018] Description of Reference Numerals

[0019] 100: Schematic diagram

[0020] 102: First IC bare die

[0021] 103, 103b: Pixel

[0022] 103a: First pixel / pixel

[0023] 104: Second IC die

[0024] 106: Light Detector

[0025] 108: Transfer transistor

[0026] 110: Second substrate

[0027] 110b, 304b: rear surface

[0028] 110f, 304f, 340f: front surface

[0029] 111: Floating diffusion node

[0030] 112: Semiconductor capacitors

[0031] 114: First capacitor electrode

[0032] 114b: Body structure

[0033] 114p: protrusion

[0034] 116: Doped capacitor region

[0035] 118: Capacitor dielectric layer

[0036] 120: Capacitor contact area

[0037] 122: Pixel transistor / first transistor

[0038] 124: Pixel transistor / reset transistor

[0039] 126: Pixel transistor / source follower transistor

[0040] 128: Pixel transistor / select transistor

[0041] 130: Source / drain region

[0042] 130a: shared source / drain region

[0043] 132: Gate electrode

[0044] 134: Gate dielectric layer

[0045] 136, 342: Isolation structure

[0046] 200: Circuit Diagram

[0047] 202: Third IC die

[0048] 204: Application-Specific Integrated Circuit (ASIC)

[0049] 300, 400, 500, 600, 700, 800a, 900a, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700: Cross-sectional view 304: First substrate

[0050] 306: First interconnect structure

[0051] 308: Second interconnect structure

[0052] 310: Third interconnect structure

[0053] 312: Trench Isolation Structure

[0054] 314: cushioning layer

[0055] 316: Trench filling layer

[0056] 318: Filter

[0057] 320: Microlens

[0058] 321: Through-substrate via (TSV)

[0059] 322: Dielectric Structure

[0060] 324: Conductive contact

[0061] 326: Conductive wiring

[0062] 326a: first conductive wiring

[0063] 328: Via

[0064] 330: Conjugate pad

[0065] 332: Sidewall spacer structure

[0066] 334: Well region

[0067] 336: Semiconductor device / n-channel metal oxide semiconductor (NMOS) transistor

[0068] 338: Semiconductor Devices / P-Channel Metal Oxide Semiconductor Transistors

[0069] 340: Third substrate

[0070] 800b, 900b, 1000a, 1000b: Top view

[0071] 802, 902: Angle

[0072] 806, 906, 1002: height

[0073] 808, 814, 908, 914, 1008: Width

[0074] 810, 816, 910, 916, 1010: length

[0075] 812, 912, 1006: distance

[0076] 1004: diameter

[0077] 1502, 3802: dielectric layer

[0078] 1504, 2904: Hard mask layer

[0079] 1506, 1804, 2502, 2906: mask layer

[0080] 1508, 3002, 3808: Open

[0081] 1602, 3902: ditch

[0082] 1802: Dielectric liner

[0083] 2402: Gate electrode material

[0084] 2602: Gate structure

[0085] 2902: Interlayer dielectric (ILD) layer

[0086] 3402: Bonding dielectric layer

[0087] 3804: First hard mask layer

[0088] 3806: First mask layer

[0089] 4002: Second hard mask layer

[0090] 4102: Third hard mask layer

[0091] 4602: Doped epitaxial layer

[0092] 4800: Method

[0093] 4802, 4804, 4806, 4808, 4810, 4812, 4814, 4816, 4818, 4820, 4822, 4824: Action

[0094] OUT: output terminal

[0095] RST: Reset signal

[0096] SEL: Select signal

[0097] ST: Gate signal

[0098] t1: thickness

[0099] TX1, TX2, TX3, TX4: transfer signal

[0100] V1: first voltage source

[0101] VDD: power supply voltage DETAILED DESCRIPTION

[0102] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0103] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0104] An image sensor may include a stacked first integrated circuit (IC) die and a second IC die. The first IC die includes a plurality of pixels, and the second IC die includes an application-specific IC (ASIC) electrically coupled to each pixel. The pixels each include a plurality of photodetectors disposed in a first substrate of the first IC die. The pixels further include a plurality of semiconductor devices configured to read out the photodetectors. The semiconductor devices include a plurality of transfer transistors, a plurality of pixel transistors, and capacitors. An interconnect structure of the first IC die includes a plurality of metal wires and a plurality of metal vias disposed on the first substrate and configured to electrically couple the semiconductor devices to each other. The capacitor may be configured as a metal-insulator-metal capacitor and disposed within the interconnect structure of the first IC die. The capacitor is configured to improve pixel performance. For example, the capacitor is configured to increase the full well capacitor (FWC) of the photodetector.

[0105] To further increase the FWC of the photodetector, the capacitance of the capacitor can be increased. This can be achieved by increasing the lateral area of ​​the first and second metal plates of the capacitor. However, increasing the lateral area of ​​the first and second metal plates reduces the area available for metal routing in the interconnect structure. In another example, the first and second metal plates can be positioned within trenches in the dielectric structure of the interconnect structure to increase the area between the first and second metal plates. This reduces the area available for metal routing, leading to complex metal routing designs and / or increased manufacturing costs. This reduction in the area available for metal routing in the interconnect structure reduces the ability to scale image sensor size and reduces device density.

[0106] Various embodiments of the present application relate to an image sensor including a pixel having a semiconductor capacitor with increased capacitance and simplified fabrication. The pixel spans a first IC die and a second IC die stacked with the first IC die. The pixel includes a plurality of photodetectors and a plurality of transfer transistors disposed within and / or on a first substrate of the first IC die. Furthermore, the pixel includes a plurality of pixel transistors (e.g., reset transistors, source-follower transistors, etc.) disposed on a second substrate of the second IC die. The first IC die and the second IC die each include an interconnect structure configured to electrically couple the first IC die to the second IC die and facilitate electrical routing. The semiconductor capacitor includes a doped capacitor region located in the second substrate, a capacitor dielectric layer along the second substrate, and a first capacitor electrode overlying the doped capacitor region. Placing the semiconductor capacitor within / along the second substrate increases the area available for metal routing in the interconnect structure of the first IC die and / or the second IC die, thereby reducing metal routing design complexity, lowering manufacturing costs, and facilitating device scalability. Furthermore, the first capacitor electrode includes one or more protrusions disposed within a trench in the second substrate. This advantageously increases the area between the first capacitor electrode and the doped capacitor region without increasing the lateral area of ​​the semiconductor capacitor. Consequently, the capacitance of the semiconductor capacitor can be increased without reducing the area of ​​the pixel transistor. Therefore, placing the semiconductor capacitor on the second substrate of the second IC die improves the overall performance of the image sensor.

[0107] Figure 1 Schematic diagram 100 shows some embodiments of an image sensor including pixel 103 having semiconductor capacitor 112 disposed within second IC die 104 .

[0108] Pixel 103 spans a first IC die 102 and a second IC die 104. First IC die 102 is shown in a circuit diagram, and second IC die 104 is shown in a cross-sectional view. Pixel 103 includes a photodetector 106 and a transfer transistor 108 located on first IC die 102. In some embodiments, photodetector 106 is disposed within a first substrate (not shown) of first IC die 102, and a floating diffusion node 111 is disposed within the first substrate. Pixel 103 further includes a plurality of pixel transistors 122-128 and a semiconductor capacitor 112 disposed on a second substrate 110 of second IC die 104. Transfer transistor 108, the plurality of pixel transistors 122-128, and semiconductor capacitor 112 are configured to collectively facilitate readout of photodetector 106. Because pixel 103 is partitioned across first IC die 102 and second IC die 104, the area of ​​first IC die 102 that would otherwise be used by pixel transistors 122-128 can now be used by photodetector 106. This facilitates increasing the size of photodetector 106 and / or increasing the number of photodetectors that can be arranged across first IC die 102, thereby improving pixel 103 performance (e.g., increasing FWC) and / or increasing device density.

[0109] Photodetector 106 is configured to absorb incident light (e.g., photons) and generate a corresponding electrical signal corresponding to the incident light. For example, photodetector 106 may generate electron-hole pairs from the incident light. Transfer transistor 108 is gated by transfer signal TX1 and configured to control the flow of current between floating diffusion node 111 and photodetector 106. For example, transfer transistor 108 may be configured to selectively form a conductive channel in the first substrate between floating diffusion node 111 and photodetector 106 to transfer charge accumulated in photodetector 106 to floating diffusion node 111. Pixel transistors 122 through 128 are configured to read the transferred accumulated charge from floating diffusion node 111.

[0110] The plurality of pixel transistors 122 to 128 include a first transistor 122, a reset transistor 124, a source-follower transistor 126, and a select transistor 128. The plurality of pixel transistors 122 to 128 respectively include a gate electrode 132 stacked with a gate dielectric layer 134 on a second substrate 110, and a source / drain region 130 disposed within the second substrate 110. The source / drain region may be individually or collectively referred to as a source or a drain, depending on the context.

[0111] Reset transistor 124 is electrically coupled between floating diffusion node 111 and a terminal to which power supply voltage VDD is applied. First transistor 122 is electrically coupled between the floating diffusion node and reset transistor 124. Reset transistor 124 is gated by a reset signal RST and is configured to selectively electrically couple floating diffusion node 111 to power supply voltage VDD. Therefore, reset transistor 124 is configured to reset floating diffusion node 111 to power supply voltage VDD by cooperating with first transistor 122. Furthermore, reset transistor 124 can be configured to selectively couple photodetector 106 to power supply voltage VDD by cooperating with first transistor 122 and transfer transistor 108, thereby clearing charge accumulated in photodetector 106.

[0112] Source-follower transistor 126 is electrically coupled between power supply voltage VDD and select transistor 128. Source-follower transistor 126 is gated by the charge at floating diffusion node 111. For example, gate electrode 132 of source-follower transistor 126 is directly electrically coupled to floating diffusion node 111. Select transistor 128 is electrically coupled between source-follower transistor 126 and output terminal OUT of second IC die 104. Thus, source-follower transistor 126 and select transistor 128 are electrically coupled in series from power supply voltage VDD to output terminal OUT. Source-follower transistor 126 is configured to buffer and / or amplify the voltage at floating diffusion node 111 for non-destructive reading of the voltage. Select transistor 128 is gated by select signal SEL and is configured to selectively pass the buffered and / or amplified voltage from source-follower transistor 126 to output terminal OUT. This buffered and / or amplified voltage is then passed to another IC die (eg, an ASIC circuit) for downstream signal processing.

[0113] Semiconductor capacitor 112 includes a first capacitor electrode 114, a capacitor dielectric layer 118, a doped capacitor region 116, and a capacitor contact region 120. First capacitor electrode 114 includes a plurality of protrusions disposed within a trench extending into second substrate 110. In various embodiments, doped capacitor region 116 is a doped region of second substrate 110. Second substrate 110 includes a first doping type (e.g., p-type), and doped capacitor region 116 includes a second doping type (e.g., n-type) opposite the first doping type. Capacitor dielectric layer 118 lines the trench of second substrate 110 and is disposed between first capacitor electrode 114 and doped capacitor region 116. Furthermore, capacitor contact region 120 is a doped region of second substrate 110 including the second doping type (e.g., n-type) and is electrically coupled to doped capacitor region 116. The semiconductor capacitor 112 is electrically coupled between the first voltage source V1 and the shared source / drain region 130 a of the first transistor 122 and the reset transistor 124 .

[0114] First transistor 122 is gated by gate signal ST and is configured to selectively electrically couple photodetector 106 to semiconductor capacitor 112 in cooperation with transfer transistor 108. During an exposure period of the image sensor, photodetector 106 absorbs incident light and accumulates charge in photodetector 106. However, in high-intensity light environments, photodetector 106 may become saturated before the end of the exposure period and may not accumulate sufficient charge to accurately reflect the high-intensity light to which photodetector 106 was exposed during the exposure period. This may partially cause blooming on the image sensor and / or reduce the accuracy of images generated from the image sensor. First transistor 122 and transfer transistor 108 are configured to transfer excess charge accumulated in photodetector 106 to semiconductor capacitor 112 during the exposure period. Therefore, when the image sensor is exposed to a high-intensity light environment, overflow charge (e.g., charge accumulated above the saturation level of photodetector 106) is transferred to semiconductor capacitor 112. The charge accumulated in semiconductor capacitor 112 can be read out by source follower transistor 126 and select transistor 128. Therefore, semiconductor capacitor 112 increases the FWC of pixel 103 and reduces negative effects caused by blooming (e.g., cross-talk between photodetectors on the image sensor).

[0115] The first IC die 102 and the second IC die 104 are connected to each other by corresponding interconnection line structures (eg, Figure 3) are electrically coupled to each other. Because semiconductor capacitor 112 is disposed on and / or within second substrate 110, semiconductor capacitor 112 is not disposed within the interconnect structure of first IC die 102 and second IC die 104. This increases the area available for metal wiring in the interconnect structure of first IC die 102 and / or second IC die 104, thereby reducing metal wiring design complexity, lowering manufacturing costs, and facilitating device scaling. Furthermore, first capacitor electrode 114, including protrusion 114p disposed within second substrate 110, increases the vertical area between first capacitor electrode 114 and doped capacitor region 116. This facilitates increasing the capacitance of semiconductor capacitor 112 while maintaining or reducing the lateral footprint of semiconductor capacitor 112. The increased capacitance of semiconductor capacitor 112 improves the performance (e.g., FWC) of pixel 103. Therefore, disposing semiconductor capacitor 112 on second substrate 110 of second IC die 104 improves the overall performance of the image sensor.

[0116] Figure 2 Show Figure 1 Circuit diagram 200 of some other embodiments of an image sensor is shown, wherein the image sensor further includes a third IC die 202 electrically coupled to second IC die 104. Third IC die 202 includes an ASIC 204 electrically coupled to output terminal OUT of second IC die 104. In some embodiments, first IC die 102 includes a plurality of photodetectors 106 and a plurality of transfer transistors 108 electrically coupled between corresponding photodetectors 106 and floating diffusion node 111. Transfer transistors 108 are gated by transfer signals TX1 through TX4. In various embodiments, semiconductor capacitor 112 is electrically coupled between supply voltage VDD and a shared source / drain region of first transistor 122 and reset transistor 124. In yet other embodiments, photodetectors 106 are electrically coupled between ground terminals and corresponding source / drain regions of the transfer transistors. Semiconductor capacitor 112 is configured to increase the FWC of photodetectors 106, thereby improving overall image sensor performance.

[0117] Figure 3 A cross-sectional view 300 of some embodiments of an image sensor is shown having first IC die 102, second IC die 104, and third IC die stacked vertically on top of each other, wherein second IC die 104 includes semiconductor capacitor 112. A plurality of pixels 103a, 103b spans first IC die 102 and second IC die 104.

[0118] First IC die 102 includes a first interconnect structure 306 disposed on a frontside surface 304f of a first substrate 304 and a plurality of photodetectors 106 disposed within first substrate 304. First substrate 304 may be or include, for example, silicon, single-crystal silicon, germanium, silicon-germanium, or another suitable semiconductor material. First substrate 304 has a first doping type (e.g., p-type). Photodetectors 106 are or include doped regions of first substrate 304 having a second doping type (e.g., n-type) opposite the first doping type. Photodetectors 106 may be configured as photodiodes or some other suitable photodetector. A plurality of floating diffusion nodes 111 are disposed in first substrate 304 and adjacent to corresponding photodetectors 106. The floating diffusion nodes include the second doping type (e.g., n-type). In various embodiments, pixels 103a and 103b each include photodetectors 106 arranged in a 2×2 layout, a 2×1 layout, or some other suitable layout.

[0119] A plurality of transfer transistors 108 are disposed on a front surface 304 f of a first substrate 304 and are each adjacent to a corresponding photodetector 106. Transfer transistors 108 include a transfer gate electrode and a transfer gate dielectric disposed between the transfer gate electrode and the first substrate 304. A trench isolation structure 312 extends into the back surface of the first substrate 304. Trench isolation structure 312 includes a trench fill layer 316 and a liner layer 314. Liner layer 314 is disposed between trench fill layers 316. Trench isolation structure 312 laterally wraps around photodetectors 106 and is configured to provide electrical and optical isolation between adjacent photodetectors 106 and between adjacent pixels in the plurality of pixels 103 a and 103 b. A plurality of light filters 318 are disposed on the back surface 304 b of the first substrate 304, overlying the photodetectors 106. A plurality of microlenses 320 are disposed on filter 318 and are configured to focus incident light toward light detector 106 .

[0120] The second IC die 104 is positioned below the first IC die 102. The second IC die 104 includes a second substrate 110, a second interconnect structure 308 located on a front surface 110f of the second substrate 110, a plurality of pixel transistors 122-128 located on the second substrate 110, and a semiconductor capacitor 112. The second substrate 110 may be or may include, for example, silicon, single crystal silicon, germanium, silicon germanium, or some other suitable semiconductor material. The second substrate 110 has a first doping type (e.g., p-type). The first interconnect structure 306 of the first IC die 102 and the second interconnect structure 308 of the second IC die 104 are bonded at a first bonding interface comprising a metal-to-metal bond and a dielectric-to-dielectric bond. The first interconnect structure 306 and the second interconnect structure 308 each include a plurality of conductive contacts 324, a plurality of conductive traces 326, a plurality of vias 328, and a plurality of bonding pads 330 disposed within a dielectric structure 322. The first interconnect structure 306 and the second interconnect structure 308 are configured to facilitate electrical coupling between the first IC die 102 and the second IC die 104 .

[0121] The plurality of pixel transistors 122 to 128 each include a gate electrode 132, a gate dielectric layer 134 disposed between the gate electrode 132 and the second substrate 110, a plurality of source / drain regions 130 disposed on opposite sides of the gate electrode 132, and sidewall spacer structures 332 disposed along the sidewalls of the gate electrode 132. The plurality of source / drain regions 130 are disposed within the second substrate 110 and include a second dopant type (e.g., n-type). An isolation structure 136 extends into the front surface 110 f of the second substrate 110 and is configured to facilitate electrical isolation between the plurality of pixel transistors 122 to 128 and the semiconductor capacitor 112. The plurality of pixel transistors 122 to 128 include a first transistor 122, a reset transistor 124, a source follower transistor 126, and a select transistor 128.

[0122] The semiconductor capacitor 112 includes a first capacitor electrode 114, a capacitor dielectric layer 118, a doped capacitor region 116, and a capacitor contact region 120. A plurality of trenches extend into the front side surface 110f of the second substrate 110 and are defined by opposing sidewalls and a lower surface of the second substrate 110. The first capacitor electrode 114 includes a body structure 114b overlying the second substrate 110 and a plurality of protrusions 114p extending from the body structure 114b into the trenches. The capacitor dielectric layer 118 is disposed between the first capacitor electrode 114 and the second substrate 110. The capacitor dielectric layer 118 directly contacts the opposing sidewalls and a lower surface of the second substrate 110 that define the trenches. In various embodiments, the outer sidewalls of the capacitor dielectric layer 118 are aligned with the outer sidewalls of the body structure 114b. The sidewall spacer structures 332 extend continuously along the outer sidewalls of the capacitor dielectric layer 118 and the outer sidewalls of the body structure 114b.

[0123] In various embodiments, the doped capacitor region 116 is a doped region of the second substrate 110 and includes the second doping type (e.g., n-type). The doped capacitor region 116 laterally and continuously wraps around the outer periphery of each of the protrusions 114p of the first capacitor electrode 114. The doped capacitor region 116 extends along the opposing sidewalls and lower surface of the second substrate 110 that define the trench. In further embodiments, the doped capacitor region 116 is a doped epitaxial layer that extends along the opposing sidewalls and lower surface of the second substrate 110 that define the trench. The capacitor contact region 120 is disposed within the second substrate 110 and is adjacent to the doped capacitor region 116. In various embodiments, the capacitor contact region 120 and the source / drain regions 130 have the same doping concentration. In further embodiments, the doping concentration of the doped capacitor region 116 is less than the doping concentration of the capacitor contact region 120.

[0124] Because first capacitor electrode 114 includes protrusion 114p disposed in second substrate 110, the area between first capacitor electrode 114 and doped capacitor region 116 is larger than the lateral area of ​​semiconductor capacitor 112. For example, providing protrusion 114p in the trench of second substrate 110 increases the vertical area between first capacitor electrode 114 and doped capacitor region 116. This advantageously increases the capacitance of semiconductor capacitor 112 without increasing the lateral area of ​​semiconductor capacitor 112. Consequently, the performance (e.g., FWC) of photodetector 106 is improved. Furthermore, disposing semiconductor capacitor 112 on second substrate 110 increases the area available for electrical routing in first and second interconnect structures 306 and 308, and reduces the design complexity of first and second interconnect structures 306 and 308. Therefore, an image sensor including semiconductor capacitor 112 improves the performance (e.g., FWC) of photodetector 106, increases device density, and reduces design complexity.

[0125] A well region 334 is disposed within the second substrate 110 and extends along the doped capacitor region 116. The well region 334 includes a first dopant type (e.g., p-type). In some embodiments, the well region 334 has a dopant concentration that is lower than the dopant concentration of the doped capacitor region 116. A plurality of bonding pads 330 are disposed on the backside surface 110b of the second substrate 110. Furthermore, through substrate vias (TSVs) 321 extend continuously through the second substrate 110 to electrically couple the third IC die 202 to the second interconnect structure 308.

[0126] In some embodiments, the top surface of the first capacitor electrode 114 is aligned with the top surface of the gate electrodes 132 of the plurality of pixel transistors 122 to 128. In yet other embodiments, the thickness of the gate dielectric layer 134 is equal to the thickness of the capacitor dielectric layer 118. In such embodiments, the top surface of the gate dielectric layer 134 is aligned with the top surface of the capacitor dielectric layer 118, and the gate dielectric layer 134 and the capacitor dielectric layer 118 comprise the same material. In yet other embodiments, the thickness of the gate dielectric layer 134 is greater than the thickness of the capacitor dielectric layer 118. In yet other embodiments, the gate electrode 132 and the first capacitor electrode 114 may be or may comprise polysilicon, doped polysilicon, a metal (e.g., aluminum, titanium, etc.), some other conductive material, or any combination thereof. In some embodiments, the gate electrode 132 and the first capacitor electrode 114 comprise the same conductive material (e.g., doped polysilicon). In still other embodiments, the gate dielectric layer 134 and the capacitor dielectric layer 118 may be or may include silicon dioxide, hafnium oxide, zirconium oxide, aluminum oxide, some other dielectric, or any combination thereof.

[0127] The third IC die 202 includes a third substrate 340, a third interconnect structure 310, and a plurality of semiconductor devices 336, 338. The plurality of semiconductor devices 336, 338 are disposed on a front side surface 340f of the third substrate 340. An isolation structure 342 is disposed between adjacent semiconductor devices 336, 338 in the third substrate 340. The third interconnect structure 310 is disposed on the front side surface 340f of the third substrate 340 and is electrically coupled to the plurality of semiconductor devices 336, 338. The third interconnect structure 310 of the third IC die 202 is bonded to the second IC die 104 at a second bonding interface, which may include a metal-to-metal bond, a dielectric-to-dielectric bond, or the like.

[0128] In various embodiments, the third IC die 202 is configured as an ASIC. In various embodiments, the plurality of semiconductor devices 336 and 338 include an n-channel metal-oxide-semiconductor (NMOS) transistor 336 and a p-channel metal-oxide-semiconductor transistor 338. In various embodiments, the plurality of semiconductor devices 336 and 338 and the plurality of pixel transistors 122 to 128 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), nanosheet field-effect transistors, similar transistors, or any combination thereof.

[0129] In various embodiments, the conductive contacts 324, the conductive traces 326, the vias 328, and the bonding pads 330 may be or include, for example, copper, aluminum, tungsten, titanium, titanium nitride, tantalum nitride, some other suitable conductive material, or any combination thereof. The dielectric structure 322 includes one or more dielectric layers, which may be or include, for example, silicon dioxide, a low-k dielectric material, silicon nitride, silicon carbide, or some other suitable dielectric material. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9.

[0130] Figure 4 Show Figure 3 A cross-sectional view 400 of another embodiment of an image sensor is shown, in which the plurality of protrusions 114 p of the first capacitor electrode 114 have a triangular shape.

[0131] Figure 5 Show Figure 3 A cross-sectional view 500 of further embodiments of an image sensor is shown, wherein the plurality of protrusions 114 p of the first capacitor electrode 114 have a cylindrical shape. In various embodiments, a bottom surface of the protrusion 114 p is curved.

[0132] Figure 6 Show Figure 3 A cross-sectional view 600 of some other embodiments of an image sensor is shown, wherein first capacitor electrode 114 is directly electrically coupled to source / drain region 130 of first transistor 122. In various embodiments, the reset transistor ( Figure 3 124) and the selection transistor ( Figure 3 128) is provided on the second substrate 110. Figure 6 In a location not visible in the cross-sectional view 600 , the capacitor contact region 120 is directly electrically coupled to the first interconnect structure 306 of the first IC die 102. The TSV 321 is directly electrically coupled to the first conductive wiring 326 a. The first conductive wiring 326 a is directly electrically coupled to the gate electrode 132 of the source-follower transistor 126 and the source / drain region 130 of the first transistor 122. Furthermore, the first conductive wiring 326 a is directly electrically coupled to the floating diffusion node 111 of the first pixel 103 a.

[0133] Figure 7 Show Figure 3 A cross-sectional view 700 of further embodiments of an image sensor is shown, wherein doped capacitor region 116 is or includes a doped epitaxial layer lining a trench in second substrate 110. In various embodiments, doped capacitor region 116 comprises epitaxial silicon having a second doping type (e.g., n-type). In some embodiments, the thickness of doped capacitor region 116 is greater than the thickness of capacitor dielectric layer 118. Capacitor contact regions 120 are disposed within second substrate 110 and along the sidewalls and lower surface of doped capacitor region 116.

[0134] Figure 8A and Figure 8B Show Figure 3 Some embodiments of the semiconductor capacitor 112 are shown in a cross-sectional view 800a and a top view 800b.

[0135] Reference Figure 8AAs shown in cross-sectional view 800a, the height 806 of the protrusion 114p of the first capacitor electrode 114 is in a range of approximately 0.35 micrometers (μm) to 2 micrometers, or some other suitable value. In some embodiments, the height 806 of the protrusion 114p is greater than the height of the body structure 114b, thereby increasing the capacitance of the semiconductor capacitor 112. In various embodiments, the angle 802 between the bottom surface of the protrusion 114p and the corresponding sidewall of the protrusion 114p is in a range of approximately 90 degrees to 135 degrees, or some other suitable value. In various embodiments, the thickness t1 of the capacitor dielectric layer 118 is in a range of approximately 19 angstroms to 75 angstroms, or some other suitable value. In various embodiments, the protrusion 114p has a polygonal shape when viewed in cross section.

[0136] Reference Figure 8B In the top view 800b shown, the plurality of protrusions 114p are shown in dashed lines and are positioned below the body structure 114b. The protrusions 114p are elongated in a first direction (e.g., along the y-axis) and spaced apart a distance 812 from one another in a second direction (e.g., along the x-axis). In some embodiments, the distance 812 is in a range of approximately 0.1 micrometers to 1 micrometer, or some other suitable value. The width 808 of the body structure 114b is in a range of, for example, approximately 0.5 micrometers to 2.4 micrometers, or some other suitable value. The length 810 of the body structure 114b is in a range of, for example, approximately 0.5 micrometers to 2.4 micrometers, or some other suitable value. The width 814 of each protrusion 114p is in a range of, for example, approximately 0.05 micrometers to 0.2 micrometers, or some other suitable value. The length 816 of each protrusion 114p is in a range of, for example, approximately 0.2 micrometers to 2 micrometers, or some other suitable value. In various embodiments, the semiconductor capacitor 112 may include a single protrusion (not shown). In still other embodiments, the semiconductor capacitor 112 may include 2 to 100 protrusions 114 p spaced across the width 808 of the body structure 114 b .

[0137] Figure 9A and Figure 9B Show Figure 4 Some embodiments of semiconductor capacitors 112 are shown in a cross-sectional view 900a and a top view 900b.

[0138] Reference Figure 9AAs shown in cross-sectional view 900a, the height 906 of the protrusion 114p of the first capacitor electrode 114 is in the range of approximately 0.06 microns to 0.5 microns, or some other suitable value. In some embodiments, the angle 902 between the opposing sidewalls of the protrusion 114p is in the range of approximately 35 degrees to 90 degrees, or some other suitable value. In various embodiments, the protrusion 114p has a rectangular shape when viewed in cross section.

[0139] Reference Figure 9B As shown in top view 900b, the plurality of protrusions 114p are arranged in an array including a plurality of columns and a plurality of rows. The protrusions 114p are spaced apart by a distance 912, which may be, for example, in a range of approximately 0.06 microns to 0.2 microns, or some other suitable value. The width 908 of the body structure 114b may be, for example, in a range of approximately 0.7 microns to 2.4 microns, or some other suitable value. The length 910 of the body structure 114b may be, for example, in a range of approximately 0.7 microns to 2.4 microns, or some other suitable value. The width 914 of each protrusion 114p may be, for example, in a range of approximately 0.09 microns to 0.7 microns, or some other suitable value. The length 916 of each protrusion 114p may be, for example, in a range of approximately 0.09 microns to 0.7 microns, or some other suitable value. In various embodiments, the semiconductor capacitor may include 1 to 100 protrusions 114p.

[0140] Figure 10A and Figure 10B Show Figure 5 Some embodiments of a semiconductor capacitor 112 are shown in a cross-sectional view 1000a and a top view 1000b.

[0141] Reference Figure 10A As shown in the cross-sectional view 1000 a , the height 1002 of the protrusion 114 p of the first capacitor electrode 114 is in a range of approximately 0.35 μm to 2 μm, or some other suitable value.

[0142] Reference Figure 10BAs shown in top view 1000b, the plurality of protrusions 114p are arranged in an array comprising a plurality of columns and a plurality of rows. The protrusions 114p are spaced apart by a distance 1006, which may be, for example, in the range of approximately 0.1 micrometers to 0.5 micrometers, or some other suitable value. The width 1008 of the body structure 114b may be, for example, in the range of approximately 0.5 micrometers to 2.4 micrometers, or some other suitable value. The length 1010 of the body structure 114b may be, for example, in the range of approximately 0.5 micrometers to 2.4 micrometers, or some other suitable value. In some embodiments, when viewed in top view, the protrusions 114p have a circular shape. The diameter 1004 of the protrusions 114p may be, for example, in the range of approximately 0.09 micrometers to 0.2 micrometers, or some other suitable value.

[0143] Figures 11 to 37 Various cross-sectional views 1100 through 3700 illustrate some embodiments of a method of forming an image sensor including a pixel having a semiconductor capacitor disposed on a substrate. Figures 11 to 37 The cross-sectional views 1100 to 3700 shown in FIG are described with reference to the method, however, it should be understood that Figures 11 to 37 The structure shown in is not limited to the method described, but can exist independently of the method described. Figures 11 to 37 It is described as a series of actions, but it should be understood that these actions are not limited, the order of the actions can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0144] like Figure 11 As shown in cross-sectional view 1100 of FIG, a plurality of photodetectors 106, a plurality of transfer transistors 108, and a floating diffusion node 111 are formed within first substrate 304. First substrate 304 includes a first dopant type (e.g., p-type). Photodetector 106 is or includes a doped region of first substrate 304 including a second dopant type (e.g., n-type) opposite the first dopant type. Photodetector 106 can be formed, for example, by ion implantation or some other suitable process. Transfer transistors 108 are formed on front side surface 304f of first substrate 304. Transfer transistors 108 each include a gate electrode extending into first substrate 304, a gate dielectric disposed between first substrate 304 and the gate electrode, and sidewall spacers disposed along sidewalls of the gate electrode and the gate dielectric. Floating diffusion node 111 is formed within first substrate 304 by, for example, ion implantation or another suitable process. Floating diffusion node 111 includes the second dopant type (e.g., n-type). The first substrate 304 may be or may include, for example, silicon, single crystal silicon, epitaxial silicon, germanium, silicon germanium, or another suitable semiconductor material.

[0145] like Figure 12 As shown in cross-sectional view 1200 of FIG, a first interconnect structure 306 is formed on the front side surface 304 f of the first substrate 304, thereby defining the first IC die 102. The first interconnect structure 306 includes a plurality of conductive contacts 324, a plurality of conductive wires 326, a plurality of vias 328, and a plurality of bonding pads 330 disposed within a dielectric structure 322. The various layers in the first interconnect structure 306 can be formed, for example, by a single damascene process, a dual damascene process, some other suitable fabrication process, or the like.

[0146] like Figure 13 As shown in cross-sectional view 1300 of FIG, trench isolation structure 312 is formed in first substrate 304 between adjacent photodetectors 106. Trench isolation structure 312 includes a trench fill layer 316 extending into backside surface 304 b of first substrate 304 and a liner layer 314 disposed between trench fill layer 316 and first substrate 304. In some embodiments, the process for forming the isolation structure includes: patterning the backside surface 304 b of the first substrate 304 to form a trench extending into the first substrate 304; depositing a liner layer 314 over the trench (e.g., by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.); depositing a trench fill layer 316 in the trench (e.g., by PVD, CVD, ALD, sputtering, electroplating, etc.); and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the liner layer 314 and the trench fill layer 316.

[0147] like Figure 14 As shown in cross-sectional view 1400 of FIG, a second substrate 110 is provided and an isolation structure 136 is formed in the second substrate 110. In some embodiments, the process for forming the isolation structure 136 includes: patterning the front surface 110f of the second substrate 110 to form one or more trenches extending into the second substrate 110; depositing (e.g., by PVD, CVD, ALD, etc.) an isolation material (e.g., silicon dioxide, silicon nitride, etc.) in the one or more trenches; and performing a planarization process (e.g., a CMP process) on the isolation material. The second substrate 110 includes a first doping type (e.g., p-type). The second substrate 110 may be or may include, for example, silicon, single crystal silicon, epitaxial silicon, germanium, silicon germanium, or another suitable semiconductor material.

[0148] like Figure 15 As shown in the cross-sectional view 1500 of FIG, a dielectric layer 1502, a hard mask layer 1504, and a mask layer 1506 are formed on the front side surface 110f of the second substrate 110. In some embodiments, the dielectric layer 1502 (e.g., comprising silicon dioxide) and the hard mask layer 1504 (e.g., comprising silicon dioxide, a metal nitride (e.g., silicon nitride), a metal, etc.) are deposited by PVD, CVD, ALD, or another suitable growth or deposition process. The mask layer 1506 is formed over the hard mask layer 1504 and includes sidewalls defining an opening 1508 over the second substrate 110. The mask layer 1506 may be or may include, for example, a photoresist or some other suitable material.

[0149] like Figure 16 As shown in the cross-sectional view 1600, according to the mask layer ( Figure 15 A patterning process is performed on the second substrate 110 (shown as 1506) to form a plurality of trenches 1602 extending into the front surface 110f of the second substrate 110. In some embodiments, the patterning process includes performing a dry etching process (e.g., plasma etching, ion beam etching, reactive ion etching, etc.) or some other suitable process. Each trench 1602 is defined by opposing sidewalls and the top surface of the second substrate 110.

[0150] like Figure 17 As shown in the cross-sectional view 1700 of FIG. 1 , a removal process is performed to remove the dielectric layer ( Figure 16 1502) and the hard mask layer ( Figure 16 1504), and a well region 334 is formed in the second substrate 110. The well region 334 includes a first dopant type (e.g., p-type) and can be formed by an ion implantation process or some other suitable process. In some embodiments, the removal process includes performing a wet etching process or some other suitable process. In various embodiments, after forming the well region 334, an annealing process is performed on the second substrate 110.

[0151] like Figure 18 As shown in cross-sectional view 1800 of FIG, a dielectric liner layer 1802 and a mask layer 1804 are formed over the second substrate 110. The dielectric liner layer 1802 (e.g., comprising silicon dioxide) can be deposited by, for example, CVD, PVD, ALD, or another suitable growth or deposition process. The dielectric liner layer 1802 lines the trench 1602 and extends along the front surface 110f of the second substrate 110. The mask layer 1804 includes opposing sidewalls that define an opening over the trench 1602. The mask layer 1804 can be or include, for example, a photoresist or some other suitable material.

[0152] like Figure 19As shown in cross-sectional view 1900 of FIG, a doped capacitor region 116 is formed in the second substrate 110. The doped capacitor region 116 lines the trench 1602 and extends along a portion of the frontside surface 110f of the second substrate 110. For example, the doped capacitor region 116 extends along opposing sidewalls and a lower surface of the second substrate 110 that define the trench 1602. The doped capacitor region 116 includes a second doping type (e.g., n-type). In some embodiments, the doped capacitor region 116 has a higher doping concentration than the well region 334. In various embodiments, the doped capacitor region 116 is formed by a doping process (e.g., a beam-line doping process, a plasma doping process, etc.) or some other suitable process. In various embodiments, the doping process is performed based on the mask layer 1804 and through the dielectric liner layer 1802, wherein the dielectric liner layer 1802 is configured to mitigate damage to the second substrate 110 during the doping process.

[0153] like Figure 20 As shown in the cross-sectional view 2000 of FIG. 2 , a removal process is performed to remove the dielectric liner layer ( Figure 19 In some embodiments, the removal process includes a wet etching process, a dry etching process, or some other suitable process.

[0154] like Figure 21 As shown in the cross-sectional view 2100 of FIG, a gate dielectric layer 134 is deposited over the second substrate 110. The gate dielectric layer 134 extends along the front surface 110f of the second substrate 110 and lines the trench 1602. The gate dielectric layer 134 can be deposited over the second substrate 110 by, for example, CVD, PVD, ALD, or another suitable growth or deposition process. In some embodiments, the gate dielectric layer 134 is or includes silicon dioxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, some other suitable dielectric material, or any combination thereof.

[0155] like Figure 22 As shown in the cross-sectional view 2200 of FIG, a patterning process is performed on the gate dielectric layer 134. The patterning process removes the gate dielectric layer 134 from above the doped capacitor region 116. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the second substrate 110; etching the gate dielectric layer 134 according to the mask layer; and performing a removal process to remove the mask layer.

[0156] like Figure 23As shown in cross-sectional view 2300 of FIG, a capacitor dielectric layer 118 is formed over the doped capacitor region 116 lining the trench 1602. The capacitor dielectric layer 118 extends along the doped capacitor region 116. In some embodiments, the process for forming the capacitor dielectric layer 118 includes depositing (e.g., by PVD, CVD, ALD, etc.) the capacitor dielectric layer 118 over the second substrate 110 and patterning the capacitor dielectric layer 118 to remove the capacitor dielectric layer 118 from over the gate dielectric layer 134. The capacitor dielectric layer 118 may be or may include, for example, silicon dioxide, hafnium oxide, zirconium oxide, aluminum oxide, or some other suitable material. Furthermore, the capacitor dielectric layer 118 is formed to have a thickness ranging from approximately 19 angstroms to 75 angstroms, or some other suitable value. In various embodiments, the gate dielectric layer 134 has a thickness greater than the thickness of the capacitor dielectric layer 118. In still other embodiments, the dielectric material of the capacitor dielectric layer 118 is different from the dielectric material of the gate dielectric layer 134 .

[0157] like Figure 24 As shown in the cross-sectional view 2400, a pair of trenches ( Figure 23 1602). The gate electrode material 2402 overlies and extends along the gate dielectric layer 134 and the capacitor dielectric layer 118. In some embodiments, the gate electrode material 2402 is deposited by CVD, PVD, ALD, electroplating, or some other suitable growth or deposition process. The gate electrode material 2402 may be or include, for example, polysilicon, a metal (e.g., aluminum, tungsten, titanium, copper, etc.), or some other suitable material. In various embodiments, the gate electrode material 2402 includes polysilicon. In such embodiments, an ion implantation process is performed after depositing the gate electrode material 2402 to dope the gate electrode material 2402 with one or more dopants, and an annealing process is performed on the gate electrode material 2402 after the ion implantation process.

[0158] like Figure 25 As shown in cross-sectional view 2500 of , a mask layer 2502 is formed over the gate electrode material 2402. The mask layer 2502 may be or may include, for example, photoresist or some other material.

[0159] like Figure 26 As shown in the cross-sectional view 2600, according to the mask layer ( Figure 25 2502) for the gate electrode material ( Figure 25A patterning process is performed on the gate dielectric layer 134 and the capacitor dielectric layer 118 (shown as 2402), thereby defining the gate electrode 132, the first capacitor electrode 114, and a plurality of gate structures 2602 above the second substrate 110. In some embodiments, the patterning process includes performing a dry etching process (e.g., plasma etching, ion beam etching, reactive ion etching, etc.) or some other suitable process. The gate structures 2602 each include a gate electrode 132 located above the gate dielectric layer 134. In various embodiments, the gate electrode 132 and the first capacitor electrode 114 are formed simultaneously. The first capacitor electrode 114 includes a body structure 114b overlying the front side surface 110f of the second substrate 110 and a plurality of protrusions 114p extending from the body structure 114b into the second substrate 110. The doped capacitor region 116 extends along the long sidewalls and lower surface of each of the protrusions 114p.

[0160] like Figure 27 As shown in cross-sectional view 2700 of FIG, sidewall spacer structures 332 are formed along sidewalls of the first capacitor electrode 114 and sidewalls of the gate electrode 132. The sidewall spacer structures 332 may be or may include, for example, silicon nitride, silicon carbide, silicon oxynitride, or some other suitable dielectric material.

[0161] like Figure 28 As shown in the cross-sectional view 2800 of , a doping process is performed on the second substrate 110 to form a plurality of source / drain regions 130 and a capacitor contact region 120 in the second substrate 110. This partially defines a plurality of pixel transistors 122 to 128 and a semiconductor capacitor 112 on the front side surface 110f of the second substrate 110. In some embodiments, the plurality of pixel transistors 122 to 128 and the semiconductor capacitor 112 are formed simultaneously. In various embodiments, the doping process includes performing an ion implantation process on the second substrate 110. The plurality of source / drain regions 130 and the capacitor contact region 120 include a second doping type (e.g., n-type) and have a higher doping concentration than the well region 334. In various embodiments, the process for forming the semiconductor capacitor 112 includes Figures 15 to 28 The processing steps shown and / or described in .

[0162] like Figure 29As shown in cross-sectional view 2900 of FIG, an inter-level dielectric (ILD) layer 2902, a hard mask layer 2904, and a mask layer 2906 are formed over the second substrate 110. The ILD layer 2902 may be or may include, for example, silicon dioxide or a similar material. The mask layer 2906 may be, for example, a photoresist or some other suitable material. In yet other embodiments, the ILD layer 2902 and the hard mask layer 2904 may be deposited over the second substrate 110 by CVD, PVD, ALD, or some other suitable growth or deposition process.

[0163] like Figure 30 As shown in the cross-sectional view 3000, according to the mask layer ( Figure 29 A patterning process is performed on the ILD layer 2902 and the hard mask layer 2904 (as shown in FIG2906) to form a plurality of openings 3002 in the ILD layer 2902 over the second substrate 110. In some embodiments, the patterning process includes performing a dry etching process (e.g., plasma etching, ion beam etching, reactive ion etching, etc.) or some other suitable process.

[0164] like Figure 31 As shown in the cross-sectional view 3100 of FIG, a plurality of conductive contacts 324 are formed in the ILD layer 2902 on the second substrate 110. In some embodiments, the process for forming the plurality of conductive contacts 324 includes: forming a plurality of conductive contacts 324 on the second substrate 110 and the plurality of openings ( Figure 30 As shown in 3002, a conductive material (eg, aluminum, titanium, tungsten, etc.) is deposited (eg, by CVD, PVD, electroplating, etc.) and a planarization process (eg, CMP process) is performed on the conductive material.

[0165] like Figure 32 As shown in the cross-sectional view 3200 of FIG, a second interconnect structure 308 is formed on the front side surface 110f of the second substrate 110. The second interconnect structure 308 includes the plurality of conductive contacts 324, a plurality of conductive wires 326, a plurality of vias 328, and a plurality of bonding pads 330 disposed in the dielectric structure 322. The ILD layer ( Figure 31 2902) is a portion of the dielectric structure 322. In various embodiments, the layers in the second interconnect structure 308 may be formed by, for example, a single damascene process, a dual damascene process, some other suitable fabrication process, or the like.

[0166] like Figure 33As shown in cross-sectional view 3300 of FIG, a through-substrate via (TSV) 321 is formed extending through the second substrate 110 to the second interconnect structure 308. The TSV 321 is electrically coupled to a conductive structure (e.g., a conductive wire) in the second interconnect structure 308. In some embodiments, the process for forming the TSV 321 includes: patterning the backside surface 110b of the second substrate 110 to form a TSV opening extending from the second substrate 110 to the second interconnect structure 308; depositing a conductive material within the TSV opening (e.g., by CVD, PVD, ALD, electroplating, etc.); and performing a planarization process (e.g., a CMP process) on the conductive material.

[0167] like Figure 34 As shown in the cross-sectional view 3400 of , a plurality of bonding pads 330 and a bonding dielectric layer 3402 are formed on the backside surface 110 b of the second substrate 110 , thereby defining the second IC die 104 .

[0168] like Figure 35 As shown in cross-sectional view 3500 of FIG, a first bonding process is performed to bond the first IC die 102 to the second IC die 104. After the first bonding process, the first interconnect structure 306 of the first IC die 102 is bonded to the second interconnect structure 308 of the second IC die 104 at a first bonding interface. In some embodiments, the first bonding process includes a eutectic bonding process, a fusion bonding process, a dielectric-to-dielectric bonding process, a metal-to-metal bonding process, some other suitable bonding process, or any combination thereof. In various embodiments, the first bonding interface between the first IC die 102 and the second IC die 104 includes a dielectric-to-dielectric bond and a metal-to-metal bond.

[0169] like Figure 36As shown in cross-sectional view 3600 of FIG, a third IC die 202 is formed, and a second bonding process is performed to bond the third IC die 202 to the second IC die 104. In various embodiments, forming the third IC die 202 includes forming a plurality of semiconductor devices 336, 338 on the front side surface 340f of the third substrate 340 and forming a third interconnect structure 310 on the front side surface 340f of the third substrate 340. After the second bonding process, the third interconnect structure 310 of the third IC die 202 is bonded to the bonding pads 330 and the bonding dielectric layer 3402 disposed on the back side surface 110b of the second substrate 110 at a second bonding interface. In some embodiments, the second bonding process includes a eutectic bonding process, a fusion bonding process, a dielectric-to-dielectric bonding process, a metal-to-metal bonding process, some other suitable bonding process, or any combination thereof. In various embodiments, the second bonding interface between the second IC die 104 and the third IC die 202 includes a dielectric-to-dielectric bond and a metal-to-metal bond. In various embodiments, each layer in the third interconnect structure 310 may be formed by, for example, a single damascene process, a dual damascene process, some other suitable fabrication process, or the like.

[0170] like Figure 37 As shown in the cross-sectional view 3700 of FIG, a plurality of color filters 318 are formed on the backside surface 304b of the first substrate 304, and a plurality of microlenses 320 are formed on the plurality of color filters 318. The color filters 318 can be formed by depositing corresponding color filter layers corresponding to the plurality of color filters 318 and patterning the corresponding color filter layers. The microlenses 320 can be formed by depositing a microlens material on the color filters 318 and patterning the microlens material to form the plurality of microlenses 320. In various embodiments, the color filters 318 can be formed by depositing a microlens material on the color filters 318 and patterning the microlens material to form the plurality of microlenses 320. Figure 35 The first bonding process is shown before forming the plurality of color filters 318 and the plurality of microlenses 320 on the backside surface 304b of the first substrate 304. For example, the plurality of color filters 318 and the plurality of microlenses 320 may be formed immediately after forming the trench isolation structure 312.

[0171] Figures 38 to 43 Shows alternatives Figures 15 to 28 The cross-sectional views 3800 to 4300 of some embodiments of the actions performed in the actions, such that Figures 11 to 37 The method shown can be used as an alternative Figures 11 to 14 Proceed to Figures 38 to 43 , and then Figure 43 Proceed to Figures 29 to 37 (jump over Figures 15 to 28 ). In various embodiments, Figures 38 to 43Cross-sectional views 3800 through 4300 illustrate some other embodiments of forming semiconductor capacitor 112 .

[0172] although Figures 38 to 43 The cross-sectional views 3800 to 4300 shown in FIG are described with reference to one method, however, it should be understood that Figures 38 to 43 The structure shown in is not limited to the method described, but can exist independently of the method described. Figures 38 to 43 It is described as a series of actions, but it should be understood that these actions are not limited, the order of the actions can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0173] like Figure 38 As shown in the cross-sectional view 3800 of FIG, a dielectric layer 3802, a first hard mask layer 3804, and a first mask layer 3806 are formed on the front surface 110f of the second substrate 110. The dielectric layer 3802 and the first hard mask layer 3804 can be deposited on the second substrate 110 by, for example, PVD, CVD, ALD, or some other suitable growth or deposition process. The first mask layer 3806 is formed on the first hard mask layer 3804 and includes sidewalls that define an opening 3808.

[0174] like Figure 39 As shown in the cross-sectional view 3900, according to the first mask layer ( Figure 38 A first patterning process is performed on the second substrate 110 (shown as 3806) to form a plurality of trenches 3902 extending into the front surface 110f of the second substrate 110. In some embodiments, the first patterning process includes performing a dry etching process (e.g., plasma etching, ion beam etching, reactive ion etching, etc.) or some other suitable process. A removal process may be performed to remove the first hard mask layer 3804 (not shown).

[0175] like Figure 40 As shown in cross-sectional view 4000 of FIG, a second hard mask layer 4002 is formed over the second substrate 110, and a second patterning process is performed on the second substrate 110 to enlarge the trench 3902. In some embodiments, the second patterning process includes performing a wet etching process or some other suitable process. In various embodiments, the second patterning process includes exposing the second substrate 110 to tetramethyl ammonium hydroxide (TMAH) or some other suitable wet etchant. A removal process may be performed to remove the second hard mask layer 4002.

[0176] like Figure 41As shown in the cross-sectional view 4100 of , a third hard mask layer 4102 is formed on the second substrate 110, and a third patterning process is performed on the second substrate 110 to enlarge the trench 3902. In various embodiments, the trench 3902 is defined by opposite sidewalls of the second substrate 110. In some embodiments, the third patterning process includes performing a wet etching process or some other suitable process. For example, the third patterning process includes exposing the second substrate 110 to TMAH or some other suitable wet etchant. A removal process may be performed to remove the third hard mask layer 4102 and the dielectric layer 3802 (not shown). Therefore, in some embodiments, the plurality of trenches 3902 may be formed by the following operations: i) performing dry etching (such as Figure 39 ii) performing a first wet etch (as shown in Figure 40 ); and iii) performing a second wet etch (as shown in Figure 41 ).

[0177] like Figure 42 As shown in the cross-sectional view 4200 of FIG. 4 , a doped capacitor region 116 and a well region 334 are formed in the second substrate 110. The doped capacitor region 116 is lined on the trench 3902 and extends along a portion of the front surface 110f of the second substrate 110. In some embodiments, the doped capacitor region 116 may be formed by Figures 17 to 20 The doped capacitor region 116 and the well region 334 are formed using the processes shown and / or described in .

[0178] like Figure 43 As shown in the cross-sectional view 4300 of FIG, a plurality of pixel transistors 122 to 128 and a semiconductor capacitor 112 are formed on the second substrate 110. The semiconductor capacitor 112 includes a doped capacitor region 116, a capacitor dielectric layer 118, and a first capacitor electrode 114. The first capacitor electrode 114 includes a body structure 114b and a plurality of protrusions 114p. When viewed in cross section, the plurality of protrusions 114p may have a triangular shape. In some embodiments, the plurality of pixel transistors 122 to 128 and a semiconductor capacitor 112 may be formed by Figures 21 to 28 The plurality of pixel transistors 122 to 128 and the semiconductor capacitor 112 are formed using the processes shown and / or described in .

[0179] Figures 44 to 47 Shows alternatives Figures 14 to 20 The cross-sectional views 4400 to 4700 of some embodiments of the actions performed in the actions, such that Figures 11 to 37 The method shown can be used as an alternative Figures 11 to 13 Proceed to Figures 44 to 47 , and then Figure 47 Proceed to Figures 21 to 37 (jump over Figures 14 to 20 ).

[0180] although Figures 44 to 47 The cross-sectional views 4400 to 4700 shown in FIG are described with reference to one method, however, it should be understood that Figures 44 to 47 The structure shown in is not limited to the method described, but can exist independently of the method described. Figures 44 to 47 It is described as a series of actions, but it should be understood that these actions are not limited, the order of the actions can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0181] like Figure 44 As shown in the cross-sectional view 4400 of FIG. 4 , a second substrate 110 is provided and an isolation structure 136 is formed in the second substrate 110. In some embodiments, as shown in FIG. Figure 14 Isolation structure 136 is formed as shown and / or described in FIG.

[0182] like Figure 45 As shown in the cross-sectional view 4500 of FIG. 4 , a plurality of trenches 1602 and a well region 334 are formed in the second substrate 110. In some embodiments, the Figures 15 to 17 The trench 1602 and the well region 334 are formed as shown and / or described in FIG.

[0183] like Figure 46 As shown in the cross-sectional view 4600 of FIG, a doped epitaxial layer 4602 is formed on the second substrate 110. The doped epitaxial layer 4602 extends along the front side surface 110f of the second substrate 110 and is lined on the second substrate 110. The doped epitaxial layer 4602 is formed to have a second doping type (e.g., n-type). The doped epitaxial layer 4602 can be deposited on the second substrate 110 by, for example, an epitaxial deposition process, and the doped epitaxial layer 4602 can be in-situ doped with the second doping type (e.g., n-type) during the epitaxial deposition process.

[0184] like Figure 47 As shown in the cross-sectional view 4700 of FIG. 4 , the doped epitaxial layer ( Figure 46 4602) to perform a patterning process, thereby forming a doped capacitor region 116. The patterning process includes forming a doped epitaxial layer ( Figure 46 A mask layer (not shown) is formed over the substrate 4602 and a dry etching process (eg, plasma etching, ion beam etching, reactive ion etching, etc.) or some other suitable etching process is performed.

[0185] Figure 48Some embodiments of method 4800 for forming an image sensor including a pixel having a semiconductor capacitor disposed on a substrate are shown. Although method 4800 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Thus, in some embodiments, the actions may be performed in an order different from the order shown and / or may be performed simultaneously. Furthermore, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed separately or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0186] At act 4802 , a plurality of photodetectors, a floating diffusion node, and a plurality of transfer transistors are formed within and / or on a first substrate. Figure 11 A cross-sectional view 1100 corresponding to some embodiments of act 4802 is shown.

[0187] At act 4804, a first interconnect line structure is formed on a first substrate, thereby defining a first IC die. Figure 12 A cross-sectional view 1200 corresponding to some embodiments of act 4804 is shown.

[0188] At act 4806, the second substrate is etched to form a plurality of trenches extending into the frontside surface of the second substrate. Figures 15 to 17 Various cross-sectional views 1500 - 1700 are shown corresponding to some embodiments of act 4806 . Figures 38 to 41 Various cross-sectional views 3800 - 4100 are shown corresponding to some other embodiments of act 4806 .

[0189] At act 4808, a doped capacitor region is formed in or on the second substrate, wherein the doped capacitor region lines the plurality of trenches. Figures 18 to 20 Various cross-sectional views 1800 - 2000 are shown corresponding to some embodiments of act 4808 . Figure 42 A cross-sectional view 4200 corresponding to some other embodiments of act 4808 is shown. Figure 46 and Figure 47 Various cross-sectional views 4600 and 4700 corresponding to further embodiments of act 4808 are shown.

[0190] At act 4810, a capacitor dielectric layer is formed on a second substrate, wherein the capacitor dielectric layer lines the plurality of trenches. Figure 23 Cross-sectional view 2300 corresponding to some embodiments of act 4810 is shown.

[0191] At act 4812, a first capacitor electrode is formed on the capacitor dielectric layer and a plurality of gate electrodes are formed over the second substrate, wherein the first capacitor electrode includes a protrusion disposed in the plurality of trenches. Figures 24 to 26 Various cross-sectional views 2400 - 2600 corresponding to some embodiments of act 4812 are shown.

[0192] At act 4814, the second substrate is doped to form source / drain regions on opposite sides of the gate electrode and to form a capacitor contact region adjacent to the doped capacitor region, thereby defining a plurality of pixel transistors and semiconductor capacitors on the second substrate. Figure 28 Cross-sectional view 2800 corresponding to some embodiments of act 4814 is shown.

[0193] At act 4816, a second interconnect line structure is formed on the frontside surface of the second substrate. Figures 29 to 32 Various cross-sectional views 2900 - 3200 corresponding to some embodiments of act 4816 are shown.

[0194] At act 4818, TSVs are formed in the second substrate and a plurality of bond pads are formed on the backside surface of the second substrate, thereby defining a second IC die. Figure 33 and Figure 34 Cross-sectional views 3300 and 3400 corresponding to some embodiments of act 4818 are shown.

[0195] At act 4820, the first IC die is bonded to the second IC die. Figure 35 Cross-sectional view 3500 corresponding to some embodiments of act 4820 is shown.

[0196] At act 4822, a plurality of logic transistors and a third interconnect line structure are formed on a third substrate, thereby defining a third IC die. Figure 36 Cross-sectional view 3600 corresponding to some embodiments of act 4822 is shown.

[0197] At act 4824, a third IC die is bonded to the second IC die. Figure 36 Cross-sectional view 3600 corresponding to some embodiments of act 4824 is shown.

[0198] Therefore, in some embodiments, the present invention relates to an image sensor comprising pixels disposed across a first IC die and a second IC die, wherein semiconductor capacitors are disposed within and / or on a substrate of the second IC die.

[0199] In some embodiments, the present application provides an image sensor comprising: a first integrated circuit (IC) die including a plurality of photodetectors disposed within a first substrate; a second IC die stacked vertically with the first IC die, wherein the second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate, wherein the semiconductor capacitor includes: a first capacitor electrode overlying the second substrate and including a protrusion disposed in the second substrate; a capacitor dielectric layer disposed between the first capacitor electrode and the second substrate; and a doped capacitor region disposed within the second substrate and underlying the first capacitor electrode; wherein the plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

[0200] In some embodiments, the present application provides an image sensor comprising: a plurality of photodetectors and floating diffusion nodes disposed within a first substrate, wherein the floating diffusion nodes are disposed between the plurality of photodetectors; a plurality of pixel transistors disposed on a second substrate below the first substrate, wherein the plurality of pixel transistors includes a first pixel transistor having a first source / drain region directly electrically coupled to the floating diffusion node; and a semiconductor capacitor disposed on the second substrate, wherein the semiconductor capacitor includes a doped capacitor region disposed on the second substrate, a first capacitor electrode disposed above the doped capacitor region, and a capacitor dielectric layer directly between the doped capacitor region and the first capacitor electrode, wherein the first capacitor electrode includes a plurality of protrusions disposed in the second substrate, wherein the doped capacitor region continuously wraps laterally around the plurality of protrusions, and wherein the semiconductor capacitor is directly electrically coupled to the second source / drain region of the first pixel transistor.

[0201] In various embodiments, the present application provides a method for forming an image sensor, the method comprising: forming a plurality of photodetectors and floating diffusion nodes within a first substrate; etching a second substrate to form a plurality of trenches disposed in a front surface of the second substrate; forming a doped capacitor region on the second substrate, wherein the doped capacitor region extends along sidewalls of the second substrate defining the plurality of trenches; forming a capacitor dielectric layer over the doped capacitor region, wherein the capacitor dielectric layer lines the plurality of trenches; forming a first capacitor electrode on the capacitor dielectric layer to define a semiconductor capacitor, wherein the first capacitor electrode comprises a body structure over the second substrate and a plurality of protrusions disposed in the plurality of trenches; forming a plurality of pixel transistors on the second substrate, wherein the plurality of pixel transistors comprises a plurality of gate electrodes over the second substrate; and bonding the second substrate to the first substrate, wherein a first transistor of the plurality of pixel transistors is electrically coupled between the floating diffusion node and the semiconductor capacitor.

[0202] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An image sensor, characterized in that: include: A first integrated circuit die includes a plurality of light detectors disposed within a first substrate; A second integrated circuit die is stacked vertically with the first integrated circuit die, wherein the second integrated circuit die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate, wherein the semiconductor capacitor includes: a first capacitor electrode overlying the second substrate and comprising a protrusion disposed in the second substrate; a capacitor dielectric layer disposed between the first capacitor electrode and the second substrate; and a doped capacitor region disposed in the second substrate and below the first capacitor electrode; and The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

2. The image sensor according to claim 1, wherein: Also includes: A floating diffusion node is disposed in the first substrate near the plurality of photodetectors, wherein a first pixel transistor among the plurality of pixel transistors is electrically coupled between the floating diffusion node and the semiconductor capacitor.

3. The image sensor according to claim 1, wherein: The plurality of pixel transistors include a first pixel transistor disposed on the second substrate, wherein the first pixel transistor includes a gate electrode located above the second substrate, wherein a top surface of the gate electrode is vertically aligned with a top surface of the first capacitor electrode.

4. The image sensor according to claim 3, wherein: The first pixel transistor includes a source / drain region disposed in the second substrate and adjacent to the gate electrode, wherein the source / drain region is directly electrically coupled to the first capacitor electrode or the doped capacitor region.

5. The image sensor according to claim 4, wherein: The bottom of the doped capacitor region is disposed below the bottom of the source / drain region.

6. The image sensor according to claim 4, wherein: The first pixel transistor includes a gate dielectric disposed between the gate electrode and the second substrate, wherein a top surface of the gate dielectric is aligned with a top surface of the capacitor dielectric layer.

7. The image sensor according to claim 1, wherein: Wherein the first capacitor electrode includes a body structure overlying the protrusion, wherein a height of the body structure is different from a height of the protrusion, and wherein a width of the doped capacitor region is different from a width of the body structure.

8. An image sensor, characterized in that: include: A plurality of photodetectors and a floating diffusion node are disposed in the first substrate, wherein the floating diffusion node is disposed between the plurality of photodetectors; a plurality of pixel transistors disposed on a second substrate below the first substrate, wherein the plurality of pixel transistors includes a first pixel transistor having a first source / drain region directly electrically coupled to the floating diffusion node; as well as A semiconductor capacitor is disposed on the second substrate, wherein the semiconductor capacitor includes a doped capacitor region disposed on the second substrate, a first capacitor electrode disposed above the doped capacitor region, and a capacitor dielectric layer disposed directly between the doped capacitor region and the first capacitor electrode, wherein the first capacitor electrode includes a plurality of protrusions disposed in the second substrate, wherein the doped capacitor region laterally continuously wraps around the plurality of protrusions, and wherein the semiconductor capacitor is directly electrically coupled to the second source / drain region of the first pixel transistor.

9. The image sensor according to claim 8, wherein: The plurality of pixel transistors include a source follower transistor disposed on the second substrate, wherein a gate electrode of the source follower transistor is directly electrically coupled to the first source / drain region.

10. The image sensor according to claim 8, wherein The doped capacitor region extends vertically continuously from the front surface of the second substrate to a point vertically below a bottom of the first source / drain region.

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