Small-area direct-current offset cancellation circuit
By introducing a logic selection switch unit in the intermediate frequency link to control the direction and magnitude of the current, the problem of high idle rate of the current source in the intermediate frequency circuit is solved, the circuit area and power consumption are optimized, and the circuit efficiency and response speed are improved.
Patent Information
- Application Number
- CN202422402853.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-09-30
AI Technical Summary
In a zero-IF transceiver architecture, the DC offset of the IF circuit causes the subsequent circuit to deviate from the normal operating point. In the existing technology, each IF link requires four current sources, which has a high idle rate and causes area waste.
A small-area DC offset cancellation circuit is used to control the current direction and magnitude through a logic-selectable switch unit. Only two current sources are used to complete the current control, reducing the number of current sources and optimizing the area and power consumption.
The number of current sources used is effectively reduced, the circuit area and power consumption are reduced, and the efficiency and response speed of the circuit are improved.
Smart Images
Figure CN223320792U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to a small-area DC offset elimination circuit. Background Art
[0002] In a zero-IF transceiver architecture, the IF circuit has a large DC offset. The offset voltage after high-gain amplification in the IF circuit can cause the subsequent circuit to deviate from the normal DC operating point, thereby seriously affecting the function and performance of the circuit. Therefore, a small-area DC offset cancellation circuit is generally required to suppress it.
[0003] As attached Figure 1 As shown, in the related technology, two current sources are connected to the P and N terminals of the intermediate frequency link. The current values are controlled by the code sent by the digital logic module. One current source is responsible for injecting current into the link when it detects a low voltage, and the other is responsible for extracting current from the link when it detects a high voltage. While the current sources are extracting and injecting, the voltages at the P and N terminals are continuously detected and searched for a balanced value through the digital logic circuit to eliminate the DC offset of the link. This current-compensated DCOC circuit uses current injection and extraction to calibrate the DC voltage of the differential circuit. The comparison result is output to the digital module through a comparator connected to the differential terminal. The codeword is then optimized in the digital domain through binary search.
[0004] However, IF links typically have multiple stages. If DCOC correction is required for each stage, two current sources are connected to each end of the differential link, for a total of four current sources per stage. Furthermore, current extraction and injection cannot be performed simultaneously at each end, meaning only two current sources are active at a time, while the other two remain idle. If n stages require correction, the total number of required current sources is n*4, and the number of idle current sources is n*2. This high idle rate of current sources results in significant area waste, leaving room for improvement. Summary of the Invention
[0005] In order to reduce the area waste caused by the idleness of current sources in an intermediate frequency link, the present application provides a small-area DC offset cancellation circuit.
[0006] The present application provides a small-area DC offset cancellation circuit, which adopts the following technical solution:
[0007] A small-area DC offset cancellation circuit includes a first reference current source and a first current mirror unit module connected thereto, and a second reference current source and a second current mirror unit module connected thereto, and further includes a first minimum current source module, a second minimum current source module, an output current on-off switch module, and a logic gate switch unit;
[0008] The first minimum current source module is connected in parallel with the first current mirror unit module to lead to a first output end, and the second minimum current source module is connected in parallel with the second current mirror unit module to lead to a second output end; the first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end;
[0009] The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end.
[0010] Optionally, the first minimum current source module includes a first current source and a first switch S1, one end of the first current source is electrically connected to a power supply, and the other end of the first current source is electrically connected to one end of the first switch S1;
[0011] The other end of the first switch S1 is electrically connected to the first branch switch of the first current mirror unit module, and the first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module.
[0012] Optionally, the second minimum current source module includes a second current source and a second switch S2, one end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2;
[0013] The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module, and the second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
[0014] Optionally, a first low-pass filter circuit is connected between one end of the first reference current source and the first current mirror unit module.
[0015] Optionally, a second low-pass filter circuit is connected between one end of the second reference current source and the second current mirror unit module.
[0016] Optionally, the output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4, one end of the current on-off switch S3 is connected to the first output end, and the other end of the current on-off switch S3 is connected to one end of the logic selection switch unit; one end of the current on-off switch S4 is connected to the second output end, and the other end of the current on-off switch S4 is connected to the other end of the logic selection switch unit.
[0017] Optionally, the logic gating switch unit includes a gating switch S5, a gating switch S6, a gating switch S7 and a gating switch S8 connected end to end, one end of the current on-off switch S3 is connected between the gating switch S5 and the gating switch S6, and one end of the current on-off switch S4 is connected between the gating switch S7 and the gating switch S8.
[0018] Optionally, a switch S9 is provided in parallel at both ends of the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel at both ends of the filter resistor of the second low-pass filter circuit.
[0019] In summary, the present application includes at least one of the following beneficial technical effects: by adding a logic selection switch unit, the circuit can complete the control of the direction and magnitude of the current with only two current sources. The area of the current source is much larger than the logic selection switch unit, which optimizes the area by about half, reduces power consumption and wiring complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of a current compensation DCOC circuit in the related art.
[0021] Figure 2 1 is a circuit diagram of a small-area DC offset cancellation circuit according to an embodiment of the present application.
[0022] Figure 3 This is a logic block diagram of a logic selection switch unit mainly embodied in this application. DETAILED DESCRIPTION
[0023] The following describes the embodiments of the present application in detail, and examples of the embodiments are shown in the attached Figure 1-3 Shown in.
[0024] Throughout this specification, reference to the terms "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
[0025] The present application discloses a small area DC offset elimination circuit. Figure 2, including a first reference current source P_bias, a first current mirror unit module P_source, and a second reference current source N_bias and a second current mirror unit module N_sink. The first reference current source P_bias has a first end connected to a power supply VDD, and a second end connected to one end of the first current mirror unit module P_source. The second reference current source N_bias has a first end connected to ground, and a second end connected to one end of the second current mirror unit module N_sink.
[0026] It should be noted that the reference current sources P_bias and N_bias are generated by external reference currents and have equal current magnitudes. P_source and N_sink contain multiple current sources (seven in this circuit) with binary proportional relationships (64I, 32I, 16I, 8I, 4I, 2I, and I). These current sources mirror the currents proportionally from the reference current sources P_bias and N_bias via bias voltages VBP and VBN, respectively. The switching of these current sources is controlled by p_code<6:0> and n_code<6:0>, respectively.
[0027] The small area DC offset cancellation circuit also includes a first minimum current source module P_fix, a second minimum current source module N_fix, an output current on-off switch module and a logic selection switch unit. The first minimum current source module P_fix is connected in parallel with the first current mirror unit module P_source to lead to the first output terminal, and the second minimum current source module N_fix is connected in parallel with the second current mirror unit module N_sink to lead to the second output terminal. The current size of N_fix and P_fix is the minimum current I, and the on-off of the switch is determined by the highest bit code. <7> The inverse signal code_b <7> Control, its function is to ensure the monotonicity of output current with code change. <7> =0, and the absolute value of the output current of Psource and Nsink is increased by I when code < 128, to prevent the output current from being 0 when code = 127 and code 128.
[0028] The first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end. The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end, thereby achieving current direction and magnitude control.
[0029] The first minimum current source module P_fix includes a first current source and a first switch S1. One end of the first current source is electrically connected to a power supply, and the other end of the first current source is electrically connected to one end of the first switch S1. The other end of the first switch S1 is electrically connected to a first branch switch of the first current mirror unit module P_source. The first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module P_source.
[0030] The second minimum current source module N_fix includes a second current source and a second switch S2. One end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2. The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module. The second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
[0031] A first low-pass filter circuit is connected between one end of the first reference current source and the first current mirror unit module, and a second low-pass filter circuit is connected between one end of the second reference current source and the second current mirror unit module.
[0032] Specifically, the first low-pass filter circuit includes a filter resistor Rp and a filter capacitor Cp, and the second low-pass filter circuit includes a filter resistor Rn and a filter capacitor Cn. Their function is to filter out high-frequency noise. A switch S9 is provided in parallel across the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel across the filter resistor of the second low-pass filter circuit. Switches S9 and S10 are fast-control switches. When closed in calibration mode, they short-circuit the resistors to quickly establish the voltage across resistors Rn and Rp, improving the circuit's response speed. S9 and S10 are complementary switches that can offset channel charge injection.
[0033] The output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4. One end of the current on-off switch S3 is connected to the first output terminal, and the other end of the current on-off switch S3 is connected to one end of the logic gate switch unit. One end of the current on-off switch S4 is connected to the second output terminal, and the other end of the current on-off switch S4 is connected to the other end of the logic gate switch unit. The logic gate switch unit includes gate switches S5, S6, S7, and S8 connected end to end. One end of the current on-off switch S3 is connected between gate switches S5 and S6, and one end of the current on-off switch S4 is connected between gate switches S7 and S8.
[0034] The direction of the current at the P and N terminals is changed to be controlled by the switch. <7> and its inverse signal code_b <7> By controlling the on and off of switches S5 to S8, the current direction of output ports P and N is controlled. <7> =0, S5 and S8 are turned on, S6 and S7 are turned off, the P terminal injects current, and the N terminal extracts current; code <7> =1, the direction of the output port current extraction and injection is opposite, as shown by the red arrow in the figure. For a certain output port, the extraction and injection of current are not performed at the same time.
[0035] The logic block diagram of the logic gate switch unit is shown in the attached Figure 3 As shown, when the highest code <7> = 0, p_code<6:0> = n_code<6:0> = code_b<6:0>; when code <7> =1,
[0036] p_code<6:0> = n_code<6:0> = code<6:0>. n_code<6:0> always equals p_code<6:0>, ensuring symmetry between the P and N output currents. For a node, the source current is negative, while the sink current is positive. Therefore, the Psource current is positive for the output node, and the Nsink current is negative for the output node.
[0037] When code = 127 = 0111 1111, n_code<6:0> = p_code<6:0> = code_b<6:0> = 0000000, and the output currents of Psource and Nsink are both 0. When code = 128 = 1000 0000, n_code<6:0> = p_code<6:0> = code_b<6:0> = 000 0000, so the output currents are not monotonic when code = 127 and code = 128. After adding the fix branch, the absolute values of the output currents of Psource and Nsink, Iout(code = 127) = I and Iout(code = 128) = 0, respectively, ensuring monotonicity.
[0038] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A small-area DC offset cancellation circuit, comprising a first reference current source and a first current mirror unit module connected thereto, and a second reference current source and a second current mirror unit module connected thereto, characterized in that: It also includes a first minimum current source module, a second minimum current source module, an output current on-off switch module and a logic gate switch unit; The first minimum current source module is connected in parallel with the first current mirror unit module to lead to a first output end, and the second minimum current source module is connected in parallel with the second current mirror unit module to lead to a second output end; the first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end; The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end.
2. The small-area DC offset cancellation circuit according to claim 1, wherein: The first minimum current source module includes a first current source and a first switch S1, one end of the first current source is electrically connected to the power supply, and the other end of the first current source is electrically connected to one end of the first switch S1; The other end of the first switch S1 is electrically connected to the first branch switch of the first current mirror unit module, and the first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module.
3. The small-area DC offset cancellation circuit according to claim 2, wherein: The second minimum current source module includes a second current source and a second switch S2, one end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2; The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module, and the second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
4. The small-area DC offset cancellation circuit according to claim 1, wherein: A first low-pass filter circuit is connected between one end of the first reference current source and the first current mirror unit module.
5. The small-area DC offset cancellation circuit according to claim 4, characterized in that: A second low-pass filter circuit is connected between one end of the second reference current source and the second current mirror unit module.
6. The small-area DC offset cancellation circuit according to claim 1, wherein: The output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4, one end of the current on-off switch S3 is connected to the first output end, and the other end of the current on-off switch S3 is connected to one end of the logic selection switch unit; one end of the current on-off switch S4 is connected to the second output end, and the other end of the current on-off switch S4 is connected to the other end of the logic selection switch unit.
7. The small-area DC offset cancellation circuit according to claim 6, wherein: The logic selection switch unit includes a selection switch S5, a selection switch S6, a selection switch S7 and a selection switch S8 connected end to end, one end of the current on-off switch S3 is connected between the selection switch S5 and the selection switch S6, and one end of the current on-off switch S4 is connected between the selection switch S7 and the selection switch S8.
8. The small-area DC offset cancellation circuit according to claim 5, wherein: A switch S9 is provided in parallel at both ends of the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel at both ends of the filter resistor of the second low-pass filter circuit.