Packaging structure for high-current SIDAC

Abstract

The utility model discloses a packaging structure used for a high current SIDAC. A surface mount device, structure, and associated methods. The device comprises: a housing; a lead frame at least partially encapsulated by the housing, the lead frame including a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface; and another lead frame at least partially encapsulated by the housing, the other lead frame coupled to a clip having one or more openings and coupled to the semiconductor chip. The semiconductor chip includes one or more protrusions extending from at least one of a top surface and a bottom surface of the semiconductor chip and positionable in at least one of: one or more recesses and one or more openings.

Description

Technical Field

[0001] The present disclosure relates generally to the field of power semiconductor discrete devices, and more particularly to a packaging structure for a high current SIDACtor device. Background Art

[0002] A discrete semiconductor is a device designed to perform a basic electronic function and cannot be broken down into individual functional components. Power semiconductors are used as switches or rectifiers in power electronics. Diodes, transistors, thyristors, and rectifiers are examples of discrete power semiconductors. Discrete power semiconductors are used in a wide range of environments, from very low-power systems to very high-power systems.

[0003] SIDACtor components (e.g., available from Littelfuse, Inc. in Chicago, Illinois, USA) can be used to protect against peak current pulses. SIDACtor components are solid-state crowbar devices designed to protect equipment located in harsh environments from overvoltage transient currents (up to 5000A surge current rating) within nanoseconds. However, SIDACTor chips typically include glass dots that protrude above the chip surface. This results in a larger void ratio for the SIDACTor chip during packaging. In addition, this reduces the surge capability of the final device to below an acceptable level, causing some devices to fail surge testing and reducing device yield.

[0004] Packaging an integrated circuit is typically the final stage of the semiconductor device manufacturing process. During packaging, the semiconductor die, representing the core of the semiconductor device, is enclosed in a housing that protects the die from physical damage and corrosion. For example, the semiconductor die is typically mounted on a copper substrate using solder paste, epoxy, or the like. The mounted semiconductor die is then typically encapsulated in a plastic or epoxy compound. However, existing packaging technologies used to package traditional SIDACTor devices do not provide components that can be used in high-reliability applications, such as, for example, but not limited to, automotive and aerospace applications. Utility Model Content

[0005] The following summary is provided to introduce some concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be an aid in determining the scope of the claimed subject matter.

[0006] In some embodiments, the present subject matter relates to a package structure (e.g., a surface mount device and / or package structure) for a high current SIDACTOR. The package structure may include a housing, a lead frame at least partially enclosed by the housing. The lead frame may include a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface. The package structure may include another lead frame at least partially enclosed by the housing. The other lead frame may be coupled to a clip having one or more openings and may be coupled to a semiconductor chip. The semiconductor chip may include one or more raised portions extending from at least one of a top surface and a bottom surface of the semiconductor chip and capable of being positioned in at least one of the following: one or more recesses and one or more openings.

[0007] In some implementations, the current subject matter can include one or more of the following optional features: A semiconductor chip can be configured to be coupled to a chip mounting pad.

[0008] In some embodiments, at least one of the one or more protrusions extending from the bottom surface of the semiconductor chip can be configured to be positionable in one or more recesses of the leadframe when coupling the semiconductor chip to the chip mounting pad.

[0009] In some embodiments, the clip may be completely enclosed by the housing.

[0010] In some embodiments, the semiconductor chip may include a semiconductor chip active region disposed on a top surface of the semiconductor chip.

[0011] In some embodiments, the clip can be configured to couple to an active area of ​​a semiconductor chip.

[0012] In some embodiments, when coupling the semiconductor chip to the clip, at least one of the one or more protrusions extending from the top surface of the semiconductor chip can be configured to be positionable in the one or more openings of the clip.

[0013] In some embodiments, the one or more raised portions may include one or more top raised portions extending from a top surface of the semiconductor chip and one or more bottom raised portions extending from a bottom surface of the semiconductor chip.

[0014] In some embodiments, the one or more top protrusions can be configured to be positionable in the one or more openings of the clip, and the one or more bottom protrusions can be configured to be positionable in the one or more recesses of the leadframe.

[0015] In some embodiments, the clip can be configured to include one or more support rods extending laterally across the clip.

[0016] In some embodiments, the clip may include a clip recess and one or more lead connection prongs. The clip recess may be positioned between the one or more lead connection prongs.

[0017] In some embodiments, the other lead frame may include one or more lead slots.

[0018] In some embodiments, one or more lead connection tines of the clip may be positioned in one or more lead slots when coupling the clip to another lead frame.

[0019] In some embodiments, the leadframe can include stress relief openings located proximate to the chip mounting surface.

[0020] In some embodiments, a lead frame can include a lead frame terminal end and another lead frame includes another lead frame terminal end.

[0021] In some embodiments, the lead frame terminal end and the other lead frame terminal end can be configured to be coupled to at least one of: a substrate, a printed circuit board, and any combination thereof.

[0022] In some embodiments, the housing may be made from at least one of: an epoxy, a plastic, and any combination thereof.

[0023] In some embodiments, the package structure may be a surface mount device.

[0024] In some embodiments, the semiconductor chip may be a SIDACTor device.

[0025] In some embodiments, the present subject matter relates to a method for manufacturing a surface mount device (and / or package structure). The method may include: providing a semiconductor chip having one or more raised portions extending from at least one of a top surface and a bottom surface of the semiconductor chip, a leadframe including a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface, a clip having one or more openings, and another leadframe; coupling the clip and the other leadframe; coupling the semiconductor chip to the leadframe and the clip, wherein the one or more raised portions are configured to be positioned in at least one of the following: the one or more recesses and the one or more openings; and forming a housing to enclose the leadframe, the other leadframe, the clip, and the semiconductor chip, wherein at least a portion of each of the leadframe and the other leadframe is configured to extend outside the housing.

[0026] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following summary is provided to introduce some concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be an aid in determining the scope of the claimed subject matter.

[0028] Figure 1A-1C shows an exemplary surface mount packaging structure according to some embodiments of the current subject matter;

[0029] Figure 2 shows the interior of a package structure according to some embodiments of the current subject matter;

[0030] Figures 3A-3D shows further details (in exploded view) of first and second leads of a package structure according to some embodiments of the current subject matter;

[0031] Figures 4A-4D shows further details (in exploded view) of a clip of a package structure according to some embodiments of the current subject matter;

[0032] Figure 5A-5B A chip showing a package structure according to some embodiments of the current subject matter; and

[0033] Figure 6 An example method for fabricating a semiconductor surface mount structure (eg, a package structure) according to some implementations of the current subject matter is shown.

[0034] The accompanying drawings are not necessarily drawn to scale. The accompanying drawings are merely representations and are not intended to depict specific parameters of the present disclosure. The accompanying drawings are intended to depict exemplary embodiments of the present subject matter and should not be considered limiting of its scope. In the accompanying drawings, like numbers represent like elements.

[0035] Furthermore, for clarity of illustration, some elements may be omitted and / or not shown to scale in some of the figures. Cross-sectional views may be in the form of "sliced" and / or "close-up" cross-sectional views, with some background lines visible in "true" cross-sectional views omitted for clarity of illustration. Furthermore, for clarity, some reference numerals may be omitted in some of the figures. DETAILED DESCRIPTION

[0036] Various methods according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate embodiments of systems and methods. A device, one or more systems, one or more components, and the like may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present subject matter to those skilled in the art.

[0037] To address these and potential other deficiencies of currently available solutions, one or more embodiments of the present subject matter are directed to methods, systems, articles of manufacture, etc., which, among other possible advantages, may provide systems and methods for manufacturing semiconductor devices, and in particular, systems and methods for manufacturing packaging structures for high current SIDACTor devices.

[0038] A voltage transient is defined as a short-duration surge of electrical energy and is the result of the sudden release of energy that was previously stored and / or induced by other means (such as, for example, heavy inductive loads, lightning, etc.). Voltage transients can be divided into predictable or repeatable transients and random transients. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions, or introduced randomly into the circuit from an external source. Repeatable transients are often caused by the operation of motors, generators, and / or the switching of reactive circuit components. Random transients, on the other hand, are typically caused by electrostatic discharge (ESD) and lightning, which are generally unpredictable.

[0039] ESD is characterized by very fast rise times and very high peak voltages and currents, likely the result of an imbalance of positive and negative charges between objects. Everyday activities can generate ESD that exceeds the vulnerability threshold of standard semiconductor technology. In the case of lightning, even though a direct lightning strike can be destructive, lightning-induced voltage transients are not the result of a direct lightning strike. When a lightning strike occurs, it can generate a magnetic field, which can in turn induce large voltage transients in nearby cables. For example, cloud-to-cloud lightning strikes can affect not only overhead cables but also buried cables. Even a lightning strike at a distance of 1 mile (1.6 km) can generate 70 volts in cables. The impact of voltage transient generation in cloud-to-ground lightning strikes is significantly greater.

[0040] Transient voltage suppressor (TVS) devices represent an important branch of power semiconductor devices that can be used to protect sensitive electronic devices from voltage transients (e.g., lightning and / or other transient voltage events). Currently, TVS device packages are typically characterized by small size and high power. Examples of TVS device packages include surface mount C-type (SMC) packages, which are used in many different technical fields, such as multi-point data transmission systems. Typically, multi-point data transmission systems require the use of asymmetric TVS devices, where the SMC package provides protection for electronic components in printed circuit boards from electrostatic discharge (ESD), electrical fast transients (EFT), lightning, etc.

[0041] SIDACtor components can be used to protect against peak current pulses. The SIDACTor component can be a solid-state crowbar device that can be designed to protect equipment located in harsh environments from overvoltage transient currents within nanoseconds. Although SIDACtor devices have the advantage of higher surge capability, they cannot fully clamp the voltage during operation. SIDACtor devices (e.g., available from Littelfuse, Inc. in Chicago, Illinois, USA) can be designed to suppress overvoltage transients in various electronic devices (e.g., telecommunications, data communications, etc.) and can divert currents of up to 5000A to ground within nanoseconds of reaching their breakdown voltage.

[0042] A typical SIDACtor chip may include one or more raised portions on its surface, such as glass dots, that extend above the chip surface. Such raised portions may be due to the manufacturing of the SIDACtor chip and / or for any other reason and may result in large void areas during mounting of the chip to the lead frame and / or other components within the package. Such void areas reduce the surface area of ​​the chip that can be mounted, thereby making the chip unstable, which may make it susceptible to failure during large current surges.

[0043] To address these issues, in some embodiments, the present subject matter may provide a package assembly that may include a leadframe having a SIDACtor chip support pad with one or more recessed areas. The recessed areas may be configured to accommodate the positioning of the SIDACtor chip's raised portions during soldering of the chip to the leadframe, clip, or the like. Once the SIDACtor chip's raised portions are positioned within the recessed areas of the chip support pad, the chip is more securely positioned within the package. In some exemplary, non-limiting embodiments, solder may be used to cover any remaining void areas. Furthermore, the clip may include one or more recessed areas, which may be connected to one of the leadframes of a semiconductor device. The recessed areas of the clip may be used to accommodate the positioning of any raised portions of the SIDACtor chip that may be located on the other side of the chip. Soldering may be used to fill any recessed areas where the chip's raised portions are unused and / or not fully filled. The clip may also include one or more groove features that may be used to dissipate heat and / or provide moisture release.

[0044] Figure 1A-Figure 1C An exemplary surface mount packaging structure 100 is shown in accordance with some embodiments of the current subject matter. Figure 1A A top perspective view of package structure 100 is shown. Figure 1B A side cross-sectional view of the package structure 100 is shown. Figure 1C A top cross-sectional view of the package structure 100 is shown.

[0045] The package structure 100 may include an encapsulation or housing 102 (hereinafter referred to as a "housing"), a semiconductor and / or SIDACtor chip 104, a clip 106, a first lead 108, a second lead 110, and a chip support or mounting (terms used interchangeably herein) pad 112 (which may be disposed on the second lead 100, as will be discussed below).

[0046] Housing 102 can be configured to house and / or encapsulate chip 104, clip 106, and at least a portion of first and second leads 108, 110, including chip support pad 112. First and second leads 108, 110 can be configured to extend from housing 102 to be conductively coupled to other electronic components and / or one or more printed circuit boards. Housing 102 can be configured to be made of epoxy, plastic, and / or any other suitable material.

[0047] The first lead 108 may include a first end 114 of the first lead and a second end 116 of the first lead. The first end 114 of the first lead may be coupled to a substrate and / or printed circuit board (PCB) 128 and / or any other electronic component using any known mechanism (e.g., soldering, welding, etc.). The second end 116 of the first lead may be coupled to the clip 106 using conductive solder 118. In particular, the second end 116 of the first lead may be coupled to the first end 120 of the clip 106. Although Figure 1A-1C The first lead 108 is shown as having a curved shape, but it will be appreciated that the first lead 108 may have any desired shape and / or its shape may be varied to accommodate various circuit configurations and / or positioning.

[0048] The second lead 110 may include a first end 124 of the second lead and a second end 126 of the second lead. The first end 124 of the second lead may be coupled to the PCB 128 and / or any other electronic component using any known mechanism (e.g., soldering, welding, etc.). The second end 126 of the second lead may include a chip support pad 112, which may be disposed (e.g., soldered, welded, molded, etc.) proximate the second end 126 of the second lead. The chip support pad 112 may be coupled to the chip 104 using conductive solder 130. Similarly, although Figure 1A-1C The second lead 110 is shown as having a curved shape, but it will be appreciated that the second lead 110 may have any desired shape and / or its shape may be varied to accommodate various circuit configurations and / or positioning.

[0049] In some embodiments, the first lead 108 and the second lead 110 can be made of a conductive material, such as, for example but not limited to, copper, a copper alloy, silver, a metal alloy, etc., and / or any combination thereof. The leads 108, 110 can also be configured to provide an electrical connection between the SIDACtor chip 104 and a circuit (e.g., PCB 128) to which the package structure 100 can be connected.

[0050] Furthermore, in some example embodiments, the first lead 108 and / or the second lead 110 may include various structural features (as discussed in further detail below) that may be configured to facilitate the manufacturing and use of the structure 100. In particular, such structural features may accommodate positioning of the chip 104 and its various protrusions, reduce and / or prevent stress damage to the chip 104 during use, dissipate heat, reduce moisture, and the like. For example, the second lead 110 and the clip 106 may include one or more recessed features ( Figure 1A-1C ), which may improve the positioning of the chip 104 .

[0051] In some example, non-limiting embodiments, the first lead 108 can be configured as a cathode and the second lead 110 can be configured as an anode, or vice versa. It will be appreciated that any other embodiments of the leads 108 and 110 are possible.

[0052] like Figure 1A-1C As shown, chip 104 can be coupled to clip 106. The coupling of chip 104 and clip 106 can occur within housing 102. Furthermore, a top working surface of chip 104 can be configured to be conductively coupled to second end 122 of the clip using conductive solder 132. Furthermore, a bottom working surface of chip 104 can be configured to be conductively coupled to chip support pad 112 using conductive solder 130.

[0053] In some embodiments, clip 106 can be made of a conductive material, such as, for example, but not limited to, copper, a copper alloy, silver, a metal alloy, and / or any combination thereof. Clip 106 can be configured to provide an electrical path between PCB 128, chip 104, and first and second leads 108 and 110. Clip 106 can be configured to have a curved shape, with a portion thereof configured to extend away from first lead 108 and chip 104.

[0054] Clip 106 can be configured to absorb more solder during the assembly process of structure 100 and can further improve the reliability of structure 100 during operation. In addition, clip 106 can include various structural features (e.g., recessed features of the clip, as discussed in further detail below) that can be configured to encapsulate chip 104.

[0055] like Figure 1A-1C As shown, the housing 102 can have a generally parallelepiped shape. It will be appreciated that it can have any other desired shape.

[0056] Figure 2 1 shows the interior of a package structure 100 according to some embodiments of the current subject matter. In particular, Figure 2 Further details of the first lead 108, the second lead 110, the clip 106, and the chip 104 are shown. Figure 2 As shown, the chip 104 can be positioned between the second lead 110 and the clip 106. In particular, the chip 104 can be positioned on top of the second lead 110 and below the clip 106. The second lead 110 can include a flat panel 208, and the chip 104 can be positioned on top of the flat panel 208 and soldered using a conductive solder 130 (e.g., Figure 1B The surface area of ​​the flat panel 208 may be larger than the surface area of ​​the chip 104 .

[0057] The clip 106 may include a flat panel 202 that may be disposed proximate the second end 122 of the clip. The flat panel 202 of the clip 106 may be positioned on top of the working surface 210 of the chip 104 and soldered to the chip 104 using the conductive solder 132. The flat panel 202 may be configured to extend at least partially above the top working surface 210 of the chip. Figure 2 As shown, the surface area of ​​the flat panel 202 of the clip 106 can be smaller than the surface area of ​​the top working panel 210 of the chip. The first end 120 of the clip can be configured to be coupled to the second end 116 of the first lead. Figure 1B As shown, conductive solder 118 may be used to couple the first end 120 of the clip and the second end 116 of the first lead.

[0058] In some example, non-limiting embodiments, the clip 106 may optionally include a clamping bar 206 that may be used to provide stress relief and / or damage protection to the clip 106 and / or the chip 104 and / or any other components of the package structure 100. The clamping bar 206 may be disposed between the flat panel 202 of the clip 106 and the first end 120 of the clip.

[0059] In some embodiments, the flat panel 202 of the clip 106 may include one or more clip openings 204a, 204b, 204c, and 204d. Figure 2 As shown, the flat panel 202 may include four openings 204 (a, b, c, d). As can be appreciated, the flat panel 202 may include any number of openings 204. The openings 204 may be configured to accommodate the positioning of corresponding protrusions 216 disposed on and extending from the surface of the chip's top working panel 210. For example, the opening 204a of the clip may be configured to accommodate the positioning of the protrusion 212a of the chip 104; the opening 204b of the clip may be configured to accommodate the positioning of the protrusion 212b of the chip 104; the opening 204c of the clip may be configured to accommodate the positioning of the protrusion 212c of the chip 104; and the opening 204d of the clip may be configured to accommodate the positioning of the protrusion 212d of the chip 104. The use of openings 204 may be configured to allow for closer positioning and coupling of the clip 106 and the chip 104. As described herein, the conductive solder 132 may be used to couple the clip 106 and the chip 104 , wherein the conductive solder 132 may fill any gaps between the clip 106 and the chip 104 , which may remain when the protrusions 214 are positioned into the corresponding openings 204 due to the clip 106 being placed on top of the chip 104 .

[0060] Figures 3A-3D1 shows further details (in exploded view) of first and second leads 108, 110 of package structure 100 according to some embodiments of the current subject matter. Figure 3A A top perspective view of the leads 108, 110 is shown; Figure 3B A top view of the leads 108, 110 is shown; Figure 3C A side view showing leads 108, 110; and Figure 3D A top perspective view of the first lead 108 is shown.

[0061] like Figures 3A-3D As shown, the first lead 108 can have a curved shape. As can be appreciated, the first lead 108 can have any desired shape and / or its shape can be changed to accommodate various circuit configurations and / or positioning. The first lead 108 can include one or more lead slots 306a and 306b, which can be positioned proximate the second end 116 of the first lead 108. The lead slot 306 can be configured to accommodate the positioning of the clip 106, for example, as shown in FIG. Figure 1A-1C Conductive solder 118 (such as Figure 1B ) to secure the first lead 108 and the clip 106 together.

[0062] In some example, non-limiting embodiments, first lead 108 may include one or more lead channels 310. Lead channels 310 may be configured to extend through first lead 108 and provide heat and / or moisture release during manufacture and / or use of package structure 100.

[0063] In some embodiments, similar to the first lead 108, the second lead 110 can have a curved shape. As can be appreciated, the second lead 110 can have any desired shape and / or its shape can be changed to accommodate various circuit configurations and / or positioning. In addition, the second lead 110, and in particular the flat face 208 thereof, can include a work face 308. The work face 308 can be configured to position the chip 104 ( Figure 3A (not shown) positioned and coupled to the second lead 110. The working panel 308 may include one or more recesses 302a, 302b, 302c, 302d. Figure 3A As shown, the working panel 308 may include four recesses 302 (a, b, c, d). As can be appreciated, the working panel 308 may include any number of recesses 302. The recesses 302 may be configured to accommodate the positioning of corresponding protrusions disposed on the surface of the chip 104 and extending from a surface of the chip 104 that may be opposite to a surface of the chip's top working panel 210 (e.g., FIG. 1 ). Figure 5A-5B). The recess 302 can be configured to have sufficient depth to accommodate the positioning of such a protrusion.

[0064] Similar to the openings 204, the use of the recesses 302 can be configured to allow for closer positioning and coupling of the second lead 110, particularly the flat face plate 208 thereof, and the chip 104. As described herein, the conductive solder 130 can be used to couple the flat face plate 208 of the second lead 110 and the chip 104, wherein the conductive solder 130 can fill any gaps between the flat face plate 208 and the chip 104, which may remain when the protrusions of the chip are positioned into the corresponding recesses 302 due to the chip 104 being placed on top of the flat face plate 208 of the second lead 110.

[0065] In some example, non-limiting embodiments, the second lead 110 may optionally include a lead opening 304. The lead opening 304 may be disposed proximate to the flat panel 208. The lead opening 304 may be disposed outside of where the chip 104 may be disposed (i.e., on top of the flat panel 208 of the second lead 110). The lead opening 304 may be configured to provide some stress relief on the package structure 100, dissipation of heat and / or moisture, etc., and to reduce chip cracking, breakage, etc. during manufacturing and / or use (such as, for example, by providing more flexibility and heat dissipation capabilities to the package structure 100).

[0066] Figures 4A-4D 1 shows further details (in exploded view) of the clip 106 of the package structure 100 according to some embodiments of the current subject matter. Figure 4A A top perspective view of the clip 106 is shown; Figure 4B A side view of the clip 106 is shown; Figure 4C A bottom perspective view of the clip 106 is shown; and Figure 4D A rear view of the clip 106 is shown.

[0067] In some embodiments, the clip 106 can be made of a conductive material, such as, for example, but not limited to, copper, a copper alloy, silver, a metal alloy, and / or any combination thereof. The clip 106 can be configured to provide an electrical path between the PCB 128, the chip 104, and the first and second leads 108 and 110. The clip 106 can be configured to have a curved shape, with a portion thereof configured to extend away from the first lead 108 and the chip 104. The clip 106 can include various structural features (e.g., a heat dissipation panel and clip support tooling as discussed herein) that can be configured to improve and accelerate heat dissipation during operation.

[0068] As discussed herein, the clip 106 may include one or more clip openings 204a, 204b, 204c, and / or 204d, which may be configured to accommodate the raised portions 212a, 212b, 212c, and 212d, respectively, of the chip 104. Figures 4A-4D The opening 204 may be positioned in the flat panel 202 of the clip 106, which may be coupled to the chip 104. The opening 204 may allow the raised portion 214 to be at least partially raised when the clip 106 and the chip 104 are coupled.

[0069] At the first end 120 of the clip, the clip 106 may also include one or more lead connection prongs 402a, 402b and a clip recess 404. Figure 4C and Figure 4D As shown, the clip recess 404 can be disposed between the lead connection prong 402a and the lead connection prong 402b. The clip recess 404 can be configured to accommodate the positioning of the lead clip connector 406 of the first lead 108. Figure 4C As shown, the clip 106 can be positioned on top of the first lead 108 by placing the lead connection prongs 402a, 402b in the lead slots 306a, 306b, respectively, wherein the lead clip connector 406 is positioned between the lead connection prongs 402a, 402b and positioned in the clip recess 404. The conductive solder 118 ( Figures 4A-4D ) may be used to secure the lead clip connector 406 in the clip recess 404 .

[0070] The clip 106 may include a clamping bar 206, which may function as a stress protection / relief bar and may be configured to extend laterally through the body of the clip 106. The clamping bar 206 may have any desired length, which may be selected based on the manufacturing, use, and / or any other requirements of the package structure 100. The clamping bar 206 may be used to reduce and / or alleviate stresses that the package structure 100 and / or its chip 104 may experience during manufacturing, use, and / or operation.

[0071] The flat panel 202 of the clip may have a substantially rectangular shape (eg, a square), the dimensions of which may be selected to accommodate the chip 104 ( Figures 4A-4D100 ). For example, the length and width of the flat panel 202 can be selected to be less than the length of the clamping rod 206, but greater than the length and / or width dimension(s) of the chip 104. The number, location(s) and / or dimensions(s) of the openings 204 can likewise be selected based on the specific requirements of the package structure 100. Furthermore, the openings 204 can have any desired shape (e.g., circular, rectangular, square, polygonal, etc.). Furthermore, the shape, size, dimensions, etc. of the lead connection tines 402a, 402b and / or the clip recesses 404 can also be selected based on the specific requirements of the package structure 100. As can be appreciated, any desired shape, size, dimensions, etc. of the various components of the package structure 100 can be used.

[0072] Figure 5A-5B FIG. 1 shows a chip 104 of a package structure 100 according to some embodiments of the current subject matter. Specifically, Figure 5A A top perspective view of chip 104 is shown, and Figure 5B A bottom perspective view of chip 104 is shown.

[0073] like Figure 5A-5B As shown, the chip 104 may include a top working panel 210 of the chip, a bottom working panel 502 of the chip, a top edge 504 of the chip, a bottom edge 506 of the chip, a top middle portion 510 of the chip, and a bottom middle portion 512 of the chip. The top middle portion 510 of the chip may be surrounded by the top edge 504 of the chip. The bottom middle portion 512 of the chip may be surrounded by the bottom edge 506 of the chip. The top edge 504 of the chip and the bottom edge 506 of the chip may serve as a guard ring for the chip and may be coupled to the corresponding top middle portion 510 of the chip and the bottom middle portion 512 of the chip (e.g., using soldering, welding, etc., and / or manufactured as an entire chip).

[0074] like Figure 5A As shown, the top working panel 210 of the chip may include a top middle portion 510 of the chip and a top edge 504 of the chip. The top working panel 210 of the chip may be used to position and / or couple various electronic components associated with the chip 104.

[0075] The top middle portion 510 of the chip may include one or more raised portions 212a, 212b, 212c, 212d. The raised portion 212 may be configured to be raised away from the surface of the top middle portion 510 of the chip. Figure 5AAs shown, the raised portion 212 can have a circular shape. As can be appreciated, the raised portion 212 can have any desired shape and / or height and / or any other dimensions. In addition, any number of raised portions can be used. The raised portions 212 can be configured to be positioned within the openings 204a, 204b, 204c, and 204d of the clip, respectively. In some example, non-limiting embodiments, the raised portions 212 can be configured to provide a more secure coupling between the chip 104 and the clip 106 by fitting the raised portions 212 within the corresponding openings 204.

[0076] refer to Figure 5B The bottom working panel 502 of the chip may include a bottom middle portion 512 of the chip and a bottom edge 506 of the chip. The bottom working panel 502 of the chip may also be used to position and / or couple various electronic components associated with the chip 104.

[0077] The bottom middle portion 512 of the chip may include one or more raised portions 508a, 508b, 508c, 508d. Raised portions 508 may be configured to be raised away from the surface of the bottom middle portion 512 of the chip. Similar to raised portions 212, raised portions 508 may have a circular shape. As can be appreciated, raised portions 508 may have any desired shape and / or height and / or any other dimensions. Furthermore, although Figure 5B Four protrusions 508 are shown, but any number of protrusions may be used. The protrusions 508 can be configured to be positioned within the recesses 302a, 302b, 302c, and 302d of the second lead 110, respectively. In some exemplary, non-limiting embodiments, the protrusions 508 can be configured to provide a more secure coupling between the chip 104 and the second lead 110 by positioning the protrusions 508 within the corresponding recesses 302. The top working panel 210 of the chip can be used to position and / or couple various electronic components associated with the chip 104.

[0078] like Figure 5A-5B As shown, chip 104 can be used in various electronic applications, such as, for example, multi-point data transmission devices, systems, telecommunications, data communications equipment, etc., wherein chip 104 can be configured to provide protection from peak current pulses. In some example, non-limiting embodiments, chip 104 can be a SIDACtor protection thyristor (e.g., available from Littelfuse, Inc. of Chicago, Illinois, USA) and can be used to suppress overvoltage transients in various electronic devices and can divert up to 5000A of current to ground within nanoseconds of reaching its breakdown voltage.

[0079] In addition, the chip 104 can be packaged using a surface mount (e.g., SMC) package (as discussed herein), which provides high power while having an overall small size. For example, the SMC package can be used for a printed circuit board (PCB) to protect various electronic components from ESD, electrical fast transients (EFT), lightning, and / or any other transients. The SMC package allows for surface mounting of electronic components and optimization of space on the PCB (where these components can be mounted). It can be further characterized by having a small profile, improved clamping capability, and other enhanced features.

[0080] As can be appreciated, the present subject matter is not limited to SIDACtor chips. For example, chip 104 can be a thyristor, a TVS semiconductor device, and / or any other type of chip. Chip 104 can be any device that can be used to protect against voltage transients that are harmful to the operation of various electronic components.

[0081] Figure 6 An example method 600 for fabricating a semiconductor surface mount structure (eg, package structure 100) is shown according to some embodiments of the current subject matter. Method 600 may be used to fabricate Figures 1A-5B The package structure 100 is shown.

[0082] At 602, a semiconductor chip (e.g., chip 104) may be provided having one or more protrusions (e.g., protrusions 212, 508) extending from at least one of the top and bottom surfaces of the semiconductor chip (e.g., top working surface 210 of the chip, bottom working surface 502 of the chip). Furthermore, a lead frame (e.g., first lead 108) may also be provided, including a chip mounting surface (e.g., working surface 308) having a chip mounting pad (e.g., chip support pad 112) and one or more recesses (e.g., recess 302) disposed on the chip mounting surface, a clip (e.g., clip 106) having one or more openings (e.g., clip opening 204), and another lead frame (e.g., second lead 110).

[0083] At 604 , a clip may be coupled to the leadframe (eg, the second lead 110 ).

[0084] At 606, the semiconductor chip can be coupled to a lead frame (e.g., first lead 108) and a clip (e.g., clip 106). One or more protrusions (e.g., protrusion 212) can be configured to be positioned in at least one of: one or more recesses (e.g., recess 302) and one or more openings (e.g., opening 204 of the clip).

[0085] At 608, a housing (eg, housing 102) can be formed to enclose the leadframe, the other leadframe, the clip, and the semiconductor chip. At least a portion of each leadframe can be configured to extend outside the housing.

[0086] The components and features of the above-described devices may be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single-chip architectures. Furthermore, where appropriate, features of the devices may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination thereof. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry."

[0087] It should be understood that the exemplary devices shown in the above block diagrams can represent one functional description example of many potential implementations. Therefore, the division, omission, or inclusion of block functions described in the drawings does not necessarily mean that the hardware components, circuits, software, and / or elements used to implement these functions will necessarily be divided, omitted, or included in the embodiments.

[0088] Some embodiments may be described using the expression "one embodiment" or "an embodiment," "one implementation," or "some implementations," and their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in one embodiment" (or its derivatives) appearing in different places in the specification do not necessarily all refer to the same embodiment. In addition, unless otherwise noted, the above-mentioned features are considered to be applicable to be used together in any combination. Therefore, any features discussed separately can be used in combination with each other unless it is noted that the features are incompatible with each other.

[0089] It is emphasized that the Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as the following claims reflect, the subject matter of the invention lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein," respectively. Furthermore, the terms "first," "second," "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects. Moreover, the use of "including," "comprising," or "having" and variations thereof herein are meant to encompass the items listed below and their equivalents as well as additional items. Thus, the terms "including," "comprising," or "having," and variations thereof, are open-ended expressions and may be used interchangeably herein.

[0090] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "side," "lateral," "radial," "inner," "outer," "left," and "right" may be used herein to describe the relative position and orientation of features and components, each relative to the geometry and orientation of other features and components as they appear in the perspective, exploded perspective, and cross-sectional views provided herein. The terminology is not intended to be limiting and includes the words specifically mentioned, derivatives thereof, and words of similar meaning.

[0091] The foregoing includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and / or methodologies, but one skilled in the art will recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0092] In one aspect, a device may include a housing; a lead frame at least partially enclosed by the housing, the lead frame including a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface; and another lead frame at least partially enclosed by the housing, the other lead frame coupled to a clip having one or more openings and coupled to a semiconductor chip; wherein the semiconductor chip includes one or more protrusions extending from at least one of a top surface and a bottom surface of the semiconductor chip and capable of being positioned in at least one of: the one or more recesses and the one or more openings.

[0093] The apparatus may include where the semiconductor chip is configured to be coupled to a chip mounting pad.

[0094] The apparatus may include wherein at least one of the one or more protrusions extending from a bottom surface of the semiconductor chip is configured to be positionable in one or more recesses of the lead frame when coupling the semiconductor chip to the chip mounting pad.

[0095] The device may include wherein the clip is fully enclosed by the housing.

[0096] The apparatus may include where the semiconductor chip includes a semiconductor chip active region disposed on a top surface of the semiconductor chip.

[0097] The apparatus may include where the clip is configured to couple to an active area of ​​the semiconductor chip.

[0098] The apparatus may include where, when coupling the semiconductor chip to the clip, at least one of the one or more protrusions extending from the top surface of the semiconductor chip is configured to be positionable in the one or more openings of the clip.

[0099] The apparatus may include where the one or more bumps include one or more top bumps extending from a top surface of the semiconductor chip and one or more bottom bumps extending from a bottom surface of the semiconductor chip.

[0100] The apparatus may include where the one or more top protrusions are configured to be positionable in the one or more openings of the clip, and the one or more bottom protrusions are configured to be positionable in the one or more recesses of the lead frame.

[0101] The apparatus may include wherein the clip is configured to include one or more support rods extending transversely through the clip.

[0102] The apparatus may include wherein the clip includes a clip recess and one or more lead connection prongs, the clip recess being positioned between the one or more lead connection prongs.

[0103] The apparatus may include wherein the other lead frame includes one or more lead slots.

[0104] The apparatus may include wherein, upon coupling the clip to another lead frame, one or more lead connection tines of the clip are positioned in one or more lead slots.

[0105] The apparatus may include wherein the leadframe includes a stress relief opening positioned proximate the chip mounting surface.

[0106] The apparatus can include where the lead frame includes a lead frame terminal end and the other lead frame includes another lead frame terminal end.

[0107] The apparatus can include where the lead frame terminal end and the other lead frame terminal end are configured to couple to at least one of: a substrate, a printed circuit board, and any combination thereof.

[0108] The device can include wherein the housing is made from at least one of: an epoxy, a plastic, and any combination thereof.

[0109] The device may include wherein the device is configured as a surface mount device.

[0110] The apparatus may include a SIDACtor device.

[0111] In one aspect, a method may include providing a semiconductor chip having one or more raised portions extending from at least one of a top surface and a bottom surface of the semiconductor chip, a lead frame comprising a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface, a clip having one or more openings, and another lead frame; coupling the clip and the other lead frame; coupling the semiconductor chip to the lead frame and the clip, wherein the one or more raised portions are configured to be positionable in at least one of: the one or more recesses and the one or more openings; forming a housing to enclose the lead frame, the other lead frame, the clip, and the semiconductor chip, wherein at least a portion of each of the lead frame and the other lead frame is configured to extend outside the housing.

[0112] The foregoing description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but by the appended claims. Future applications claiming priority to the present application may claim the disclosed subject matter in different ways and may generally include any combination of one or more limitations variously disclosed or otherwise illustrated herein.

[0113] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to assist the reader in understanding the present disclosure and are not intended to be limiting, particularly with respect to the position, orientation, or use of the present disclosure. Unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) are to be interpreted broadly and may include intermediate members between a collection of elements and relative movement between elements. Thus, connection references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

[0114] Furthermore, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but rather to distinguish one feature from another. The drawings are for illustration purposes only, and the dimensions, positions, order, and relative sizes reflected in the accompanying drawings may vary.

[0115] The scope of the present disclosure is not limited by the specific embodiments described herein. In fact, in addition to those described herein, various other embodiments and modifications of the present disclosure will be apparent to those of ordinary skill in the art based on the foregoing description and drawings. Therefore, such other embodiments and modifications are intended to fall within the scope of the present disclosure. In addition, the present disclosure is described herein in the context of specific embodiments in specific environments for specific purposes. Those of ordinary skill in the art will recognize that usefulness is not limited thereto, and that the present disclosure can be beneficially implemented in any number of environments for any number of purposes. Therefore, the claims set forth below will be interpreted in light of the full breadth and spirit of the present disclosure as described herein.

Claims

1. A packaging structure for a high current SIDACtor, characterized in that: The packaging structure includes: shell; a lead frame at least partially enclosed by the housing, the lead frame comprising a chip mounting surface having a chip mounting pad and one or more recesses disposed on the chip mounting surface; and another lead frame at least partially enclosed by the housing, the other lead frame coupled to a clip having one or more openings and coupled to a semiconductor chip; The semiconductor chip includes one or more protrusions extending from at least one of a top surface and a bottom surface of the semiconductor chip and capable of being positioned in at least one of: the one or more recesses and the one or more openings.

2. The packaging structure according to claim 1, wherein: The semiconductor chip is configured to be coupled to the chip mounting pad.

3. The packaging structure according to claim 2, wherein: At least one of the one or more protrusions extending from the bottom surface of the semiconductor chip is configured to be positionable in one or more recesses of the lead frame when coupling the semiconductor chip to the chip mounting pad.

4. The packaging structure according to claim 1, wherein: The clip is completely enclosed by the housing.

5. The packaging structure according to claim 4, wherein: The semiconductor chip includes a semiconductor chip active region disposed on a top surface of the semiconductor chip.

6. The packaging structure according to claim 5, wherein: The clip is configured to be coupled to the semiconductor chip active area.

7. The packaging structure according to claim 6, wherein: When the semiconductor chip is coupled to the clip, at least one of the one or more raised portions extending from the top surface of the semiconductor chip is configured to be positionable in one or more openings of the clip.

8. The packaging structure according to claim 1, wherein: The one or more bumps include one or more top bumps extending from a top surface of the semiconductor chip and one or more bottom bumps extending from a bottom surface of the semiconductor chip.

9. The packaging structure according to claim 8, wherein: The one or more top protrusions are configured to be positionable in the one or more openings of the clip, and the one or more bottom protrusions are configured to be positionable in the one or more recesses of the lead frame.

10. The packaging structure according to claim 1, wherein: The clip is configured to include one or more support rods extending transversely through the clip.

11. The packaging structure according to claim 1, wherein: The clip includes a clip recess and one or more lead connection prongs, the clip recess being positioned between the one or more lead connection prongs.

12. The packaging structure according to claim 11, wherein: The other lead frame includes one or more lead slots.

13. The packaging structure according to claim 12, wherein: When the clip is coupled to the other lead frame, the one or more lead connection prongs of the clip are positioned in the one or more lead slots.

14. The packaging structure according to claim 1, wherein: The lead frame includes a stress relief opening positioned proximate the chip mounting surface.

15. The packaging structure according to claim 1, wherein: The lead frame includes a lead frame terminal end, and the other lead frame includes another lead frame terminal end.

16. The packaging structure according to claim 15, wherein: The lead frame terminal end and the another lead frame terminal end are configured to be coupled to at least one of: a substrate, a printed circuit board, and any combination thereof.

17. The packaging structure according to claim 1, wherein: The housing is made of at least one of: epoxy, plastic, and any combination thereof.

18. The packaging structure according to claim 1, wherein: The packaging structure is a surface mounted device.

19. The packaging structure according to claim 1, wherein: The semiconductor chip is a SIDACTor device.

Images