Transient voltage suppressor and security POE port circuit board

Abstract

The embodiment of the utility model discloses a transient voltage suppressor and a security POE port circuit board. The transient voltage suppressor comprises a first transient voltage suppressor chip, a second transient voltage suppressor chip, a third transient voltage suppressor chip, a fourth transient voltage suppressor chip, a fifth transient voltage suppressor chip, a first copper electrode, a second copper electrode, a third copper electrode, a fourth copper electrode, a first pin, a second pin and a third pin. The first transient suppression diode chip is arranged between the first copper electrode and the second copper electrode; the second transient voltage suppressor chip and the third transient voltage suppressor chip are arranged in a stacked mode and located between the second copper electrode and the third copper electrode. The fourth transient voltage suppressor chip and the fifth transient voltage suppressor chip are arranged in a stacked mode and located between the second copper electrode and the fourth copper electrode. According to the utility model, the packaging cost can be directly reduced, and the device integration is improved.

Description

Technical Field

[0001] The embodiments of the utility model relate to the field of semiconductor packaging technology, and in particular to a transient voltage suppressor and a security POE port circuit board. Background Art

[0002] In network equipment, POE (Power over Ethernet) ports are a key technology, enabling the transmission of both power and data over a single network connection, providing a continuous and stable power supply for devices. Currently, demand for security POE ports is the most influential and in-demand product on the market. Conventional single-chip packaged products are no longer considered competitive. Common security products on the market use multiple single-chip products connected in parallel, increasing costs. Furthermore, the large board layout area hinders technological advancement, hindering the long-term development of POE port protection.

[0003] Figure 1 This is a schematic diagram of a security POE port circuit board in the prior art. Figure 1 Three transient voltage suppressor (TVS) diodes are connected in parallel at the POE port in the circuit, with one device corresponding to each of the three lines. The disadvantages of using three TVS diodes in parallel are: the need for three independent TVS diodes is high in cost; and the three devices occupy three pads on the PCB, which increases the board area and affects the overall circuit integration. Utility Model Content

[0004] The utility model provides a transient voltage suppressor and a security POE port circuit board, which can directly reduce packaging costs and improve device integration.

[0005] According to one aspect of the present invention, a transient voltage suppressor is provided, comprising: a first transient voltage suppressor diode chip, a second transient voltage suppressor diode chip, a third transient voltage suppressor diode chip, a fourth transient voltage suppressor diode chip, a fifth transient voltage suppressor diode chip, a first copper electrode, a second copper electrode, a third copper electrode, a fourth copper electrode, a first pin, a second pin, and a third pin;

[0006] The first transient suppression diode chip is arranged between the first copper electrode and the second copper electrode, and the first pin is connected to the first copper electrode and the second copper electrode;

[0007] The second TVS diode chip and the third TVS diode chip are stacked and located between the second copper electrode and the third copper electrode, and the second pin is connected to the third copper electrode;

[0008] The fourth transient voltage suppressor diode chip and the fifth transient voltage suppressor diode chip are stacked and located between the second copper electrode and the fourth copper electrode, and the third pin is connected to the fourth copper electrode.

[0009] Optionally, the transient voltage suppressor further includes solder or conductive glue, wherein the solder or the conductive glue is used to connect the first transient voltage suppressor diode chip, the first copper electrode and the second copper electrode, to connect the second transient voltage suppressor diode chip and the second copper electrode, to connect the third transient voltage suppressor diode chip and the third copper electrode, to connect the fourth transient voltage suppressor diode chip and the second copper electrode, and to connect the fifth transient voltage suppressor diode chip and the fourth copper electrode.

[0010] Optionally, the first pin, the second pin and the third pin form a Y-shaped structure in combination.

[0011] Optionally, the protection voltages of the first pin, the second pin, and the third pin are all 50V-60V.

[0012] Optionally, the first pin, the second pin and the third pin are used to withstand a lightning pulse with an open-circuit voltage wave of 10 / 700 μS and a voltage greater than 4 kV.

[0013] Optionally, the second transient suppression diode chip is connected in series with the third transient suppression diode chip, and the fourth transient suppression diode chip is connected in series with the fifth transient suppression diode chip;

[0014] The second TVS diode chip and the third TVS diode chip connected in series are connected in parallel with the fourth TVS diode chip and the fifth TVS diode chip connected in series.

[0015] Optionally, the second TVS diode chip and the third TVS diode chip connected in series are connected in series with the first TVS diode chip;

[0016] The fourth TVS diode chip and the fifth TVS diode chip connected in series are connected in series with the first TVS diode chip.

[0017] Optionally, the second pin and the third copper electrode are integrally formed, and the third pin and the fourth copper electrode are integrally formed.

[0018] Optionally, the second TVS diode chip is of the same model as the third TVS diode chip, the fourth TVS diode chip, and the fifth TVS diode chip.

[0019] According to another aspect of the present invention, a security POE port circuit board is provided, and the security POE port circuit board includes the transient voltage suppressor described in any one of the above aspects.

[0020] The technical solution of the embodiment of the present utility model is to simplify the device size, improve the integration of the transient suppressor, reduce the board area occupied by the protective devices, and improve the circuit integration by simplifying the three transient suppression diodes connected in parallel to one transient voltage suppressor connected in parallel to the circuit. The use of one transient voltage suppressor can replace and surpass the lightning protection capability of the three transient suppression diodes in the original solution, improve the protection capability of the transient voltage suppressor, increase the protection capability of the POE port, and directly reduce the packaging cost and improve the device integration compared with the existing solution. In summary, the present utility model solves the problem that the existing technology needs to use three independent TVS, which is costly; the three devices need to occupy three pads on the PCB board, which occupies a large board area and affects the overall circuit integration.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is an overall schematic diagram of a security POE port circuit board in the prior art;

[0024] Figure 2 1 is a schematic structural diagram of a transient voltage suppressor provided according to an embodiment of the present utility model;

[0025] Figure 3 1 is a structural diagram of another transient voltage suppressor provided according to an embodiment of the present utility model;

[0026] Figure 4 1 is a schematic diagram of an open-circuit voltage waveform of a transient voltage suppressor provided according to an embodiment of the present utility model;

[0027] Figure 5 This is a schematic diagram of a packaged transient voltage suppressor provided according to an embodiment of the present utility model;

[0028] Figure 61 is a front view of a transient voltage suppressor provided according to an embodiment of the present utility model;

[0029] Figure 7 is a side view of a transient voltage suppressor provided according to an embodiment of the utility model;

[0030] Figure 8 is a side view of another transient voltage suppressor provided according to an embodiment of the utility model;

[0031] Figure 9 The figure is an overall schematic diagram of a security POE port circuit board provided according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0032] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Figure 2 1 is a schematic structural diagram of a transient voltage suppressor provided according to an embodiment of the present utility model. Figure 3 This is a schematic diagram of the structure of another transient voltage suppressor provided according to an embodiment of the present invention, with reference to Figure 2 and Figure 3An embodiment of the utility model provides a transient voltage suppressor, which includes: a first transient voltage suppressor diode chip 1, a second transient voltage suppressor diode chip 2, a third transient voltage suppressor diode chip 3, a fourth transient voltage suppressor diode chip 4, a fifth transient voltage suppressor diode chip 5, a first copper electrode 11, a second copper electrode 12, a third copper electrode 13, a fourth copper electrode 14, a first pin 21, a second pin 22, and a third pin 23; the first transient voltage suppressor diode chip 1 is arranged between the first copper electrode 11 and the second copper electrode 12, and the first pin 21 is connected to the first copper electrode 11 and the second copper electrode 12; the second transient voltage suppressor diode chip 2 and the third transient voltage suppressor diode chip 3 are stacked and located between the second copper electrode 12 and the third copper electrode 13, and the second pin 22 is connected to the third copper electrode 13; the fourth transient voltage suppressor diode chip 4 and the fifth transient voltage suppressor diode chip 5 are stacked and located between the second copper electrode 12 and the fourth copper electrode 14, and the third pin 23 is connected to the fourth copper electrode 14.

[0035] Specifically, the transient voltage suppressor is a three-in-one transient voltage suppressor, and the internal package contains at least five transient voltage suppressor diode chips. The second transient voltage suppressor diode chip 2, the third transient voltage suppressor diode chip 3, the fourth transient voltage suppressor diode chip 4, and the fifth transient voltage suppressor diode chip 5 are rectangular chips with small pins. The second transient voltage suppressor diode chip 2 and the third transient voltage suppressor diode chip 3 connected in series together are considered a TVS structure, and the fourth transient voltage suppressor diode chip 4 and the fifth transient voltage suppressor diode chip 5 connected in series together are considered a TVS structure. Together with the first transient voltage suppressor diode chip 1, which is considered a TVS structure, the five TVS chips form a three-in-one transient voltage suppressor. The first pin 21, the second pin 22, and the third pin 23 can all reach the protection voltage level of the original three parallel TVSs. Compared with the existing solution, it can directly reduce the packaging cost and improve the integration of the device.

[0036] The technical solution of the embodiment of the present utility model is to simplify the device size, improve the integration of the transient suppressor, reduce the board area occupied by the protective devices, and improve the circuit integration by simplifying the three transient suppression diodes connected in parallel to one transient voltage suppressor connected in parallel to the circuit. The use of one transient voltage suppressor can replace and surpass the lightning protection capability of the three transient suppression diodes in the original solution, improve the protection capability of the transient voltage suppressor, increase the protection capability of the POE port, and directly reduce the packaging cost and improve the device integration compared with the existing solution. In summary, the present utility model solves the problem that the existing technology needs to use three independent TVS, which is costly; the three devices need to occupy three pads on the PCB board, which occupies a large board area and affects the overall circuit integration.

[0037] Continue to refer Figure 2 and Figure 3 Optionally, the transient voltage suppressor further includes solder or conductive glue (not shown in the figure), which is used to connect the first transient voltage suppressor diode chip 1, the first copper electrode 11 and the second copper electrode 12, to connect the second transient voltage suppressor diode chip 2 and the second copper electrode 12, to connect the third transient voltage suppressor diode chip 3 and the third copper electrode 13, to connect the fourth transient voltage suppressor diode chip 4 and the second copper electrode 12, and to connect the fifth transient voltage suppressor diode chip 5 and the fourth copper electrode 14.

[0038] Specifically, solder or conductive adhesive is applied to both sides of the chip, and at least one copper electrode is positioned on one side of the solder to connect to the TVS diode chip. Manufacturing methods: Using a unique semiconductor vacuum welding process, copper electrodes and solder are used to connect the TVS diode chip. A stacked solder joint is created to meet the product's dimensions, and low-stress epoxy resin is used for encapsulation to create a three-in-one transient voltage suppressor.

[0039] Continue to refer Figure 2 and Figure 3 Optionally, the first pin 21, the second pin 22 and the third pin 23 are combined to form a Y-shaped structure.

[0040] Specifically, the Y-shaped structure can effectively reduce the PCB board area reserved for protective devices, laying a good foundation for the industry upgrade of POE ports.

[0041] Continue to refer Figure 2 and Figure 3 Optionally, the second TVS diode chip 2 is connected in series with the third TVS diode chip 3, and the fourth TVS diode chip 4 is connected in series with the fifth TVS diode chip 5; the second TVS diode chip 2 and the third TVS diode chip 3 connected in series are connected in parallel with the fourth TVS diode chip 4 and the fifth TVS diode chip 5 connected in series.

[0042] Continue to refer Figure 2 and Figure 3 Optionally, the second TVS diode chip 2 and the third TVS diode chip 3 connected in series are connected in series with the first TVS diode chip 1; the fourth TVS diode chip 4 and the fifth TVS diode chip 5 connected in series are connected in series with the first TVS diode chip 1.

[0043] Continue to refer Figure 2 and Figure 3 Optionally, the second pin 22 and the third copper electrode 13 are integrally formed, and the third pin 23 and the fourth copper electrode 14 are integrally formed.

[0044] Specifically, the copper electrode and the pin are integrated, and the pin extends from the copper electrode for direct welding and power supply.

[0045] Continue to refer Figure 2 and Figure 3 Optionally, the second TVS diode chip 2 is of the same model as the third TVS diode chip 3 , the fourth TVS diode chip 4 , and the fifth TVS diode chip 5 .

[0046] Specifically, the first TVS diode chip 1 is a square chip, while the second TVS diode chip 2, the third TVS diode chip 3, the fourth TVS diode chip 4, and the fifth TVS diode chip 5 are rectangular chips with small pins. By combining multiple chips, a lightning surge level can be met by any combination of the three circuits. The multi-layer combination of square and rectangular chips achieves product miniaturization (small size, high current flow). Double-convex copper particles are used to match the square and rectangular chips.

[0047] Figure 4 1 is a schematic diagram of an open-circuit voltage waveform of a transient voltage suppressor provided according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a packaged transient voltage suppressor provided by an embodiment of the present invention, with reference to Figure 4 and Figure 5 Optionally, the protection voltages of the first pin, the second pin, and the third pin are all 50V-60V.

[0048] Continue to refer Figure 4 and Figure 5 Optionally, the first pin, the second pin and the third pin are used to withstand a lightning pulse with an open circuit voltage wave of 10 / 700μS and a voltage greater than 4kV.

[0049] Specifically, the transient voltage suppressor (TVS) has three pins: pin 1, pin 2, and pin 3. The TVS device voltage level between pins can achieve a 50-60V voltage protection effect. Using a 10 / 700μS open-circuit voltage wave for lightning pulses, all three pins can clamp voltages exceeding 4kV. This provides effective protection for the entire protected port, a higher level of integration, and industry-leading cost advantages.

[0050] Pins 1, 2, and 3 enhance lightning surge protection. Each output pin can withstand an open-circuit voltage surge of 10 / 700μS and lightning pulses exceeding 4kV. This improves overall product performance, reduces port protection costs, and frees up space on the PCB for improved transmission efficiency.

[0051] Figure 61 is a front view of a transient voltage suppressor provided according to an embodiment of the present utility model. Figure 7 1 is a side view of a transient voltage suppressor provided according to an embodiment of the present utility model. Figure 8 is a side view of another transient voltage suppressor provided according to an embodiment of the present invention, with reference to Figure 6 、 Figure 7 and Figure 8 By reducing the number of TVS diodes connected in parallel from three to one TVS connected in parallel, the device size is reduced and the circuit integration is improved. Using a single TVS replaces and surpasses the lightning protection capabilities of the original three TVS diodes, improving the protection capabilities of TVSs in the 50-60V voltage range.

[0052] Figure 9 This is a schematic diagram of a security POE port circuit board provided according to an embodiment of the present invention, with reference to Figure 9 The embodiment of the present invention further provides a security POE port circuit board, which includes the transient voltage suppressor provided by any embodiment of the present invention.

[0053] Since the security POE port circuit board includes the transient voltage suppressor provided by any embodiment of the present invention, the beneficial effects of the above-mentioned security POE port circuit board and the transient voltage suppressor are the same, which will not be repeated here.

[0054] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A transient voltage suppressor, characterized in that: include: a first TVS diode chip, a second TVS diode chip, a third TVS diode chip, a fourth TVS diode chip, a fifth TVS diode chip, a first copper electrode, a second copper electrode, a third copper electrode, a fourth copper electrode, a first pin, a second pin, and a third pin; The first transient suppression diode chip is arranged between the first copper electrode and the second copper electrode, and the first pin is connected to the first copper electrode and the second copper electrode; The second TVS diode chip and the third TVS diode chip are stacked and located between the second copper electrode and the third copper electrode, and the second pin is connected to the third copper electrode; The fourth transient voltage suppressor diode chip and the fifth transient voltage suppressor diode chip are stacked and located between the second copper electrode and the fourth copper electrode, and the third pin is connected to the fourth copper electrode.

2. The transient voltage suppressor according to claim 1, wherein: The device further includes solder or conductive glue, which is used to connect the first transient suppression diode chip, the first copper electrode and the second copper electrode, to connect the second transient suppression diode chip and the second copper electrode, to connect the third transient suppression diode chip and the third copper electrode, to connect the fourth transient suppression diode chip and the second copper electrode, and to connect the fifth transient suppression diode chip and the fourth copper electrode.

3. The transient voltage suppressor according to claim 1, wherein: The first pin, the second pin and the third pin form a Y-shaped structure in combination.

4. The transient voltage suppressor according to claim 1, wherein: The protection voltages of the first pin, the second pin, and the third pin are all 50V-60V.

5. The transient voltage suppressor according to claim 1, wherein: The first pin, the second pin, and the third pin are used to withstand a lightning pulse with an open-circuit voltage wave of 10 / 700 μS and a voltage greater than 4 kV.

6. The transient voltage suppressor according to claim 1, wherein: The second TVS diode chip is connected in series with the third TVS diode chip, and the fourth TVS diode chip is connected in series with the fifth TVS diode chip; The second TVS diode chip and the third TVS diode chip connected in series are connected in parallel with the fourth TVS diode chip and the fifth TVS diode chip connected in series.

7. The transient voltage suppressor according to claim 6, wherein: The second TVS diode chip and the third TVS diode chip connected in series are connected in series with the first TVS diode chip; The fourth TVS diode chip and the fifth TVS diode chip connected in series are connected in series with the first TVS diode chip.

8. The transient voltage suppressor according to claim 1, wherein: The second pin and the third copper electrode are integrally formed, and the third pin and the fourth copper electrode are integrally formed.

9. The transient voltage suppressor according to claim 1, wherein: The second TVS diode chip has the same model as the third TVS diode chip, the fourth TVS diode chip, and the fifth TVS diode chip.

10. A security POE port circuit board, characterized in that: The transient voltage suppressor comprises the transient voltage suppressor according to any one of claims 1 to 9.

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