Charging circuit and electronic equipment

Abstract

The utility model relates to a charging circuit and electronic equipment, and the charging circuit comprises a receiving circuit which is used for receiving an electric signal; a battery circuit; and a plurality of chips, each of the plurality of chips comprises a first type of pins, an input pin and an output pin, the input pin of each chip is connected to the receiving circuit, the output pin of each chip is connected to the battery circuit, the first type of pins of different chips are connected with each other, and the first type of pins of different chips are connected with each other. The chip in the working state receives an electric signal from the receiving circuit through the input pin, and transmits the electric signal to the battery circuit through the output pin to charge a battery; the chips in the working state output level signals through the first type of pins, and the chips not in the working state receive the level signals through the first type of pins. According to the charging circuit, the plurality of chips which are connected in parallel are configured in the charging circuit, when part of the chips break down, some chips can still work, normal operation of the charging system is ensured, and the reliability of the charging system is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of charging technology, and in particular to a charging circuit and electronic equipment. Background Art

[0002] With the rapid development of mobile communication technology, electronic devices such as mobile phones and tablet computers have become indispensable in people's daily lives. Among them, the charging function of mobile phones and other electronic devices has become one of the common functions in people's daily lives due to its convenience.

[0003] However, as the usage rate of the charging function increases, it is more likely that the charging receiving chip will be damaged. When the charging receiving chip is damaged, the electronic device can no longer be charged through the charging function. Utility Model Content

[0004] To overcome the problems existing in the related art, the present disclosure provides a charging circuit and an electronic device.

[0005] According to a first aspect of an embodiment of the present disclosure, a charging circuit is provided, comprising: a receiving circuit; a battery circuit; and a plurality of chips, each of the plurality of chips comprising a first-class pin, an input pin, and an output pin, the input pin of each chip being connected to the receiving circuit, the output pin of each chip being connected to the battery circuit, and the first-class pins of different chips being connected to each other, wherein a chip in a working state receives an electrical signal from the receiving circuit through the input pin, and transmits the electrical signal to the battery circuit through the output pin to charge the battery; a chip in a working state outputs a level signal through the first-class pin, and a chip not in a working state receives a level signal through the first-class pin.

[0006] In some embodiments, each of the multiple chips includes a voltage circuit VRECT; the charging circuit further includes: a first capacitor circuit; one end of the first capacitor circuit is grounded, and the other end is connected to the voltage circuit VRECT of each chip.

[0007] In some embodiments, the charging circuit further includes: a second capacitor circuit; one end of the second capacitor circuit is grounded, and the other end is connected to the output pin of each chip and the battery circuit.

[0008] In some embodiments, the charging circuit further includes: a processor including a plurality of second-category pins; each of the plurality of chips includes a third-category pin connected to the second-category pin of the processor, and the third-category pin of each chip is connected to a different second-category pin among the plurality of second-category pins.

[0009] In some embodiments, the second category of pins and the third category of pins include at least one of the following: the second category of pins and the third category of pins are both serial clock line SCL pins; the second category of pins and the third category of pins are both serial data line SDA pins; the second category of pins and the third category of pins are both interrupt signal INT pins; the second category of pins are general-purpose input and output GPIO pins, and the third category of pins are power indication PowerGood pins.

[0010] In some embodiments, the first type of pins of each chip in the plurality of chips include general purpose input and output (GPIO) pins; and the general purpose input and output (GPIO) pins of different chips are connected to each other.

[0011] In some embodiments, the receiving circuit includes a resonant coil and a resonant capacitor, and the resonant coil and the resonant capacitor are connected in series to form a capacitor-inductor resonant circuit.

[0012] In some embodiments, each of the multiple chips includes a rectifier bridge, which includes a first transistor, a second transistor, a third transistor and a fourth transistor; the source of the first transistor is connected to the resonant coil and the drain of the second transistor, and the drain of the first transistor is connected to the output pin; the source of the second transistor is grounded, and the drain of the second transistor is connected to the resonant coil and the source of the first transistor; the source of the third transistor is connected to the resonant capacitor and the drain of the fourth transistor, and the drain of the third transistor is connected to the output pin; the source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the resonant capacitor and the source of the third transistor.

[0013] In some embodiments, the battery circuit includes a power management chip and / or a charge pump chip.

[0014] According to a second aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: the charging circuit described in any one of the first aspects.

[0015] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: the present disclosure configures multiple chips connected in parallel in the charging circuit, and enables the chip in working state to communicate with other chips to stop the other chips from working. In this way, when some chips fail, there are still chips that can work, thereby ensuring the normal operation of the charging system and improving the reliability of the charging system.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0018] Figure 1 is a circuit diagram of a charging circuit according to an exemplary embodiment.

[0019] Figure 2 is a circuit diagram of a charging circuit according to an exemplary embodiment.

[0020] Figure 3 is a circuit diagram of a charging circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0021] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0022] In related technologies, electronic devices that support wireless charging function are equipped with a wireless charging receiving chip. The wireless charging receiving chip can be used to convert the alternating current received by the wireless charging coil into direct current for use by the electronic device, and the wireless charging receiving chip can also perform protocol communication with the wireless charging transmitter.

[0023] When the wireless charging chip is damaged, the electronic device can no longer be charged via the wireless charging function and can only be charged via the wired charging function or cannot be charged at all.

[0024] In order to solve the above technical problems, according to an embodiment of the present disclosure, a charging circuit and an electronic device are provided, wherein the charging circuit includes: a receiving circuit; a battery circuit; and multiple chips, each of the multiple chips including a first-class pin, an input pin, and an output pin, the input pin of each chip being connected to the receiving circuit, the output pin of each chip being connected to the battery circuit, and the first-class pins of different chips being connected to each other, wherein a chip in a working state receives an electrical signal from the receiving circuit through the input pin, and transmits the electrical signal to the battery circuit through the output pin to charge the battery; a chip in a working state outputs a level signal through the first-class pin, and a chip not in a working state receives a level signal through the first-class pin.

[0025] The present disclosure configures a plurality of chips connected in parallel in a charging circuit, and enables a chip in a working state to communicate with other chips to stop the other chips from working. Thus, when some chips fail, there are still chips that can work, thereby ensuring the normal operation of the charging system and improving the reliability of the charging system.

[0026] It can be understood that the charging circuit involved in the present disclosure can be applicable to any terminal listed below.

[0027] It is understandable that the terminal involved in the present disclosure may also be referred to as a terminal device, user equipment (UE), mobile station (MS), mobile terminal (MT), etc., which is a device that provides voice and / or data connectivity to users. For example, the terminal can be a handheld device with wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals are: smart phones (Mobile Phones), pocket personal computers (PPCs), handheld computers, personal digital assistants (PDAs), laptops, tablet computers, wearable devices, or vehicle-mounted devices, etc. In addition, when it is a vehicle-to-everything (V2X) communication system, the terminal device can also be a vehicle-mounted device. It should be understood that the embodiments of the present disclosure do not limit the specific technology and specific device form adopted by the terminal.

[0028] Figure 1 is a circuit diagram of a charging circuit according to an exemplary embodiment.

[0029] In some embodiments, as Figure 1 As shown, the charging circuit includes: a receiving circuit 100, a battery circuit 200 and multiple chips.

[0030] The charging circuit can receive external current through the receiving circuit 100 .

[0031] Exemplarily, the receiving circuit 100 may be configured to receive a charging signal transmitted by an external wireless charging transmitter and convert the charging signal into current.

[0032] Each of the plurality of chips includes a first type of pin, an input pin, and an output pin.

[0033] The input pins are used to connect to the receiving circuit 100 . Current from the receiving circuit 100 can flow into the chip in the working state through the input pins. In addition, the input pins of each chip are connected to the receiving circuit 100 .

[0034] The output pins are used to connect to the battery circuit 200 . A chip in a working state can output current to the battery circuit 200 through the output pins, and the output pins of each chip are connected to the battery circuit 200 .

[0035] The first type pins of different chips are connected to each other, and the first type pins can be used for communication between multiple chips.

[0036] A chip in an active state can output a level signal through the first type of pins, while a chip in an inactive state can receive a level signal through the first type of pins and remain in an inactive state. The active state refers to a state in which the chip can normally complete tasks such as communication and AC power conversion after power is applied.

[0037] The embodiment of the present disclosure configures multiple chips connected in parallel in the charging circuit, and enables the chip in working state to communicate with other chips to stop the other chips from working. In this way, when some chips fail, there are still chips that can work, thereby ensuring the normal operation of the charging system and improving the reliability of the charging system.

[0038] In some embodiments, the receiving circuit 100 may be a circuit for receiving wireless charging signals and converting them into current. By enabling a working chip to communicate with other chips, causing them to stop working, the system ensures the normal operation of the wireless charging system even when some chips fail, reduces the chances of the system malfunctioning due to chip damage, and improves the reliability of the wireless charging system.

[0039] However, the present disclosure is not limited thereto, and the receiving circuit 100 may also be a circuit for receiving wired charging current.

[0040] In some embodiments, a chip in an operating state can output a level signal via a first-type pin, while a chip not in an operating state receives the level signal via the first-type pin and maintains itself in an inoperative state through a logic control circuit within the chip. In other embodiments, the charging circuit may include a processor that can connect to multiple chip signals and can obtain and monitor the operating status of each chip. When one chip is in an operating state, the processor can put other chips into an inoperative state.

[0041] In some embodiments, one chip among the multiple chips can be configured to directly enter a working state and output a level signal through the first type of pin after the chip is powered on without detecting whether the first type of pin receives a level signal.

[0042] Other chips in the plurality of chips may be configured to monitor whether the first type of pin receives a level signal after the chip is powered on. When the first type of pin receives a level signal, the chip does not enter a working state. When the first type of pin does not receive a level signal within a threshold time, the chip enters a working state.

[0043] In some embodiments, different chips have different threshold times so that the chips can sequentially detect whether to enter the working state. For example, the chips may include a first chip 10, a second chip 20, and a third chip 30. The first chip 10 may be configured not to detect whether a level signal is received, the second chip 20 may be configured to wait for one unit time and then enter the working state if no level signal is received, and the third chip 30 may be configured to wait for two unit times and then enter the working state if no level signal is received.

[0044] In some embodiments, as Figure 1 As shown, the plurality of chips may include a first chip 10 and a second chip 20 , and the first chip 10 includes a first current input pin Vin1 , a first current output pin Vout1 and a first pin 11 , and the second chip 20 includes a second current input pin Vin2 , a second current output pin Vout2 and a second pin 21 .

[0045] When the first chip 10 is working, the first chip 10 receives an electrical signal from the receiving circuit 100 through the first current input pin Vin1 and outputs the electrical signal to the battery circuit 200 through the first current output pin Vout1 .

[0046] When the second chip 20 is working, the second chip 20 receives the electrical signal from the receiving circuit 100 through the second current input pin Vin2 and outputs the electrical signal to the battery circuit 200 through the second current output pin Vout2.

[0047] The first pin 11 may be connected to the second pin 21 , and the first chip 10 and the second chip 20 may communicate through the connection relationship between the first pin 11 and the second pin 21 .

[0048] When the first chip 10 is in the working state, the first chip 10 can send a level signal to the second chip 20 through the first pin 11 and the second pin 21. After receiving the level signal, the second chip 20 stops working or does not enter the working state.

[0049] The embodiment of the present disclosure configures the first chip 10 and the second chip 20 so that when some chips fail, some chips can still operate, thereby ensuring the normal operation of the wireless charging system and improving the reliability of the charging system.

[0050] In some embodiments, the chip can be a wireless charging receiving chip, which can be used to convert the alternating current received by the wireless charging coil into direct current for use by electronic devices, and the wireless charging receiving chip can also perform protocol communication with the wireless charging transmitting end.

[0051] In some embodiments, when a chip is in a fault state, the chip cannot communicate with other chips through the first type of pins. At this time, other chips fail to receive the signal and enter the working state normally to ensure the normal operation of the wireless charging system.

[0052] For example, when the first chip 10 is in a fault state, the first chip 10 cannot send a signal to the second chip 20, and the second chip 20 fails to receive a signal from the first chip 10, and the second chip 20 enters a working state to ensure the normal operation of the wireless charging system.

[0053] Figure 2 is a circuit diagram of a charging circuit according to an exemplary embodiment.

[0054] In some embodiments, as Figure 2 As shown, the chip may further include a third chip 30 , and the third chip 30 may include a third pin 31 .

[0055] The first pin 11 , the second pin 21 , and the third pin 31 may be connected to each other, so that the first chip 10 , the second chip 20 , and the third chip 30 can communicate with each other.

[0056] When the first chip 10 is in the working state, the first chip 10 can send a level signal to the second chip 20 and the third chip 30 . After receiving the level signal, the second chip 20 and the third chip 30 stop working or do not enter the working state.

[0057] When the first chip 10 fails and cannot enter the working state, the second chip 20 enters the working state after not receiving the level signal and sends a level signal to the third chip 30. The third chip 30 stops working or does not enter the working state after receiving the level signal.

[0058] When both the first chip 10 and the second chip 20 fail and cannot enter the working state, the third chip 30 enters the working state after not receiving the level signal.

[0059] The embodiment of the present disclosure configures the first chip 10, the second chip 20 and the third chip 30 so that when some chips fail, there are still chips that can work, thereby ensuring the normal operation of the wireless charging system and improving the reliability of the charging system.

[0060] Figure 3 is a circuit diagram of a charging circuit according to an exemplary embodiment.

[0061] In some embodiments, as Figure 3 As shown, each of the plurality of chips includes a voltage circuit VRECT.

[0062] The charging circuit further includes a first capacitor circuit 50 , one end of which is grounded, and the other end of which is connected to the voltage circuit VRECT of each chip. The first capacitor circuit 50 may be a filter capacitor circuit.

[0063] Since the charging circuit has at most one chip working at the same time, multiple chips can be connected to the same first capacitor circuit 50 , which can save the component cost of the charging circuit without exceeding the carrying capacity of the circuit components.

[0064] In some embodiments, as Figure 3 As shown, the first chip 10 may include a first voltage circuit VRECT1 , and the second chip 20 may include a second voltage circuit VRECT2 . The first voltage circuit VRECT1 and the second voltage circuit VRECT2 may be connected to the other end of the first capacitor circuit 50 .

[0065] In some embodiments, as Figure 3 As shown, the charging circuit further includes: a second capacitor circuit 40, one end of the second capacitor circuit 40 is grounded, and the other end is connected to the current output pin of each chip and the battery circuit 200. The second capacitor circuit 40 can be an output capacitor circuit.

[0066] Since the charging circuit has at most one chip working at the same time, multiple chips can be connected to the same second capacitor circuit 40 , which can save the component cost of the charging circuit without exceeding the carrying capacity of the circuit components.

[0067] In some embodiments, as Figure 3 As shown, the first chip 10 may include a first current output pin Vout1 , and the second chip 20 may include a second current output pin Vout2 . The first current output pin Vout1 and the second current output pin Vout2 may be connected to the other end of the second capacitor circuit 40 .

[0068] In some embodiments, as Figure 3 As shown, the charging circuit further includes: a processor 300.

[0069] The processor 300 may include a plurality of second-category pins.

[0070] Each of the multiple chips may include a third-category pin, which can be connected to the second-category pin of the processor 300 for signal transmission. The third-category pin of each chip is connected to a different second-category pin among the multiple second-category pins. By connecting the signal transmission pins of the multiple chips to different second-category pins of the processor 300, the processor 300 can identify and obtain operating status information of different chips and identify and send instructions to different chips. This also prevents the failure of a single chip from paralyzing the information circuits of the processor 300.

[0071] In some embodiments, as Figure 3 As shown, the first chip 10 may include a first interrupt signal pin INT1 , the second chip 20 may include a second interrupt signal pin INT2 , and the second type of pins of the processor 300 may include a first processor pin 301 and a second processor pin 302 .

[0072] The first interrupt signal pin INT1 may be connected to the first processor pin 301 , so that the processor 300 may send an interrupt signal to the first chip 10 through the first processor pin 301 to stop the first chip 10 from operating.

[0073] The second interrupt signal pin INT2 may be connected to the second processor pin 302 , so that the processor 300 may send an interrupt signal to the second chip 20 through the second processor pin 302 to stop the second chip 20 from working.

[0074] In some embodiments, as Figure 3 As shown, the second category pins and the third category pins may include at least one of the following: the second category pins and the third category pins are both serial clock line SCL pins; the second category pins and the third category pins are both serial data line SDA pins; the second category pins and the third category pins are both interrupt signal INT pins; the second category pins are general purpose input and output GPIO pins, and the third category pins are power indication PowerGood pins.

[0075] In some embodiments, as Figure 3 As shown, the second type of pins and the third type of pins both include a serial clock line SCL pin, and the second type of pins and the third type of pins both include a serial data line SDA pin.

[0076] The first chip 10 may include a first serial clock line pin SCL1 and a first serial data line pin SDA1 , and the second chip 20 may include a second serial clock line pin SCL2 and a second serial data line pin SDA2 .

[0077] The second category of pins of the processor 300 may include a first serial clock bus pin 311 , a first serial data bus pin 312 , a second serial clock bus pin 321 , and a second serial data bus pin 322 .

[0078] The first serial clock bus pin 311 can be connected to the first serial clock line pin SCL1, the first serial data bus pin 312 can be connected to the first serial data line pin SDA1, the second serial clock bus pin 321 can be connected to the second serial clock line pin SCL2, and the second serial data bus pin 322 can be connected to the second serial data line pin SDA2.

[0079] Through the above connection relationship, the data transmission requirements between the first chip 10 and the second chip 20 and the processor 300 can be met.

[0080] Furthermore, when a chip fails, the chip will pull down the voltage level of the serial communication bus to which it is connected, causing the serial communication bus to malfunction. Therefore, the above connection relationship can maintain the independence of the serial communication buses between different chips, preventing the failure of a single chip from affecting the normal operation of the processor 300.

[0081] In some embodiments, as Figure 3 As shown, the second type of pins are general-purpose input and output (GPIO) pins, and the third type of pins are power indication (PowerGood) pins.

[0082] When the chip is powered on, if the voltage flowing into the input pin is within the threshold range, the power indication PowerGood pin can send a high level to the general input and output GPIO pin of the processor 300 to indicate that the power is normal. If the voltage flowing into the input pin is not within the threshold range, the power indication PowerGood pin can send a low level to the general input and output GPIO pin of the processor 300 to indicate that the power is abnormal.

[0083] The first chip 10 may include a first power indication pin PowerGood1, the second chip 20 may include a second power indication pin PowerGood2, and the second type of pins of the processor 300 may include a third processor pin 303 and a fourth processor pin 304, wherein the third processor pin 303 and the fourth processor pin 304 may be general purpose input and output GPIO pins.

[0084] The first power indication pin PowerGood1 can be connected to the third processor pin 303, so that the processor 300 can receive the power indication signal sent by the first chip 10 through the third processor pin 303 to obtain whether the power connected to the first chip 10 is abnormal.

[0085] The second power indication pin PowerGood2 can be connected to the fourth processor pin 304, so that the processor 300 can receive the power indication signal sent by the second chip 20 through the fourth processor pin 304 to obtain whether the power connected to the second chip 20 is abnormal.

[0086] In some embodiments, as Figure 3 As shown, the first type of pins of each chip in the multiple chips can include general-purpose input and output GPIO pins. The general-purpose input and output GPIO pins of different chips are connected to each other. The chip can send level signals to other chips through the general-purpose input and output GPIO pins to achieve communication between chips.

[0087] In some embodiments, as Figure 3 As shown, the receiving circuit 100 may include a resonant coil 101 and a resonant capacitor 102. The resonant coil 101 and the resonant capacitor 102 are connected in series to form a capacitor-inductor resonant circuit. The receiving circuit 100 can receive the wireless charging signal through the circuit resonance of the capacitor-inductor resonant circuit and convert it into an electrical signal to realize the reception of the wireless charging signal.

[0088] In some embodiments, as Figure 3 As shown, each of the multiple chips may include a rectifier bridge, which may be used to convert the alternating current output by the receiving circuit 100 to the chip into direct current.

[0089] The rectifier bridge may include a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. For example, the rectifier bridge may include a first metal-oxide field effect transistor, a second metal-oxide field effect transistor, a third metal-oxide field effect transistor, and a fourth metal-oxide field effect transistor.

[0090] The source of the first transistor Q1 is connected to the resonant coil 101 and the drain of the second transistor Q2 , and the drain of the first transistor Q1 is connected to the output pin.

[0091] The source of the second transistor Q2 is grounded, and the drain of the second transistor Q2 is connected to the resonant coil 101 and the source of the first transistor Q1.

[0092] The source of the third transistor Q3 is connected to the resonant capacitor 102 and the drain of the fourth transistor Q4 , and the drain of the third transistor Q3 is connected to the output pin.

[0093] The source of the fourth transistor Q4 is grounded, and the drain of the fourth transistor Q4 is connected to the resonant capacitor 102 and the source of the third transistor Q3.

[0094] By matching the switching frequency of the transistors of the rectifier bridge with the current frequency of the receiving circuit 100, the current direction of the negative half cycle of the AC power is made the same as the current direction of the positive half cycle, so that the rectifier bridge can convert the AC power output by the receiving circuit 100 into DC power.

[0095] The rectifier bridge may include a first access point AC1 and a second access point AC2 . The first access point AC1 is disposed between the third transistor Q3 and the fourth transistor Q4 . The second access point AC2 is disposed between the first transistor Q1 and the second transistor Q2 .

[0096] The first access point AC1 can be connected to the resonant capacitor 102, and the second access point AC2 can be connected to the resonant coil 101, so that the two access points of the rectifier bridge are connected to the two AC output lines of the receiving circuit 100, so that the rectifier bridge converts AC power into DC power.

[0097] In some embodiments, the battery circuit 200 may include a power management chip and / or a charge pump chip. The power management chip may be used for power conversion, distribution, and monitoring and control of power status. The charge pump chip may be provided with a charge pump and regulate and monitor the current flowing through the charge pump.

[0098] The chip in working state can output current to the battery circuit 200 through the output pin. The current can be distributed and monitored by the power management chip and / or the charge pump chip to charge the battery.

[0099] Based on the same concept, an embodiment of the present disclosure further provides an electronic device.

[0100] The electronic device may include a laptop computer, a desktop computer, a mobile phone, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, a translator, or a wearable device such as a watch or a bracelet. The electronic device may be any electronic device with a charging circuit. In the following description, a mobile phone is used as an example, but the present disclosure is not limited thereto.

[0101] In some embodiments, an electronic device may include a charging circuit, which may be a charging circuit that supports wired charging. The electronic device may receive wireless charging signals through the charging circuit, thereby implementing wireless charging functionality. By configuring multiple chips in parallel within the charging circuit and enabling active chips to communicate with other chips to stop them, the remaining chips can function even if some chips fail, ensuring the normal operation of the wired charging system and reducing the risk of the wired charging system malfunctioning due to chip damage.

[0102] In some embodiments, an electronic device may include a charging circuit, which may be a charging circuit that supports wireless charging. The electronic device may receive wireless charging signals through the charging circuit to implement wireless charging. By configuring multiple chips in parallel within the charging circuit and enabling the working chip to communicate with other chips to stop them, even if some chips fail, some chips can still operate, thereby ensuring the normal operation of the wireless charging system and improving the reliability of the charging system.

[0103] In some embodiments, the electronic device can be a non-porous electronic device that can be charged via wireless charging, which can improve the dust and water resistance of the electronic device. By improving the durability of the charging circuit, it can reduce the situation where the electronic device cannot be charged.

[0104] It is understood that in this disclosure, "plurality" refers to two or more than two, and other quantifiers are similar. "And / or" describes the association relationship of related objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship. The singular forms "a", "the" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0105] It is further understood that the terms "second," "second," and the like are used to describe various information, but such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another and do not indicate a particular order or level of importance. In fact, expressions such as "second," "secondary," and the like are fully interchangeable. For example, without departing from the scope of this disclosure, the second information may also be referred to as the second information, and similarly, the second information may also be referred to as the second information.

[0106] It can be further understood that the terms "center", "longitudinal", "lateral", "front", "back", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this embodiment and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation.

[0107] It is further understood that, unless otherwise specified, “connection” includes a direct connection where there are no other components between the two elements, and also includes an indirect connection where there are other elements between the two elements.

[0108] It is further understood that although operations are described in a particular order in the drawings in the embodiments of the present disclosure, this should not be construed as requiring that the operations be performed in the particular order shown or in a serial order, or that all of the operations shown be performed to obtain the desired results. In certain circumstances, multitasking and parallel processing may be advantageous.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0110] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the scope of the appended claims.

Claims

1. A charging circuit, characterized in that: The charging circuit comprises: a receiving circuit, for receiving an electrical signal; battery circuit; and Multiple chips, each of the multiple chips includes a first type pin, an input pin, and an output pin, the input pin of each chip is connected to the receiving circuit, the output pin of each chip is connected to the battery circuit, and the first type pins of different chips are connected to each other, The chip in working state receives the electrical signal from the receiving circuit through the input pin, and transmits the electrical signal to the battery circuit through the output pin to charge the battery; The chip in the working state outputs a level signal through the first type of pins, and the chip not in the working state receives a level signal through the first type of pins.

2. The charging circuit according to claim 1, wherein: Each of the plurality of chips includes a voltage circuit VRECT; The charging circuit further includes: a first capacitor circuit; One end of the first capacitor circuit is grounded, and the other end is connected to the voltage circuit VRECT of each chip.

3. The charging circuit according to claim 1, wherein: The charging circuit further includes: a second capacitor circuit; One end of the second capacitor circuit is grounded, and the other end is connected to the output pin of each chip and the battery circuit.

4. The charging circuit according to claim 1, wherein: The charging circuit further includes: a processor comprising a plurality of second-category pins; Each of the plurality of chips includes a third-type pin connected to the second-type pin of the processor, and the third-type pin of each chip is connected to a different second-type pin of the plurality of second-type pins.

5. The charging circuit according to claim 4, characterized in that: The second type of pins and the third type of pins include at least one of the following: The second type of pins and the third type of pins are both serial clock line SCL pins; The second type of pins and the third type of pins are both serial data line SDA pins; The second type of pins and the third type of pins are both interrupt signal INT pins; The second type of pins are general purpose input and output (GPIO) pins, and the third type of pins are power indication (PowerGood) pins.

6. The charging circuit according to claim 1, wherein: The first type of pins of each chip in the plurality of chips include general purpose input and output (GPIO) pins; The general purpose input and output (GPIO) pins of different chips are connected to each other.

7. The charging circuit according to any one of claims 1 to 6, characterized in that: The receiving circuit includes a resonant coil and a resonant capacitor, and the resonant coil and the resonant capacitor are connected in series to form a capacitor-inductor resonant circuit.

8. The charging circuit according to claim 7, wherein: Each of the plurality of chips includes a rectifier bridge, and the rectifier bridge includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The source of the first transistor is connected to the resonant coil and the drain of the second transistor, and the drain of the first transistor is connected to the output pin; The source of the second transistor is grounded, and the drain of the second transistor is connected to the resonant coil and the source of the first transistor; The source of the third transistor is connected to the resonant capacitor and the drain of the fourth transistor, and the drain of the third transistor is connected to the output pin; The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the resonant capacitor and the source of the third transistor.

9. The charging circuit according to claim 1, wherein: The battery circuit includes a power management chip and / or a charge pump chip.

10. An electronic device, characterized in that: include: The charging circuit according to any one of claims 1 to 9.

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