Communication level conversion circuit

Abstract

The utility model discloses a communication level conversion circuit, which belongs to the technical field of circuits, and comprises a processor, a memory, a pull-up resistor I, a pull-up resistor II, an SOUT signal line, a pull-up power supply I and a pull-up power supply II, one end of the pull-up resistor I is electrically connected with the pull-up power supply I, the other end of the pull-up resistor I is electrically connected with the SOUT signal line, and the other end of the pull-up resistor II is electrically connected with the processor. One end of the second pull-up resistor is connected with the second pull-up power supply, the other end of the second pull-up resistor is electrically connected with the SOUT signal line, the two ends of the SOUT signal line are electrically connected with the processor and the memory respectively, and the processor and the memory are electrically connected through a CS signal line, an SIN signal line, a CLK signal line and an R / W signal line. Through the above mode, by adding one NMOS tube on the SOUT signal line, the signal transmission link is shortened, and the signal error rate is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, in particular to a communication level conversion circuit. Background Art

[0002] With the application of chips with different voltage platforms, many methods have emerged for converting signals of different levels, such as transformer isolation amplification.

[0003] However, with the large-scale integration of analog circuits into chips and the vigorous development of digital signals, the realization of functions has shifted from circuit construction with discrete components to chip selection. Among them, the communication conversion between 5V and 3.3V is particularly widely used, such as the communication between a 5V MCU platform and a 3.3V memory.

[0004] Current shortcomings: The existing voltage platform conversion solution is completed by combining multiple chips. Taking the communication between a 5V MCU platform and a 3.3V memory as an example, in traditional designs, the 5V MCU and the 3.3V memory use SPI communication.

[0005] When writing, the MCU outputs the signal to the level conversion chip through the write pin defined by the chip, such as TI's TXB0104 series chip, to complete the 5V to 3.3V conversion, and then the signal enters the memory. Currently, there are larger capacity 64MFlash chips, such as Infineon's S25FL064L series chips, whose operating voltage is 3.3V. Because the voltage is the same, the write operation can be performed;

[0006] When reading, the signal on the 5V MCU side of the memory needs to be converted from 3.3V to 5V. This can also be achieved by using a level conversion chip such as TI's TXB0104 series chip. Only when the output signal is 5V can it communicate normally with the MCU. Otherwise, communication failure or communication frame loss will occur due to level mismatch.

[0007] In this traditional circuit, two level-conversion chips are required to complete read and write operations between the MCU and the memory. This is costly, space-consuming, and has a long link length, resulting in a high probability of product failure, which is detrimental to circuit design.

[0008] Based on this, the utility model designs a communication level conversion circuit to solve the above problem. Utility Model Content

[0009] In view of the above-mentioned shortcomings of the prior art, the utility model provides a communication level conversion circuit.

[0010] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0011] A communication level conversion circuit includes a processor, a memory, a first pull-up resistor, a second pull-up resistor, an SOUT signal line, a first pull-up power supply, and a second pull-up power supply, wherein one end of the first pull-up resistor is electrically connected to the first pull-up power supply, and the other end of the first pull-up resistor is electrically connected to the SOUT signal line, one end of the second pull-up resistor is connected to the second pull-up power supply, and the other end of the second pull-up resistor is electrically connected to the SOUT signal line, two ends of the SOUT signal line are electrically connected to the processor and the memory, respectively, and the processor and the memory are electrically connected via a CS signal line, a SIN signal line, a CLK signal line, and a R / W signal line;

[0012] It also includes a high-frequency switch device, wherein the conduction control terminal and the signal output terminal of the high-frequency switch device are connected in series with the SOUT signal line, and the conduction control terminal of the high-frequency switch device is close to the storage, and the signal input terminal of the high-frequency switch device is electrically connected to the pull-up power supply 2.

[0013] Furthermore, the high-frequency switching device is an NMOS transistor.

[0014] Furthermore, the drain and gate of the high-frequency switch device are connected in series to the SOUT signal line, the gate of the high-frequency switch device is close to the storage, and the source of the high-frequency switch device is electrically connected to the second pull-up power supply.

[0015] Furthermore, the supply voltage of the pull-up power supply 1 is 5V.

[0016] Furthermore, the supply voltage of the pull-up power supply 2 is 3.3V.

[0017] Furthermore, the processor is an MCU with a 5V voltage platform;

[0018] The memory is a Flash chip with a 3.3V voltage platform.

[0019] Furthermore, the switching frequency of the high-frequency switching device is 6.25 bps-10 bps.

[0020] Furthermore, the switching frequency of the high-frequency switching device is 9 Mbps.

[0021] Compared with the prior art, the present invention has the following beneficial effects: 1. When the present invention is used, the high and low levels of the feedback signal of the storage control the conduction and disconnection of the high-frequency switching device. When the feedback signal of the storage is at a high level, the high-frequency switching device is not turned on, and the signal on the processor side is at a high level due to the action of the pull-up resistor 1. When the feedback signal of the storage is at a low level, the high-frequency switching device is turned on, and the signal of the SOUT signal line input to the processor is at a low level, thereby achieving the same level of signals on both sides of the high-frequency switching device, shortening the signal transmission link, reducing the signal error rate, and reducing costs and PCB space. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0023] Figure 1 This is a schematic diagram of a communication level conversion circuit of the present utility model.

[0024] The numbers in the figure represent:

[0025] 1. Processor 2. Memory 3. High-frequency switching device 4. Pull-up resistor 1 5. Pull-up resistor 2 6. SOUT signal line 7. Pull-up power supply 1 8. Pull-up power supply 2 DETAILED DESCRIPTION

[0026] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0027] Example 1: In some embodiments, please refer to the accompanying drawings of the specification. Figure 1A communication level conversion circuit includes a processor 1, a memory 2, a pull-up resistor 1 4, a pull-up resistor 2 5, an SOUT signal line 6, a pull-up power supply 1 7, and a pull-up power supply 2 8, wherein one end of the pull-up resistor 1 4 is electrically connected to the pull-up power supply 1 7, and the other end of the pull-up resistor 1 4 is electrically connected to the SOUT signal line 6, one end of the pull-up resistor 2 5 is connected to the pull-up power supply 2 8, and the other end of the pull-up resistor 2 5 is electrically connected to the SOUT signal line 6, and both ends of the SOUT signal line 6 are electrically connected to the processor 1 and the memory 2 respectively, and the processor 1 and the memory 2 are electrically connected via a CS signal line, a SIN signal line, a CLK signal line, and a R / W signal line;

[0028] It also includes a high-frequency switch device 3, the conduction control terminal and the signal output terminal of the high-frequency switch device 3 are connected in series with the SOUT signal line 6, and the conduction control terminal of the high-frequency switch device 3 is close to the storage 2, and the signal input terminal of the high-frequency switch device 3 is electrically connected to the pull-up power supply 8.

[0029] When the present invention is in use, the high and low levels of the feedback signal of the storage 2 control the conduction and disconnection of the high-frequency switch device 3. When the feedback signal of the storage 2 is at a high level, the high-frequency switch device 3 is not turned on. The signal on the processor 1 side is at a high level due to the action of the pull-up resistor 4, and the signal input to the processor 1 by the SOUT signal line 6 is at a high level; when the feedback signal of the storage 2 is at a low level, the high-frequency switch device 3 is turned on, and the signal input to the processor 1 by the SOUT signal line 6 is at a low level, thereby achieving the same level of signals on both sides of the high-frequency switch device 3, shortening the signal transmission link, reducing the signal error rate, and reducing cost and PCB space.

[0030] The high frequency switch device 3 is an NMOS transistor;

[0031] The drain and gate of the high-frequency switch device 3 are connected in series to the SOUT signal line 6, and the gate of the high-frequency switch device 3 is close to the storage 2. The source of the high-frequency switch device 3 is electrically connected to the pull-up power supply 2 8;

[0032] The supply voltage of the pull-up power supply 7 is 5V;

[0033] The supply voltage of the pull-up power supply 28 is 3.3V;

[0034] Processor 1 is a 5V voltage platform MCU;

[0035] Storage 2 is a Flash chip with a 3.3V voltage platform;

[0036] The switching frequency of the high-frequency switching device 3 is 6.25 bps-10 bps;

[0037] The switching frequency of the high-frequency switching device 3 is 9 Mbps.

[0038] When the present invention is used, the processor 1 outputs a digital signal according to the SPI protocol requirements of CS, SIN, CLK and R / W. After receiving the signal, the storage 2 feeds back the signal through the SOUT signal line 6. When the storage 2 feeds back a signal level to the processor 1, the high-frequency switch device 3 is disconnected, and the SOUT signal line 6 outputs a level equal to the processor 1 due to the pull-up power supply 7. When the storage 2 feeds back a signal level of 0, the high-frequency switch device 3 is turned on, and the output level of the SOUT signal line 6 is 0.

[0039] This process is repeated, and signals of the same level can be output on both sides of the high-frequency switch device 3 .

[0040] When the utility model is used, an NMOS tube is added to the SOUT signal line, thereby shortening the signal transmission link and reducing the signal error rate.

[0041] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A communication level conversion circuit, characterized in that: The invention comprises a processor (1), a memory (2), a pull-up resistor 1 (4), a pull-up resistor 2 (5), a SOUT signal line (6), a pull-up power supply 1 (7) and a pull-up power supply 2 (8), wherein one end of the pull-up resistor 1 (4) is electrically connected to the pull-up power supply 1 (7), the other end of the pull-up resistor 1 (4) is electrically connected to the SOUT signal line (6), one end of the pull-up resistor 2 (5) is connected to the pull-up power supply 2 (8), the other end of the pull-up resistor 2 (5) is electrically connected to the SOUT signal line (6), the two ends of the SOUT signal line (6) are electrically connected to the processor (1) and the memory (2), respectively, and the processor (1) and the memory (2) are electrically connected via a CS signal line, a SIN signal line, a CLK signal line and a R / W signal line. It also includes a high-frequency switch device (3), wherein the conduction control terminal and the signal output terminal of the high-frequency switch device (3) are connected in series with the SOUT signal line (6), and the conduction control terminal of the high-frequency switch device (3) is close to the storage (2), and the signal input terminal of the high-frequency switch device (3) is electrically connected to the pull-up power supply 2 (8).

2. The communication level conversion circuit according to claim 1, characterized in that: The high-frequency switching device (3) is an NMOS transistor.

3. The communication level conversion circuit according to claim 2, characterized in that: The drain and gate of the high-frequency switch device (3) are connected in series to the SOUT signal line (6), and the gate of the high-frequency switch device (3) is close to the storage (2), and the source of the high-frequency switch device (3) is electrically connected to the second pull-up power supply (8).

4. The communication level conversion circuit according to claim 3, characterized in that: The supply voltage of the pull-up power supply 1 (7) is 5V.

5. The communication level conversion circuit according to claim 4, characterized in that: The supply voltage of the pull-up power supply 2 (8) is 3.3V.

6. The communication level conversion circuit according to claim 5, characterized in that: The processor (1) is an MCU with a 5V voltage platform; The memory (2) is a Flash chip with a 3.3V voltage platform.

7. The communication level conversion circuit according to claim 6, characterized in that: The switching frequency of the high-frequency switching device (3) is 6.25 bps-10 bps.

8. The communication level conversion circuit according to claim 7, characterized in that: The switching frequency of the high-frequency switching device (3) is 9 Mbps.

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