Semiconductor structure

Abstract

The utility model provides a semiconductor structure. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines including a write bit line and a complementary write bit line positioned at a first interconnect layer disposed over the gate structure; and a read word line positioned at the second interconnect layer and electrically coupled to the gate structure, the second interconnect layer disposed below the gate structure.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnects per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be formed using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling has also increased the complexity of processing and manufacturing ICs. For example, the rapid scaling of IC dimensions has resulted in densely spaced source / drain features and gate structures, as well as densely spaced source / drain contacts and gate vias formed thereon. In some IC circuits (e.g., memory devices), a multi-layer interconnect structure is formed above the transistors of the memory cells. This multi-layer interconnect structure provides metal tracks (metal lines) for interconnecting power and signal lines within and between the memory cells of the memory device. With the continued reduction in device size and the denser spacing of transistors, some metal tracks (e.g., bonding pads for signal lines) are formed with reduced dimensions, which can lead to increased parasitic resistance, increased parasitic capacitance, increased process risk, and / or poor connections. Some signal lines may be routed in metal lines far from the memory cells, which can reduce the speed of the memory device. All of these issues pose challenges in terms of performance, yield, and cost. Therefore, while existing memory devices may generally be adequate for their intended purposes, they are not always satisfactory. Utility Model Content

[0004] The present invention provides a semiconductor structure. The semiconductor structure includes a dual-port static random access memory (SRAM) cell, the dual-port SRAM cell including a write port portion and a read port portion, the read port portion electrically coupled to the write port portion and including a transistor having a gate structure. The semiconductor structure also includes: a first plurality of metal lines, including a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first interconnect layer disposed above the gate structure; and a read word line, positioned at a second interconnect layer and electrically coupled to the gate structure, wherein the second interconnect layer is disposed below the gate structure.

[0005] The utility model provides a semiconductor structure comprising: a memory cell connected to a write word line and a read word line; a first interconnect structure disposed above the memory cell and including the write word line; and a second interconnect structure disposed below the memory cell and including the read word line.

[0006] The present invention provides a semiconductor structure. The semiconductor structure includes a first memory cell, the first memory cell including a write port portion; and a read port portion including a transistor and a gate structure, the transistor having first and second source / drain features coupled to a channel region, the gate structure being bonded to the channel region. The semiconductor structure also includes a backside via directly disposed below and in direct contact with the gate structure; and a first interconnect layer disposed below and electrically coupled to the backside via, wherein a read word line is positioned at the first interconnect layer.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic plan view of a portion or the entirety of an IC chip according to various aspects of the present disclosure.

[0009] Figure 1B is a schematic plan view of a portion or the entirety of an array of memory cells (eg, static random access memory (SRAM) cells) according to various aspects of the present disclosure.

[0010] Figure 2 According to various aspects of the present disclosure, Figure 1A 、 Figure 1B A circuit diagram of a memory cell (eg, an SRAM cell) implemented in an IC chip is shown.

[0011] Figure 3 Cross-sectional views illustrating portions or entirety of various layers of a memory device according to various aspects of the present disclosure are shown.

[0012] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 Showing various aspects of the present disclosure Figure 2 Different parts of the layout of a memory device showing an SRAM cell.

[0013] Figure 9 Showing the various aspects of the present disclosure along Figure 4 and Figure 6 A cross-sectional view of a portion or the entirety of a memory device taken along line AA shown in FIG.

[0014] Figure 10 Showing the various aspects of the present disclosure along Figure 9 FIG. 1 is a partial cross-sectional view of the memory device taken along line BB shown in FIG.

[0015] Figure 11 A first alternative layout of part or all of a memory device according to various aspects of the present disclosure is shown.

[0016] Figure 12 A second alternative layout of part or all of a memory device according to various aspects of the present disclosure is shown.

[0017] Figure 13 A third alternative layout of part or all of a memory device according to aspects of the present disclosure is shown.

[0018] Figure 14 The diagram shows a partial or entire layout of various layers of another memory device according to various aspects of the present disclosure.

[0019] Figure 15 Showing various aspects of the present disclosure Figure 14 A first alternative layout of portions or the entirety of the various layers of a memory device in FIG.

[0020] Figure 16 Showing various aspects of the present disclosure Figure 14 A second alternative layout of portions or all of the various layers of the memory device in FIG.

[0021] Figure 17 Showing various aspects of the present disclosure Figure 14 A third alternative layout of portions or all of the various layers of the memory device in FIG.

[0022] Figure 18 According to various aspects of the present disclosure, Figure 1A 、 Figure 1B A circuit diagram of another memory cell implemented in an IC chip is shown. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the present disclosure below, forming another feature located on, connected to, and / or coupled to a feature may include embodiments in which the other feature is formed in direct contact, and may also include embodiments in which an insertion may be made within a feature to form an additional feature so that the features are not in direct contact. In addition, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” and the like, as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upward,” etc.), are used to simplify the relationship of one feature of the present disclosure to another. Spatially relative terms are intended to encompass different orientations of the device including the feature.

[0024] Furthermore, when "about," "approximately," etc., are used to describe a number or range of numbers, such terms are intended to encompass numbers within a reasonable range to account for variations inherent in manufacturing, as understood by those skilled in the art. For example, a number or range of numbers encompasses a reasonable range including the number (e.g., within + / - 10% of the number) based on known manufacturing tolerances associated with manufacturing features having the characteristic associated with the number. For example, a material layer having a thickness of "approximately 5 nanometers" may encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with depositing the material layer is known to those skilled in the art to be + / - 15%. Furthermore, the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0025] The IC manufacturing process flow can generally be divided into three categories: front-end-of-line (FEOL) processes, middle-end-of-line (MEOL) processes, and back-end-of-line (BEOL) processes. FEOL processes generally include processes associated with the fabrication of IC devices (e.g., transistors). For example, FEOL processes may include the formation of isolation features, gate structures, and source / drain features. Source / drain features may refer to either the source or the drain, individually or collectively, depending on the context. MEOL processes generally include processes associated with the fabrication of contacts to conductive features of the IC device (e.g., gate vias to the gate structure and / or source / drain contacts to the source / drain features). BEOL processes generally include processes associated with the fabrication of multi-layer interconnect structures that interconnect IC features fabricated via the FEOL and MEOL processes, thereby enabling the operation of the IC device. Features fabricated via FEOL processes may be referred to as FEOL features. Features fabricated via MEOL processes may be referred to as MEOL features. Features fabricated via BEOL processes may be referred to as BEOL features.

[0026] Multi-gate devices, such as fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). MBC transistors have a gate structure that partially or completely extends around the channel region to access the channel region on two or more sides. Because the gate structure of an MBC transistor surrounds the channel region, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed of nanowires, nanosheets, or other nanostructures, and therefore, an MBC transistor may also be referred to as a nanostructure transistor.

[0027] To achieve satisfactory functionality, a static random-access memory (SRAM) cell is electrically coupled to signal lines and power lines. For example, a dual-port SRAM cell formed of seven transistors (i.e., a 7T SRAM cell) is electrically coupled to signal lines, including a read port bit line R_BL, a read port word line R_WL, a write port bit line W_BL, a write port word line W_WL, and a power line configured to provide predetermined voltages VDD and VSS (referred to as a VDD line and a VSS line, respectively). In some prior art techniques, all of these signal and power lines, as well as associated landing pads, are formed in an interconnect layer disposed on the front side of the SRAM cell. In this disclosure, a pad generally refers to a metal line in an interconnect layer that provides an intermediate local interconnect for an SRAM cell, such as (1) an intermediate local interconnect between a device-level feature (e.g., gate or source / drain) and a bit line, bit line bar, word line, voltage line, or (2) an intermediate local interconnect between bit lines, word lines, or power lines. As described above, the rapid scaling of IC dimensions has resulted in densely spaced transistors, and therefore densely spaced BEOL features with reduced dimensions, which may result in increased parasitic resistance, increased parasitic capacitance, increased process risk, and / or reduced speed.

[0028] The present disclosure provides a memory device including a read port word line formed below the backside of an SRAM cell rather than above the frontside of the SRAM cell, thereby widening the process window and easing constraints on SRAM performance optimization. In one embodiment, the memory device includes a 7T SRAM cell having a write portion and a read portion; and a transistor in the read portion having a first source / drain feature coupled to the write portion, a second source / drain feature coupled to a read port bit line, and a gate structure electrically coupled to the read port word line. In a cross-sectional view, the read port bit line is disposed directly above the second source / drain feature, and the read port word line is disposed directly below the gate structure. Forming the read port word line below the gate structure frees up space that would otherwise be occupied by a front-side bonding pad for the front-side read port bit line, thereby increasing design flexibility for metal lines disposed above the SRAM cell. Forming the read port word line below the gate structure also enables formation of the read port bit line at the M0 level, thereby increasing the speed of the memory device.

[0029] The various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1A is a schematic plan view of an exemplary IC chip. Figure 1Bis a schematic plan view of a portion or the entirety of an array of memory cells (eg, static random access memory (SRAM) cells) according to various aspects of the present disclosure.

[0030] Figure 2 It is available in Figure 1A 、 Figure 1B Circuit diagram of a 7T SRAM cell implemented in an IC chip. Figure 3 Cross-sectional views illustrating portions or entirety of various layers of a memory device according to various aspects of the present disclosure are shown. Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 Different portions of the layout of a memory device 1000 having 7T SRAM cells according to various aspects of the present disclosure are shown. Figure 9 Showing the various aspects of the present disclosure along Figure 4 and Figure 6 1 is a cross-sectional view of a portion or the entirety of the memory device 1000 taken along line AA shown in FIG. Figure 10 Showing the various aspects of the present disclosure along Figure 9 FIG. 1 is a cross-sectional view of a portion or the entirety of the memory device 1000 taken along line BB shown in FIG. Figures 11 to 13 Alternative layouts of parts or all of a memory device according to various aspects of the present disclosure are shown. Figures 14 to 18 Each shows a partial or entire layout of various layers of another memory device 2000 according to various aspects of the present disclosure. Figure 18 According to various aspects of the present disclosure, Figure 1A 、 Figure 1B 1. A circuit diagram of another memory cell implemented in the IC chip shown. For the avoidance of doubt, the X-axis, Y-axis, and Z-axis in the figure are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, unless otherwise indicated, identical reference numerals denote identical features.

[0031] Reference Figure 1AThe present disclosure provides an IC chip 10 formed on a substrate and including at least an array 20 of memory cells. Array 20 may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. IC chip 10 may further include a plurality of other components, such as an array 30 of standard logic (STD) cells, configured to provide various standard logic devices (e.g., inverters, ANDs, NANDs, ORs, exclusive ORs, NORs, other suitable devices, or combinations thereof). Additionally, IC chip 10 may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, bipolar transistors, high voltage transistors, high frequency transistors, other suitable devices, or combinations thereof. Additional features may be added to IC chip 10, and some of the features described below may be replaced, modified, or deleted in other embodiments of IC chip 10.

[0032] In this embodiment, referring to Figure 1B , the array 20 includes a plurality of SRAM cells (e.g., SRAM cells 100A, 100B, 100C, and 100D) that generally provide a memory or storage capable of retaining data when powered. As such, the array 20 is hereinafter referred to as an SRAM array 20. The array 20 may also be referred to as a memory device 20 or a semiconductor structure 20. In the present disclosure, the memory device 20 may include one or more SRAM cells and a front-side interconnect layer and a back-side interconnect layer associated with the one or more SRAM cells. In the present embodiment, each of the SRAM cells 100A to 100D includes one or more GAA transistors, which will be discussed in detail below.

[0033] In this embodiment, still referring to Figure 1B, the SRAM cells 100A, 100B, 100C, and 100D, which collectively define a two-by-two grid, exhibit mirror and / or rotational symmetry relative to one another. For example, using SRAM cell 100C as a reference (denoted as "R0"), the layout of SRAM cell 100A (denoted as "MX") is a mirror image of the layout of SRAM cell 100C relative to the X-axis. Similarly, the layout of SRAM cell 100B is a mirror image of the layout of SRAM cell 100A, and the layout of SRAM cell 100D (denoted as "MY") is a mirror image of the layout of SRAM cell 100C, both relative to the Y-axis. In other words, the layout of SRAM cell 100B (denoted as "R180") is symmetrical to the layout of SRAM cell 100C by rotating 180 degrees about the geometric center of the grid, which is defined as the intersection of an imaginary line bisecting the rectangular grid along the Y-axis and an imaginary line bisecting the rectangular grid along the X-axis. Furthermore, in the illustrated embodiment, SRAM cells 100A-100D are substantially identical in size, i.e., have substantially identical cell widths S1 along the X-axis and substantially identical cell heights S2 along the Y-axis. Thus, for simplicity, each of SRAM cells 100A-100D may be referred to hereinafter as SRAM cell 100.

[0034] Figure 2An exemplary circuit diagram of a dual-port SRAM cell 100 including seven transistors (7T) is shown. The dual-port SRAM cell 100 includes a write port portion 100W. In this embodiment, the write port portion 100W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and channel gate transistors PG-1 and PG-2. In the illustrated embodiment, transistors PU-1 and PU-2 are P-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are N-type transistors. The drain of pull-up transistor PU-1 is coupled to the drain of pull-down transistor PD-1, and the drain of pull-up transistor PU-2 is coupled to the drain of pull-down transistor PD-2. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-1 and PD-1 are coupled together and coupled to the common drain of transistors PU-2 and PD-2 to form a storage node SN, and the gates of transistors PU-2 and PD-2 are coupled together and coupled to the common drain of transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to a power line configured to provide a first voltage VDD (this power line may be referred to as a VDD line), and the sources of pull-down transistors PD-1 and PD-2 are coupled to a power line configured to provide a second voltage VSS (this power line may be referred to as a VSS line), which may be electrically grounded in some embodiments.

[0035] Storage node SN of the data latch is coupled to bit line W_BL of write port portion 100W (which may be referred to as write bit line W_BL or write port bit line W_BLB) via channel-gate transistor PG-2, and complementary storage node SNB is coupled to complementary bit line W_BLB of write port portion 100W (which may be referred to as complementary write bit line W_BLB or complementary write port bit line W_BLB) via channel-gate transistor PG-1. Storage node SN and complementary storage node SNB are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of channel-gate transistor PG-1 and channel-gate transistor PG-2 are coupled to word line W_WL of write port portion 100W (which may be referred to as write word line W_WL or write port word line W_WL).

[0036] The dual-port SRAM cell 100 also includes a read port portion 100R coupled to the write port portion 100W. The read port portion 100R of the SRAM cell 100 includes a read port channel-gate transistor R-PG. One source / drain terminal of the read port channel-gate transistor R-PG is electrically coupled to the bit line R_BL of the read port portion 100R. The bit line of the read port portion 100R may be referred to as the read port bit line R_BL or the read bit line R_BL. The other source / drain terminal of the read port channel-gate transistor R-PG is electrically coupled to the storage node SN (or electrically coupled to the gate of transistor PU-1 and the gate of transistor PD-1). The gate of the read port channel-gate transistor R-PG is coupled to the word line R_WL of the read port portion 100R. The word line R_WL of the read port portion 100R may be referred to as the read word line R_WL or the read port word line R_WL. In the illustrated embodiment, transistor R-PG is a P-type transistor. That is, in the dual-port SRAM cell 100 , the channel gate transistors in the write port portion 100W are N-type transistors, and the channel gate transistors in the read port portion 100R are P-type transistors.

[0037] Figure 3 According to various aspects of the present disclosure, the semiconductor substrate (or wafer) 60 may be formed on or below the semiconductor substrate (or wafer) 60 to form, for example, Figure 1A 、 Figure 1B FIG. 1 is a partial schematic cross-sectional view of various layers (levels) of a portion of a memory device such as an IC chip 10. Figure 3 As shown in FIG, each layer includes: a device layer DL; a front-side multi-layer interconnect structure FMLI disposed above the device layer DL; and a back-side multi-layer interconnect structure BMLI disposed below the device layer DL.

[0038] The device layer DL includes devices (eg, transistors, resistors, capacitors, and / or inductors) and / or device components (eg, doped wells, gate structures, and / or source / drain features). Figure 3 In the illustrated embodiment, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, isolation features 64, and a transistor T. In the illustrated embodiment, the transistor T includes a suspended channel layer 70 disposed between source / drain features 72 and a gate structure 68, wherein the gate structure 68 wraps around and / or surrounds the suspended channel layer 70. Each gate structure 68 includes a metal gate stack formed by a gate electrode 74 disposed on a gate dielectric layer 76 and gate spacers 78 disposed along the sidewalls of the metal gate stack.

[0039] The multi-layer interconnect structures FMLI and BMLI electrically couple the various devices and / or components of the device layer DL, enabling the various devices and / or components to operate as dictated by the design requirements of the memory device. Each of the multi-layer interconnect structures FMLI and BMLI may include one or more interconnect layers. In the illustrated embodiment, the multi-layer interconnect structure FMLI includes a contact interconnect layer (CO layer), a via zero interconnect layer (V0 layer), a metal zero interconnect layer (M0 layer), a via one interconnect layer (V1 layer), a metal one interconnect layer (M1 layer), a via two interconnect layer (V2 layer), a metal two interconnect layer (M2 layer), a via three interconnect layer (V3 layer), and a metal three interconnect layer (M3 layer). Each of the CO level, V0 level, M0 level, V1 level, M1 level, V2 level, M2 level, V3 level, and M3 level may be referred to as a metal level. A metal line formed at the M0 level may be referred to as an M0 metal line. Similarly, vias or metal lines formed at the V1 level, M1 level, V2 level, M2 level, V3 level, and M3 level may be referred to as V1 vias, M1 metal lines, V2 vias, M2 metal lines, V3 vias, and M3 metal lines, respectively. The present disclosure contemplates a multi-layer interconnect structure FMLI having more or fewer interconnect layers and / or levels. For example, the total number of interconnect layers (levels) of the multi-layer interconnect structure FMLI is N, where N is an integer ranging from 1 to 10. Each level of the multilayer interconnect structure FMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and an etch stop layer (ESL)). The dielectric layers of the multilayer interconnect structure FMLI are collectively referred to as a dielectric structure 66. In some embodiments, the conductive features are formed simultaneously at the same level (e.g., the M0 level) of the multilayer interconnect structure FMLI. In some embodiments, the conductive features located at the same level of the multilayer interconnect structure FMLI have substantially coplanar top surfaces and / or substantially coplanar bottom surfaces.

[0040] exist Figure 3In the illustrated embodiment, the CO level includes source / drain contacts MD disposed in the dielectric structure 66. The source / drain contacts MD may be formed on and in direct contact with a silicide layer disposed directly on the source / drain features 72. The V0 level includes gate vias VG disposed on the gate structure and source / drain contact vias VD disposed on the source / drain contacts MD, wherein the gate vias VG connect the gate structure to the M0 metal line, and the source / drain vias V0 connect the source / drain contacts MD to the M0 metal line. In some embodiments, the V0 level may also include docking contacts disposed in the dielectric structure 66. The V1 level includes V1 vias disposed in the dielectric structure 66, wherein the V1 vias connect the M0 metal line to the M1 metal line. The M1 level includes the M1 metal line disposed in the dielectric structure 66. The V2 level includes V2 vias disposed in dielectric structure 66, wherein the V2 vias connect the M1 metal line to the M2 metal line. The M2 level includes M2 metal lines disposed in dielectric structure 66. The V3 level includes V3 vias disposed in dielectric structure 66, wherein the V3 vias connect the M2 metal line to the M3 metal line.

[0041] In the illustrated embodiment, the multi-layer interconnect structure BMLI includes a backside via zero interconnect layer (BV0 level), a backside metal zero level (BM0 level), a backside via one interconnect layer (BV1 level), and a backside metal one interconnect layer (BM1 level). Each of the BV0 level, the BMO level, the BV1 level, and the BM1 level may be referred to as a metal level. The metal line formed at the BM0 level may be referred to as a BM0 metal line. Similarly, the vias or metal lines formed at the BV0 level, the BV1 level, and the BM1 level may be referred to as BV0 vias, BV1 vias, and BM1 metal lines, respectively. The present disclosure contemplates a multi-layer interconnect structure BMLI having more or fewer interconnect layers and / or levels, for example, the total number of interconnect layers (levels) of the multi-layer interconnect structure BMLI is M, where M is an integer ranging from 1 to 10. Each level of the multi-layer interconnect structure BMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and an etch stop layer (ESL)). The dielectric layers of the multi-layer interconnect structure BMLI are collectively referred to as a dielectric structure 66'. In some embodiments, the conductive features located at the same level (e.g., the BM0 level) of the multi-layer interconnect structure BMLI are formed simultaneously. In some embodiments, the conductive features located at the same level of the multi-layer interconnect structure BMLI have substantially coplanar top surfaces and / or substantially coplanar bottom surfaces.

[0042] exist Figure 3In the illustrated embodiment, the BV0 level includes a via BV0 formed below the device layer DL. For example, the via BV0 may include one or more backside source / drain vias formed directly below the source / drain features of the device layer DL and coupled to the source / drain features via a silicide layer. The via BV0 may include one or more backside gate vias formed directly below the gate structure of the device layer DL and in direct contact with the gate structure of the device layer DL. The BM0 level includes a BM0 metal line formed below the BV0 level. The backside gate via connects the gate structure to the BM0 metal line, and the backside source / drain via connects the source / drain features to the BM0 metal line. The BV1 level includes a BV1 via disposed in the dielectric structure 66', wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 level includes the BM1 metal lines formed below the BV1 level.

[0043] For the sake of clarity, Figure 3 The simplification is done to better understand the inventive concepts of the present disclosure. Additional features may be added in the various layers of the memory, and some of the features described may be replaced, modified, or deleted in other embodiments of the memory. Figure 3 This is merely an example and may not reflect an actual cross-sectional view of the IC chip 10 and / or the memory device 1000 , which will be described in further detail below.

[0044] exist Figures 2 to 10In the illustrated embodiment, the SRAM cell 100 of the memory device 1000 is electrically coupled to a write port bit line W_BL, a complementary write port bit line W_BLB, a write port word line W_WL, a read port word line R_WL, a read port bit line R_BL, a VSS line, and a VDD line. In this embodiment, the write port bit line W_BL and the complementary write port bit line W_BLB are positioned at the M2 level, and various bonding pads are formed between the M2 level and the device layer DL to provide a conductive path. The write port word line W_WL is positioned at the M1 level, and various bonding pads are formed between the M1 level and the device layer DL to provide a conductive path. The VSS line, the VDD line, and the read port bit line R_BL are positioned at the M0 level, and various conductive features are provided at the CO level and the V0 level to provide a conductive path. In this embodiment, as described above, to relax the process window for forming the SRAM cell and the conductive features (e.g., bonding pads) formed on the SRAM cell, and to ease the constraints on optimizing SRAM performance, the read port word line R_WL is positioned below the device layer DL of the SRAM cell 100. Various bonding pads are formed between the read port word line and the device layer DL to provide a conductive path. That is, the read port word line R_WL is located below the backside of the SRAM cell 100, while other signal lines and power lines (e.g., the read port bit line R_BL, VSS line, VDD line, and associated bonding pads) are formed on the frontside of the SRAM cell 100.

[0045] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 Some embodiments of the present disclosure include Figure 2 A partial portion of the layout of a memory device 1000 of a dual-port SRAM cell 100 is shown. More specifically, Figure 4 FIG. 1 shows a partial portion of the layout of the device layer DL, CO level, and V0 level of the memory device 1000. Figure 5 FIG. 1 shows a partial portion of the layout of the V0 level and the M0 level of the memory device 1000 , Figure 6 FIG. 1 shows a partial portion of the layout of the device layer DL, BV0 level, BM0 level, BV1 level, and BM1 level of the memory device 1000 . Figure 7 shows a partial portion of the layout of the M0 level, V1 level, and M1 level of the memory device 1000, and Figure 8 A partial portion of the layout of the M1 level, V2 level, and M2 level of the memory device 1000 is shown. Figure 9 According to some embodiments of the present disclosure, Figure 4 and Figure 6A partial cross-sectional view of the memory device taken along line AA shown in FIG. Figure 10 According to some embodiments of the present disclosure, Figure 9 FIG. 1 is a partial cross-sectional view of the memory device taken along line BB shown in FIG.

[0046] First refer to Figure 4 At the device level DL, the dual-port SRAM cell 100 as part of the memory device 1000 includes a substrate 902 (eg, Figure 9 ) above the active regions 102 and 104. Figure 4 In the illustrated embodiment, active regions 102 and 104 each extend longitudinally along the X-axis and are separated by isolation features 904 (e.g., Figure 10 ) are spaced apart from each other along the Y-axis. In the present embodiment, the active region 102 is a three-dimensional fin-shaped active region (hereinafter referred to as N-type fin 102) disposed in a doped region or well (e.g., P-well, not shown) and configured to provide a channel region for an N-type transistor (e.g., a pull-down transistor or a channel gate transistor), and the active region 104 is a three-dimensional fin-shaped active region (hereinafter referred to as P-type fin 104) disposed in another doped region (e.g., N-well, not shown) and configured to provide a channel region for a P-type transistor (e.g., a pull-up transistor). In an embodiment, each of the N-type fin 102 and the P-type fin 104 includes a set of vertically stacked semiconductor layers (e.g., Figure 9 The semiconductor layer 908 shown in FIG.

[0047] Still refer to Figure 4 , the SRAM cell 100 also includes gate structures (e.g., gate structures 112, 114, 116, 118, and 120) that are oriented longitudinally along the Y axis and disposed on the N-type fin 102 and / or the P-type fin 104 to form various transistors. Each of the gate structures 112, 114, 116, 118, and 120 traverses the channel region of the N-type fin 102 and / or the channel region of the P-type fin 104. In the illustrated embodiment, reference is made to Figure 4As an example, gate structure 112 engages with N-type fin 102 to form channel gate transistor PG-1. Gate structure 114 engages with N-type fin 102 and P-type fin 104 to form pull-down transistor PD-1 and pull-up transistor PU-1, respectively. Gate structure 116 engages with N-type fin 102 and P-type fin 104 to form pull-down transistor PD-2 and pull-up transistor PU-2, respectively. Gate structure 118 engages with P-type fin 104 to form read port channel gate transistor R-PG. Gate structure 120 engages with N-type fin 102 to form channel gate transistor PG-2. In an embodiment, gate structure 118 and gate structure 120 are portions of a continuous gate structure similar to gate structures 114 / 116. To achieve the desired functionality, an isolation structure (e.g., Figure 10 ) to cut the continuous gate structure into two electrically and physically isolated portions (i.e., gate structures 118 and 120). That is, the sidewalls of gate structure 118 and gate structure 120 are aligned along the Y-axis. In this embodiment, the pull-up transistors PU-1, PU-2 and the read port channel gate transistor R-PG are P-type GAA transistors; the pull-down transistors PD-1 and PD-2 and the channel gate transistors PG-1 and PG-2 are N-type GAA transistors. The area utilization at the device layer DL of the SRAM cell 100 is considered to be efficient because only one unit area is not used to form functional transistors but to accommodate the intersection of the dielectric feature 110 and the active region. The boundary 190 of the dual-port SRAM cell 100 is shown using a dotted line. Note that at least some of the active regions 102 , 104 and the gate structures 112 , 114 , 116 , 118 , and 120 may extend beyond the illustrated boundary 190 , as these active regions and gate structures may also form components of other adjacently located SRAM cells.

[0048] Still refer to Figure 4Memory device 1000 includes conductive features formed at the CO level and the V0 level above SRAM cell 100. At the V0 level, a gate via 150C is formed on the gate structure 112 of channel-gate transistor PG-1 and is configured to electrically connect the gate structure 112 of channel-gate transistor PG-1 to a write port word line W_WL located at a higher metal level. A gate via 150D is formed on the gate structure 120 of channel-gate transistor PG-2 and is configured to electrically connect the gate structure 120 of channel-gate transistor PG-2 to a write port word line W_WL located at a higher metal level. A gate via 150E is formed on the gate structure 114 and electrically connects the gate structure 114 to a storage node (SN) located at a higher metal level. A gate via 150F is formed on the gate structure 116 and electrically connects the gate structure 116 to a complementary storage node (SNB) located at a higher metal level. Note that at the V0 level, there is no gate via formed directly on the gate structure 118 of the read port pass-gate transistor R-PG.

[0049] Still refer to Figure 4At the CO and V0 levels, source / drain contacts 160A and source / drain contact vias 170A strapping over source / drain contacts 160A electrically connect the source region of read-port channel-gate transistor R-PG to a read-port bit line R_BL located at a higher metal level. Memory device 1000 includes dummy source / drain contacts 160B adjacent to dielectric feature 110 and held electrically floating because no corresponding source / drain contact vias are strapped over them. Source / drain contacts 160C and source / drain contact vias 170C strapping over source / drain contacts 160C electrically connect the source region of channel-gate transistor PG-1 to a complementary write-port bit line (W_BLB) located at a higher metal level. Source / drain contact 160D and source / drain contact via 170D connected thereto electrically connect the source region of pass-gate transistor PG-2 to a write port bit line (W_BL) located at a higher metal level. Source / drain contact 160E and source / drain contact via 170E connected thereto electrically connect the shared drain region of pass-gate transistor PG-1 and pull-down transistor PD-1, as well as the drain region of pull-up transistor PU-1, to a complementary storage node (SNB) located at a higher metal level. Source / drain contact 160F and source / drain contact via 170F connected to source / drain contact 160F electrically connect the shared drain region of pass-gate transistor PG-2 and pull-down transistor PD-2, and the shared drain region of pull-up transistor PU-2 and read port pass-gate transistor R-PG, to a storage node (SN) located at a higher metal level. Source / drain contact 160G and source / drain contact via 170G connected to source / drain contact 160G electrically connect the shared source region of pull-down transistor PD-1 and pull-down transistor PD-2 to a VSS line located at a higher metal level. Source / drain contact 160H and source / drain contact via 170H connected to source / drain contact 160H electrically connect the shared source region of pull-up transistor PU-1 and pull-up transistor PU-2 to a VDD line located at a higher metal level. In the illustrated embodiment, each of the source / drain contacts 160A- 160H is elongated and has a longitudinal direction along the Y-axis that is parallel to the extension direction of the gate structures 112 - 120 .

[0050] Storage node SN includes a gate via 150E and a source / drain contact via 170F positioned on two opposite sides of gate structure 116. As will be described in further detail below, a metal line at the M0 level extends along the X-axis to connect gate via 150E and source / drain contact via 170F. In other words, the M0 metal line is suspended above gate structure 116 and provides a cross-coupling function between gate via 150E and source / drain contact via 170F. Therefore, in the layout, gate via 150E and source / drain contact via 170F are positioned flush along the Y-axis so that a metal line extending along the X-axis can connect the two. Similarly, a complementary storage node (storage node bar) SNB includes a gate via 150F and a source / drain contact via 170E positioned on two opposite sides of gate structure 114. As will be described in further detail below, another metal line at the M0 level extends across the gate structure 114 along the X-axis and connects the gate via 150F and the source / drain contact via 170E. In other words, the other M0 metal line is suspended above the gate structure 114 and provides a cross-coupling function between the gate via 150F and the source / drain contact via 170E. Therefore, in the layout, the gate via 150F and the source / drain contact via 170E are positioned flush along the Y-axis, allowing the metal line extending along the X-axis to connect them.

[0051] Now refer to Figure 5 , Figure 5 A portion of a layout including a V0 level and an M0 level of a memory device 1000 is shown. At the M0 level, the memory device 1000 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout, the memory device 1000 includes six metal tracks arranged sequentially along the Y-axis from a first track (M0 Track 1) to a sixth track (M0 Track 6). In the present disclosure, a metal line having a longitudinal dimension that is smaller than the dimension of the SRAM cell 100 (e.g., a dimension along the X-axis that is smaller than the cell width S1 and a dimension along the Y-axis that is smaller than the cell height S2) is referred to as a local metal line, and a metal line having a longitudinal dimension that is not smaller than the dimension of the SRAM cell 100 (e.g., a dimension along the X-axis that is smaller than the cell width S1 along the X-axis and a dimension along the Y-axis that is smaller than the cell height S2 along the Y-axis) is referred to as a global metal line.

[0052] like Figure 5 As shown in FIG. 1 , the first metal track "M0 Track 1" includes a global metal line 510 serving as a VSS line. The global metal line 510 is disposed above and electrically coupled to the source / drain contact via 170G. The VSS line is disposed on the upper edge of the boundary 190 of the SRAM cell 100 and can be shared by adjacent SRAM cells.

[0053] The second metal track "M0 Track 2" includes a local metal line 520 as a landing pad for the write port word line W_WL located at a higher metal level. In a top view, the local metal line 520 is completely within the boundary 190 of the SRAM cell 100. The local metal line 520 is disposed above and in direct contact with gate vias 150C and 150D.

[0054] The third metal track "M0 Track 3" includes three local metal lines 530A, 530B, and 530C. Local metal line 530A provides a landing pad for the complementary write port bit line W_BLB located at a higher metal level. In a top view, local metal line 530A extends beyond the left edge of the boundary 190 of the SRAM cell 100 and can be shared by adjacent SRAM cells. In a top view, local metal line 530B is completely within the boundary 190 of the SRAM cell 100. Local metal line 530B belongs to the storage node (SN) and provides cross-coupling between the gate via 150E and the source / drain contact via 170F. As described above, when viewed from the top, local metal line 530B crosses the gate structure 116. Local metal line 530C provides a landing pad for the write port bit line W_BL located at a higher metal level. In the top view, the local metal line 530C extends beyond the right edge of the boundary 190 of the SRAM cell 100 and may be shared by adjacent SRAM cells.

[0055] The fourth metal track, "M0 Track 4," includes a local metal line 540. In top view, local metal line 540 is located entirely within boundary 190 of SRAM cell 100 and belongs to the complementary storage node (SNB). It also provides cross-coupling between gate via 150F and source / drain contact via 170E. As described above, when viewed from the top, local metal line 540 intersects gate structure 114. Note that "M0 Track 4" has no other metal lines within boundary 190.

[0056] The fifth metal track "M0 Track 5" includes a global metal line 550 serving as a read port bit line R_BL, which is electrically coupled to the source / drain contact via 170A. In a top view, the read port bit line R_BL may extend beyond the left and / or right edges of the boundary 190 of the SRAM cell 100 and may be shared by adjacent SRAM cells. That is, the length of the read port bit line R_BL is equal to or greater than the cell width along the X-axis. By placing the read port bit line R_BL at the M0 level and configuring the read port bit line R_BL as a global metal line, the speed of the memory device 1000 can be advantageously increased. In addition, forming this read port bit line R_BL at the M0 level also avoids forming a small landing pad for the read port bit line R_BL, thereby alleviating overlap issues and reducing process risks.

[0057] The sixth metal track "M0 Track 6" includes a global metal line 560 serving as a VDD line electrically coupled to the source / drain contact via 170H. The VDD line is disposed directly above the bottom edge of the boundary 190 of the SRAM cell 100 and can be shared by adjacent SRAM cells.

[0058] In the depicted embodiment, the metal lines at the M0 level (e.g., local metal lines 520, 530A-530C, 540 and global metal lines 510, 550, 560) have longitudinal dimensions along the X-axis. The longitudinal dimensions of the local metal lines at the M0 level are smaller than the dimensions of the SRAM cell 100, for example, the dimension along the X-axis is smaller than the cell width S1 and the dimension along the Y-direction is smaller than the cell height S2. Compared to the local metal lines, the longitudinal dimensions of the VSS line (i.e., metal line 510), the read port bit line (i.e., metal line 550), and the VDD line (i.e., metal line 560) along the X-axis are equal to or greater than the cell width of the SRAM cell 100. Each of the metal lines 520, 530A-530C, 540, and 550 has the same width along the Y-axis, which is smaller than the widths of the VSS and VDD lines.

[0059] Now refer to Figure 6 , Figure 6A portion of the layout including the BV0, BM0, BV1, and BM1 levels of the memory device 1000 is shown. As described above, the gate structure 118 of the read port channel-gate transistor R-PG is electrically connected to the read port word line R_WL. In this embodiment, to increase design flexibility for the metal lines at the M0 level, improve the speed of the memory device, and mitigate leakage and overlap issues caused by forming a small landing pad on the device layer DL of the SRAM cell 100 rather than forming the read port word line R_WL and the landing pad for the read port word line R_WL above the device layer DL of the SRAM cell 100, the read port word line R_WL in this embodiment is positioned below the device layer DL of the SRAM cell 100. More specifically, at the BV0 level, a gate via 610 is formed directly beneath and in direct contact with the gate structure 118 of the read-port channel-gate transistor R-PG to electrically connect the gate structure 118 to the read-port word line R_WL located at a lower metal level. Gate via 610 may be referred to as backside gate via 610 or backside gate via BV0, and gate vias 150C, 150D, 150E, and 150F may be referred to as frontside gate vias 150C, 150D, 150E, and 150F, respectively. Backside gate via 610 has a width Wx along the X-axis and a width Wy along the Y-axis. The overlap area provided by backside gate via 610 is equal to the product of Wx and Wy (i.e., Wx*Wy). The N-type fin 102 has a width D1 along the Y-axis, and the P-type fin 104 has a width D2 along the Y-axis. In some embodiments, width D1 is substantially equal to width D2. In some embodiments, a ratio of width Wx to width Wg of gate structure 118 along the X-axis is in a range between approximately 0.5 and 1.5. In some embodiments, a ratio of width Wy to width D2 is in a range between approximately 0.5 and 1.5.

[0060] Still refer to Figure 6, at the BM0 level, the memory device 1000 includes a local metal line 620, the local metal line 620 providing a landing pad for the read port word line R_WL, the local metal line 620 being disposed below and in direct contact with the backside gate via 610 and configured to electrically couple the backside gate via 610 to the read port word line R_WL positioned at a lower metal level. In the present embodiment, the local metal line 620 extends longitudinally along the X-axis. In a top view, the local metal line 620 is entirely within the boundary 190 of the SRAM cell 100. The local metal line 620 has a width D3 along the Y-axis and a length L3 along the X-axis. In some embodiments, to provide reduced resistance, the ratio of the width D3 to the width D2 is in a range between approximately 1 and 3, and to provide reduced capacitance associated with the read port word line, the ratio of the length L3 to the width Wg (i.e., L3 / Wg) is in a range between approximately 2 and 10. In Figure 6 In the illustrated embodiment, when viewed from the top, local metal line 620 intersects gate structures 118, 116, and 114, and thus intersects centerline 100c of SRAM cell 100 along the Y-axis. Centerline 100c divides SRAM cell 100 into two portions having the same shape and area. In one embodiment, the distance between centerline 100c and gate structure 114 is equal to the distance between centerline 100c and gate structure 116. Local metal line 620 may be referred to as backside local metal line 620 or metal line BM0, and local metal lines formed above device layer DL may be referred to as frontside local metal lines. Local metal line 620 intersects centerline 100c of SRAM cell 100 to provide a landing area for the read port wordline R_WL, which is positioned in the middle of SRAM cell 100 when viewed from the top.

[0061] At the BV1 level, a via 630 is formed below the local metal line 620 and in direct contact with the local metal line 620 to electrically connect the local metal line 620 to the read port word line R_WL located at a lower metal level. The via 630 may be referred to as a backside via 630 or a backside via BV1.

[0062] At the BM1 level, the memory device 1000 includes a global metal line 640 serving as a read port word line R_WL. The global metal line 640 is disposed below and in direct contact with the via 630 and is electrically coupled to the gate structure 118. The global metal line 640 may also be referred to as a backside metal line BM1. In a top view, the read port word line R_WL may extend beyond the upper and / or lower edges of the boundary of the SRAM cell 100 and may be shared by adjacent SRAM cells. That is, the length of the read port word line R_WL is equal to or greater than the cell height S2 along the Y-axis. In some embodiments, to provide satisfactory parasitic resistance and parasitic capacitance, the ratio of the width D4 of the global metal line 640 to the width Wg (i.e., D4 / Wg) is in a range between approximately 2 and 10. In this embodiment, when viewed from the top, the read port word line R_WL (i.e., the global metal line 640) is positioned in the middle of the boundary of the SRAM cell 100. That is, the center line of the read port word line R_WL along the Y axis is aligned with the center line 100c of the SRAM cell. Figures 9 to 10 The cross-sectional view of memory device 1000 shown in FIG1 illustrates in greater detail vias 610 and 630 and metal lines 620 and 640. Forming the read port word line R_WL and associated bonding pads (e.g., local metal line 620) at the backside of the SRAM cell 100 reduces the density of metal lines formed at the M0 level and thus increases design flexibility.

[0063] Now refer to Figure 7 , Figure 7A portion of a layout including the M0, V1, and M1 levels of memory device 1000 is shown. At the V1 level, memory device 1000 includes a plurality of vias formed above and in direct contact with the M0 level. For example, the V1 level of memory device 1000 includes via 710A formed above and in direct contact with local metal line 530A to electrically couple local metal line 530A to a complementary write port bit line W_BLB located at a higher interconnect layer. The V1 level of memory device 1000 also includes via 710B formed above and in direct contact with local metal line 520 to electrically couple local metal line 520 to a write port word line W_WL located at a higher metal level. The V1 level of memory device 1000 also includes a via 710C formed above and in direct contact with global metal line 510, electrically connecting global metal line 510 to a metal line located at a higher metal level. The V1 level of memory device 1000 also includes a via 710E formed above and in direct contact with local metal line 530C, electrically connecting local metal line 530C to a write port bit line W_BL located at a higher metal level.

[0064] At the M1 level, memory device 1000 includes a plurality of metal lines formed above the V1 level. For example, the M1 level of memory device 1000 includes a local metal line 720A. Local metal line 720A is formed above and in direct contact with via 710A to electrically couple via 710A to a complementary write port bit line W_BLB located at a higher metal level. Local metal line 720A may also be referred to as a landing pad for the complementary write port bit line W_BLB. Local metal line 720A may extend beyond the left edge of boundary 190 of SRAM cell 100 and may be shared by adjacent SRAM cells.

[0065] The M1 level of memory device 1000 also includes a global metal line 720B serving as a write port word line W_WL. Global metal line 720B is disposed above and electrically coupled to via 710B. Write port word line W_WL may extend beyond the upper and / or lower edges of boundary 190 of SRAM cell 100 and may be shared between adjacent SRAM cells. The M1 level of memory device 1000 also includes a global metal line formed above and in direct contact with via 710C. The M1 level of memory device 1000 also includes a global metal line 720D disposed adjacent to global metal line 720C. The M1 level of the memory device 1000 also includes a local metal line 720E. The local metal line 720E is formed above the through-hole 710E and directly contacts the through-hole 710E to electrically couple the through-hole 710E to the write port bit line W_BL located at a higher metal level. The local metal line 720E can also be referred to as a landing pad for the write port bit line W_BL. The local metal line 720E can extend beyond the right edge of the boundary 190 of the SRAM cell 100 and can be shared by adjacent SRAM cells. Figure 7 As shown in FIG. 1 , in a top view, all metal lines at the M1 level (including global metal lines 720B, 720C, 720D and local metal lines 720A, 720E) extend longitudinally along the Y-axis.

[0066] Now refer to Figure 8 , Figure 8 A portion of a layout including the M1 level, the V2 level, and the M2 level of memory device 1000 is shown. At the V2 level, memory device 1000 includes a plurality of vias formed above the M1 level. For example, the V2 level of memory device 1000 includes via 810A, which is formed above and directly contacts local metal line 720A to electrically couple local metal line 720A to a complementary write-port bit line W_BLB located at a higher metal level. The V2 level of memory device 1000 also includes via 810B, which is formed above and directly contacts local metal line 720E to electrically couple local metal line 720E to a write-port bit line W_BL located at a higher metal level.

[0067] At the M2 level, memory device 1000 includes a plurality of metal lines formed above the V2 level. In this embodiment, memory device 1000 includes a global metal line 820A serving as a complementary write port bit line W_BLB. Global metal line 820A is formed above and in direct contact with via 810A. Memory device 1000 also includes a global metal line 820B serving as a write port bit line W_BL. Global metal line 820B is formed above and in direct contact with via 810B. Both write port bit line W_BL and complementary write port bit line W_BLB extend longitudinally along the X-axis, may extend beyond the left and / or right edges of boundary 190 of SRAM cell 100, and may be shared by adjacent SRAM cells.

[0068] Compared to embodiments in which the read port word line R_WL is formed above the device layer DL of the SRAM cell, forming the read port word line R_WL below the device layer DL of the SRAM cell can relax the design flexibility of the metal lines formed at the M0 level. Furthermore, forming the read port bit line R_BL at the M0 level can also relax the metal lines at other metal levels (e.g., the M2 level). Therefore, in this embodiment, the complementary write port bit line W_BLB and the write port bit line W_BL formed at the M2 level can have increased widths, thereby reducing parasitic resistance and improving write speed.

[0069] Figure 9 According to some embodiments of the present disclosure, Figure 4 and Figure 6 1 is a cross-sectional view of the memory device 1000 taken along line AA shown in FIG. Figure 10 According to some embodiments of the present disclosure, Figure 9 The cross-sectional view of the memory device 1000 cut through the N-type fin 102 and the gate structures 112, 114, 116 and 120 is similar to the cross-sectional view of the memory device 1000. Figure 9 FIG. 1 is a cross-sectional view of the memory device 1000 shown in FIG. 1 and repeated description is omitted for brevity.

[0070] like Figures 9 and 10As shown, SRAM cell 100 (as part of memory device 1000) is formed on substrate (or wafer) 902. In one embodiment, substrate 902 comprises silicon. Depending on the design requirements of memory device 1000, substrate 902 includes a plurality of p-wells (not shown) and n-wells (not shown) formed in (and / or on) substrate 902. The n-well is configured to provide at least one p-type field-effect transistor (PFET) (e.g., a pull-up transistor), and the p-well is configured to provide at least one n-type field-effect transistor (NFET) (e.g., a pull-down transistor or a channel-gate transistor). In some embodiments, substrate 902 may include additional doped regions configured to provide one or more transistors depending on the design requirements of memory device 1000.

[0071] exist Figures 9 and 10In the illustrated embodiment, the transistors of the SRAM cell 100 (e.g., pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and channel-gate transistors PG-1, PG-2, and R-PG) comprise GAA transistors. The P-type fin 104 comprises a stack of a semiconductor layer 908 and a portion of the substrate 902 located below the semiconductor layer 908. Similarly, the N-type fin 102 comprises a stack of a semiconductor layer and a portion of the substrate 902 located below the semiconductor layer. In the illustrated embodiment, the semiconductor layers 908 are stacked vertically along the Z-axis. Each stack of semiconductor layers 908 for the P-type fin 104 is interposed within a P-type source / drain (S / D) feature 910P, and each stack of semiconductor layers for the N-type fin 102 is interposed within an N-type source / drain (S / D) feature (not shown). The semiconductor layer 908 may comprise Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof. In this embodiment, each of the semiconductor layers 908 comprises a nanosheet, a nanowire (e.g., a nanowire having a hexagonal cross-section), a nanorod (e.g., a nanorod having a square or circular cross-section), or other suitable configurations. In some embodiments, the N-type fin 102 and the P-type fin 104 each include two to ten channel layers 908. For example, the N-type fin 102 and the P-type fin 104 may each include three channel layers 908. Of course, the present disclosure is not limited to this configuration, and the number of semiconductor layers may be adjusted according to the design requirements of the memory device 1000. Source / drain features may be referred to individually or collectively as source or drain, depending on the context. Exemplary N-type source / drain features may comprise silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be doped in situ during the epitaxial process by introducing an N-type dopant (e.g., phosphorus, arsenic, or antimony) or ex situ using a junction implantation process. Exemplary P-type source / drain features 910P may comprise germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be doped in situ during the epitaxial process by introducing a P-type dopant (e.g., boron or gallium) or ex situ using a junction implantation process. In some embodiments, each of the N-type source / drain features and / or the P-type source / drain features 910P may be a multi-layer structure comprising: an undoped semiconductor layer; a lightly doped semiconductor layer disposed above the undoped semiconductor layer; and a heavily doped semiconductor layer disposed above the lightly doped semiconductor layer.

[0072] In this embodiment, each gate structure (including gate structures 112, 114, 116, 118, 120) includes at least a high-k gate dielectric layer (eg, Figure 3 ) and a metal gate electrode (e.g., a gate dielectric layer 76 shown in FIG. Figure 3). In this embodiment, portions of the high-k gate dielectric layer wrap around each channel layer so that each gate structure is bonded to the multiple channel layers (e.g., channel layer 908) in each GAA transistor. The high-k gate dielectric layer may include silicon oxynitride, aluminum silicon oxide, a high-k dielectric material (e.g., hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials, or combinations thereof. Although not shown, each metal gate electrode may further include a bulk conductive layer disposed above at least one work function metal layer. The bulk conductive layer may include Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof. In some examples, each gate structure may include one or more work function metal layers of the same conductivity type or different conductivity types. Examples of work function metal layers may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. Each work function metal layer may be deposited first and then patterned to meet the different threshold voltage requirements for different GAAFETs. Each gate structure may also include additional material layers, such as an interface layer, a barrier layer, a cap layer, other suitable material layers, or combinations thereof. The various layers of the gate structure may be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plating, other suitable methods, or combinations thereof. The SRAM cell 100 may further include top spacers 912a and 912b and an inner spacer 912c disposed on the sidewalls of the gate structure, wherein the top spacers 912a and 912b are disposed above the channel layer 908 and the inner spacer 912c is disposed in the space between two vertically stacked channel layers 908. Figure 9As shown in FIG, 7T SRAM cell 100 also includes a dielectric feature 110. Dielectric feature 110 can be formed in a continuous-poly-on-diffusion-edge (CPODE) process. In the CPODE process, at least a portion of the polysilicon gate and the channel region underlying the at least a portion are replaced with a dielectric feature, and the remaining portion of the polysilicon gate can be replaced with a functional gate structure. For the purposes of this disclosure, a "diffusion edge" may equivalently be referred to as an active edge, where, for example, the active edge abuts an adjacent active region. Dielectric feature 110 is also referred to as CPODE feature 110. CPODE feature 110 extends into substrate 902.

[0073] Still refer to Figures 9 and 10 Memory device 1000 includes a contact etch stop layer (CESL) 914 and a first interlayer dielectric (ILD) layer 916 deposited over P-type source / drain features 910P. CESL 914 may include silicon nitride, silicon oxynitride, and / or other suitable materials and may be formed via ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. First ILD layer 916 may be deposited after CESL 914 is deposited via PECVD or other suitable deposition techniques. The first ILD layer 916 may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxides such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The memory device 1000 also includes an etch stop layer 918 and a second interlayer dielectric (ILD) layer 920 deposited over the first ILD layer 916 and the gate structures (including the gate structures 112, 114, 116, 118, and 120). The formation and composition of the etch stop layer 918 and the second ILD layer 920 are similar to the formation and composition of the CESL 914 and the first ILD layer 916, respectively.

[0074] Still refer to Figure 9 and 10Memory device 1000 includes source / drain contacts (including source / drain contacts 160E, 160H, 160F, 160A) extending through etch stop layer 918, first and second ILD layers 916, 920, and CESL 914. Each of the front-side source / drain contacts (including source / drain contacts 160E, 160H, 160F, 160A) is formed over a corresponding source / drain feature and is electrically coupled to a corresponding source / drain feature 910P via silicide layer 922. The source / drain contacts (including source / drain contacts 160E, 160H, 160F, and 160A) may include any suitable conductive material, such as Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof, and may further include a barrier layer comprising any suitable material, such as Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. In some embodiments, the silicide layer 922 may include nickel silicide, titanium silicide, cobalt silicide, other suitable silicides, or combinations thereof.

[0075] In order to increase the design flexibility of the metal lines at the M0 level and alleviate the leakage and overlap problems, the read port word line R_WL of the memory device 1000 is set below the SRAM cell 100. Figures 9 and 10 As shown in FIG, the memory device 1000 includes a gate through hole 610 disposed below and in direct contact with the gate structure 118 of the read port channel gate transistor R-PG of the SRAM cell 100. The gate through hole 610 is separated from the substrate 902 by a dielectric liner 915. In some embodiments, the dielectric liner 915 may include silicon nitride or other suitable materials. Figure 10 In the illustrated embodiment, the backside gate via 610 is in direct contact with both the gate structure 118 and the channel region of the P-type fin 104 disposed directly below the gate structure 118 .

[0076] Memory device 1000 includes a backside local metal line 620 serving as a landing pad for a read port word line R_WL. Backside local metal line 620 is disposed beneath substrate 902 and in direct contact with backside gate via 610. Backside local metal line 620 is embedded in dielectric layer 930 and separated from substrate 902 by an etch stop layer 928. Dielectric layer 930 and etch stop layer 928 are similar to second ILD layer 920 and etch stop layer 918, respectively.

[0077] Memory device 1000 includes an etch stop layer 938 and a dielectric layer 940 disposed below backside local metal line 620. Dielectric layer 940 and etch stop layer 938 are similar to second ILD layer 920 and etch stop layer 918, respectively. Backside via 630 extends through dielectric layer 940 and etch stop layer 938 and is electrically connected to and in direct contact with backside local metal line 620.

[0078] Memory device 1000 also includes an etch stop layer 948 and a dielectric layer 950 disposed below backside via 630. Dielectric layer 950 and etch stop layer 948 are similar to second ILD layer 920 and etch stop layer 918, respectively. Global metal line 640, serving as read port word line R_WL, extends through dielectric layer 950 and etch stop layer 948 and is electrically connected to and in direct contact with backside via 630. Because backside local metal line 620 and read port word line R_WL are formed below SRAM cell 100 rather than above it, the dimensions of backside local metal line 620 and read port word line R_WL can be flexibly adjusted to achieve satisfactory performance. That is, the parasitic capacitance and parasitic resistance of the memory device 1000 can be optimized by adjusting the dimensions (eg, width, thickness) of the backside local metal lines 620 and the dimensions (eg, width, thickness) of the read port word lines R_WL.

[0079] Figure 11 A first alternative layout of a portion or the entire memory device 1000 according to various aspects of the present disclosure is shown. Figure 6 and Figure 9 In the above described embodiment, the backside gate via 610 is directly disposed below the channel region of the P-type fin 104 and in direct contact with the gate structure 118. Figure 11 In the alternative embodiment shown, the backside gate via 610 is directly disposed below and in direct contact with the gate structure 118 and does not overlap with the P-type fin 104 in the vertical direction. Figure 10 As shown by the dashed line 1100 in FIG, in an alternative embodiment, the backside gate via 610 may extend through the STI feature 904 to contact the gate structure 118 and be disposed between two adjacent fins (e.g., the N-type fin 102 and the P-type fin 104). In some other embodiments, the backside gate via 610 may overlap both the STI feature 904 and the channel region of the P-type fin 104 in a vertical direction. That is, in a cross-sectional view, the backside gate via 610 may extend through both the channel region of the P-type fin 104 and the STI feature 904 to directly contact the gate structure 118, as shown in FIG. Figure 10 As shown by the dotted line 1100'.

[0080] Figure 12 A second alternative layout of part or all of the memory device 2000 according to various aspects of the present disclosure is shown. Figure 6 In the embodiment described above, global metal line 640 (i.e., read port word line R_WL) is positioned at the BM1 level and electrically coupled to the gate structure 118 of the read port channel-gate transistor R-PG via backside gate vias 610 formed at the BV0 level, local metal lines 620 formed at the BV0 level, and backside vias 630 formed at the BV1 level. In this alternative embodiment, global metal line 640′, serving as read port word line R_WL, is positioned at the BMO level, extends longitudinally along the Y-axis, and is electrically coupled to the gate structure 118 of the read port channel-gate transistor R-PG via backside gate vias 610 formed at the BMO level. In this alternative embodiment, there is an offset between the centerline of global metal line 640′ (i.e., read port word line R_WL) and the centerline 100c of the SRAM cell 100.

[0081] Figure 13 A third alternative layout of part or all of memory device 1000 according to various aspects of the present disclosure is shown. Figure 13 The third alternative layout of the memory device 2000 shown in FIG. Figure 12 . That is, in the third alternative embodiment, a global metal line 640″ serving as the read port word line R_WL is positioned at the BMO level and electrically coupled to the gate structure 118 of the read port channel-gate transistor R-PG via a backside gate via 610 formed at the BMO level. Figure 12 and Figure 13 One difference between the two layouts depicted in includes the shape of the read port word line R_WL. More specifically, in the third alternative embodiment, the global metal line 640" includes a first portion 640a" extending longitudinally along the Y-axis, and when viewed from the top, the centerline of the first portion 640a" is aligned with the centerline 100c of the SRAM cell. In some embodiments, the length of the first portion 640a" is not less than the cell height of the SRAM cell 100 along the Y-axis. The global metal line 640" also includes a second portion 640b" protruding from the first portion 640a" and extending longitudinally along the X-axis. The backside gate via 610 is disposed directly above and in direct contact with the second portion 640b". The second portion 640b" has a width D5 along the Y-axis and a length D6 along the X-axis. In some embodiments, the ratio of width D5 to width D2 (ie, D5 / D2) is in a range between about 0.5 and 5, and the ratio of length D6 to width Wg (ie, D6 / Wg) is in a range between about 1 and 5. Figures 10 and 11As described above, the backside gate via 610 may directly contact the P-type fin 104, the STI feature 904, or both. Forming this global metal line 640" enables the first portion 640a" to be disposed under the center of the SRAM cell 100, thereby reducing parasitic capacitance.

[0082] Figure 14 FIG. 2 shows a partial or overall layout of various layers of another memory device 2000 according to various aspects of the present disclosure. Figure 14 As shown in FIG. 1 , the memory device 2000 includes two SRAM cells. For example, the memory device 2000 includes an SRAM cell 100A and an SRAM cell 100C. The layout of the SRAM cell 100A is substantially the same as that of the reference cell 100. Figure 4 The layout of the illustrated SRAM cell 100 is identical, and the layout of the SRAM cell 100C is a mirror image of the layout of the SRAM cell 100A with respect to the X-axis. The SRAM cell 100C includes pull-up transistors PU-1′ and PU-2′, pull-down transistors PD-1′ and PD-2′, channel-gate transistors PG-1′ and PG-2′, and read port channel-gate transistor R-PG′ formed by gate structures 112′, 114′, 116′, 118′, and 120′ and N-type fins 102′ and P-type fins 104′, and has a cell boundary 190′. Unless otherwise specified, identical reference numerals (e.g., 112′ and 112) denote identical elements, and repeated descriptions are omitted for brevity.

[0083] The memory device 2000 includes a backside gate via 610 disposed under the gate structure 118 of the SRAM cell 100A; a local metal line 620 disposed under and in direct contact with the backside gate via 610; and a backside via 630 disposed under and in direct contact with the local metal line 620, as described above with reference to FIG. Figure 6 As described. Similarly, Figure 14As shown, memory device 2000 also includes a backside gate via 610' disposed beneath gate structure 118' of SRAM cell 100C; a local metal line 620' disposed beneath and in direct contact with backside gate via 610'; and a backside via 630' disposed beneath and in direct contact with local metal line 620'. Backside gate via 610', local metal line 620', and backside via 630' are substantially identical to backside gate via 610, local metal line 620, and backside via 630, respectively. Memory device 2000 also includes a global metal line 640 serving as a read port word line R_WL. Global metal line 640 is disposed beneath SRAM cell 100A and SRAM cell 100C and extends longitudinally along the Y-axis to cross cell boundary 190 and cell boundary 190'. In this embodiment, the read port word line R_WL is in direct contact with both the backside via 630′ and the backside via 630 to be electrically coupled to the gate structure 118 of the read port channel-gate transistor R-PG of the SRAM cell 100A and the gate structure 118′ of the read port channel-gate transistor R-PG′ of the SRAM cell 100C.

[0084] Figure 15 Showing various aspects of the present disclosure Figure 14 A first alternative layout of portions or the entirety of the various layers of the memory device 2000 in FIG. Figure 15 The first alternative layout shown in FIG is similar to Figure 14 One difference between the two layouts includes, Figure 15 As shown in FIG, memory device 2000 includes a backside gate via 610S disposed below and in direct contact with both the gate structure 118 of the read-port channel-gate transistor R-PG of SRAM cell 100A and the gate structure 118' of the read-port channel-gate transistor R-PG' of SRAM cell 100C. That is, backside gate via 610S is shared by both SRAM cells 100A and 100C. Backside gate via 610S has a first portion that vertically overlaps with local metal line 620, a second portion that vertically overlaps with local metal line 620', and a third portion that does not vertically overlap with either local metal line 620 or local metal line 620'. In some embodiments, a ratio of length Wy' to width D2 of backside gate via 610S is within a range between approximately 0.5 and approximately 10.

[0085] Figure 16 Showing various aspects of the present disclosure Figure 14 A second alternative layout of portions or the entirety of the various layers of the memory device 2000 in FIG. Figure 16 The second alternative layout shown in Figure 15 One difference between the two layouts includes, Figure 16 As shown in FIG, instead of having two local metal lines (e.g., local metal lines 620 and 620′), the memory device 2000 includes a local metal line 620S disposed under the backside gate via 610S. The local metal line 620S vertically overlaps both the SRAM cell 100A and the SRAM cell 100C. Another difference between the two layouts includes, for example, Figure 16 As shown in FIG, instead of having two backside vias (e.g., backside vias 630 and 630′), the memory device 2000 includes a backside via 630S disposed below the local metal line 620S and vertically overlapping both the SRAM cell 100A and the SRAM cell 100C. That is, the global metal line 640 (i.e., the read port word line R_WL) is electrically coupled to the gate structure 118 of the SRAM cell 100A and the gate structure 118′ of the SRAM cell 100C via a common backside via (i.e., backside via 630S) at the BV1 level, a common local metal line (i.e., local metal line 620S) at the BMO level, and a common backside gate via (i.e., backside gate via 610S) at the BV0 level.

[0086] Figure 17 Showing various aspects of the present disclosure Figure 14 A third alternative layout of portions or all of the various layers of the memory device 2000 in FIG. Figure 17 The third alternative layout shown in Figure 16 One difference between the two layouts includes, Figure 17 As shown in FIG, instead of having one common backside gate via 610S, the memory device 2000 includes reference Figure 14 That is, the global metal line 640 (i.e., the read port word line R_WL) is electrically coupled to the gate structure 118 of the SRAM cell 100A and the gate structure 118' of the SRAM cell 100C via a common backside via (i.e., the backside via 630S at the BV1 level), a common local metal line at the BMO level (i.e., the local metal line 620S), and two corresponding backside gate vias at the BV0 level (i.e., the backside gate vias 610 and 610').

[0087] In reference Figures 2 to 17 In the above embodiments, the structure of the memory device 1000 / 2000 including a 7T SRAM cell is described. The concepts of the present invention (e.g., forming a read port word line R_WL at the back side of the SRAM cell) are also applicable to a memory device including a dual-port SRAM cell having eight transistors (8T). Figure 18According to various aspects of the present disclosure, Figure 1A 、 Figure 1B A circuit diagram of an 8T SRAM cell 100' implemented in an IC chip is shown. The 8T SRAM cell 100' is similar to the 7T SRAM cell 100, with one difference between the two SRAM cells being that the 8T SRAM cell 100' includes an additional read port channel gate transistor, R-PG2. The read port word line, R_WL, of a memory device including the 8T SRAM cell 100' can be formed below the device layer of the 8T SRAM cell 100'.

[0088] One or more embodiments of the present disclosure provide numerous benefits to memory devices and their formation, but are not intended to be limiting. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need be disclosed herein, and not all embodiments require specific advantages. For example, the present disclosure provides a memory device comprising an SRAM cell and a read port word line disposed beneath the SRAM cell. Forming a read port word line disposed beneath the SRAM cell relaxes the design flexibility of front-side conductive features (e.g., metal lines) formed above the SRAM cell and alleviates leakage and short circuit issues associated with the front-side conductive features. In some embodiments, forming a read port word line disposed beneath the SRAM cell enables the parasitic capacitance and parasitic resistance of the memory device to be reduced, thereby improving overall performance.

[0089] The present disclosure provides a number of different embodiments. Disclosed herein are semiconductor structures and methods for making the same. In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a dual-port static random access memory (SRAM) cell, the dual-port SRAM cell including a write port portion and a read port portion, the read port portion electrically coupled to the write port portion and including a transistor having a gate structure. The semiconductor structure also includes: a first plurality of metal lines including a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first interconnect layer disposed above the gate structure; and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, wherein the second interconnect layer is disposed below the gate structure.

[0090] In some embodiments, the semiconductor structure may also include: a first through-hole disposed below and in direct contact with the gate structure; a strapping pad disposed directly below and in direct contact with the first through-hole; and a second through-hole disposed directly below and in direct contact with the strapping pad. A second interconnect layer is disposed below and in direct contact with the second through-hole. In some embodiments, the first through-hole may overlap with the channel region of the transistor in a vertical direction. In some embodiments, the first through-hole may not overlap with the channel region of the transistor in a vertical direction. In some embodiments, the strapping pad extends longitudinally along a first direction, and the gate structure extends longitudinally along a second direction substantially perpendicular to the first direction. In some embodiments, the transistor may also include a first source / drain feature electrically coupled to a write port portion and a second source / drain feature electrically coupled to a read bit line, and the read bit line may be positioned at a third interconnect layer disposed above the gate structure. In some embodiments, the semiconductor structure may also include: a silicide layer disposed over and in direct contact with the second source / drain feature; and a source / drain contact disposed over and in direct contact with the silicide layer, wherein a third interconnect layer may be disposed over and in direct contact with the source / drain contact. In some embodiments, the transistor may also include vertically stacked nanostructures, and the gate structure may include a first portion and a second portion, the first portion being disposed over the vertically stacked nanostructures and the second portion wrapping around each of the vertically stacked nanostructures. In some embodiments, the gate structure and the read word line extend longitudinally in the same direction.

[0091] In another exemplary aspect, the present disclosure relates to a semiconductor structure comprising: a memory cell connected to a write word line and a read word line; a first interconnect structure disposed above the memory cell and including the write word line; and a second interconnect structure disposed below the memory cell and including the read word line.

[0092] In some embodiments, a memory cell may include: a first active region and a second active region extending longitudinally along a first direction; and a first gate structure and a second gate structure extending longitudinally in a second direction perpendicular to the first direction, wherein the first gate structure is bonded to the first active region to form an N-type transistor, and the first gate structure is electrically coupled to a write word line, and wherein the second gate structure is bonded to the second active region to form a P-type transistor, and the second gate structure is electrically coupled to a read word line. In some embodiments, the P-type transistor may also include a first source / drain feature and a second source / drain feature, the first source / drain feature being electrically coupled to a read bit line, and the second source / drain feature being electrically coupled to a source / drain feature of the N-type transistor, and wherein the first interconnect structure may include: a source / drain contact disposed above the first source / drain feature; and a read bit line disposed above and in direct contact with the source / drain contact. In some embodiments, the second interconnect structure may include: a first via disposed beneath and in direct contact with the second gate structure; a strapping pad disposed directly beneath and in direct contact with the first via; a second via disposed directly beneath and in direct contact with the strapping pad; and a read word line disposed directly beneath and in direct contact with the second via. In some embodiments, the first via may be disposed directly beneath a channel region of the P-type transistor. In some embodiments, the memory cell may also include an isolation feature configured to isolate the first active region from the second active region, and the first via extends through the isolation feature to directly contact the second gate structure. In some embodiments, the memory cell may include a seven-transistor static random access memory (SRAM) cell.

[0093] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first memory cell, the first memory cell including a write port portion; and a read port portion including a transistor and a gate structure, the transistor having first and second source / drain features coupled to a channel region, the gate structure being bonded to the channel region. The semiconductor structure also includes a backside via directly beneath and in direct contact with the gate structure; and a first interconnect layer beneath and electrically coupled to the backside via, wherein a read word line is positioned at the first interconnect layer.

[0094] In some embodiments, the first memory cell can be connected to a first power line for receiving a first power supply voltage and a second power line for receiving a second power supply voltage, wherein the first power line and the second power line are located at a second interconnect layer disposed above the gate structure. In some embodiments, one of the first source / drain feature and the second source / drain feature can be electrically coupled to a read bit line, and the read bit line can be located at the second interconnect layer. In some embodiments, the semiconductor structure can also include a second memory cell, wherein the backside via can further directly contact the gate structure of a transistor in a read port portion of the second memory cell.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A dual-port static random access memory cell comprising: write port portion; and a read port portion electrically coupled to the write port portion and comprising a transistor having a gate structure; a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines is positioned at a first interconnect layer disposed above the gate structure; and A read word line is positioned at a second interconnect layer and electrically coupled to the gate structure, wherein the second interconnect layer is disposed below the gate structure.

2. The semiconductor structure according to claim 1, further comprising: a first through hole, disposed below the gate structure and in direct contact with the gate structure; a bonding pad, disposed directly below and in direct contact with the first through hole; and The second through hole is directly disposed under the bonding pad and in direct contact with the bonding pad. The second interconnect layer is disposed below the second through hole and directly contacts the second through hole.

3. The semiconductor structure of claim 2 , wherein the transistor further comprises a first source / drain feature electrically coupled to the write port portion and a second source / drain feature electrically coupled to a read bit line, and the read bit line is positioned at a third interconnect layer disposed above the gate structure.

4. The semiconductor structure according to claim 3, further comprising: a silicide layer disposed above and in direct contact with the second source / drain feature; as well as a source / drain contact disposed on the silicide layer and in direct contact with the silicide layer; The third interconnect layer is disposed on the source / drain contact and is in direct contact with the source / drain contact.

5. The semiconductor structure of claim 1 , wherein the transistor further comprises vertically stacked nanostructures, and the gate structure comprises a first portion and a second portion, the first portion being located above the vertically stacked nanostructures, and the second portion surrounding each of the vertically stacked nanostructures.

6. A semiconductor structure comprising: a memory cell connected to a write word line and a read word line; A first interconnect structure disposed above the memory cell and including the write word line; as well as The second interconnect structure is disposed below the memory cell and includes the read word line.

7. The semiconductor structure according to claim 6, wherein the memory cell comprises: The first active area and the second active area extend longitudinally along a first direction; as well as The first gate structure and the second gate structure extend longitudinally in a second direction perpendicular to the first direction, The first gate structure is bonded to the first active region to form an N-type transistor, and the first gate structure is electrically coupled to the write word line, and The second gate structure is bonded to the second active region to form a P-type transistor, and the second gate structure is electrically coupled to the read word line.

8. A semiconductor structure comprising: The first storage unit includes: write port portion; and A read port portion includes a transistor and a gate structure, wherein the transistor has a first source / drain feature and a second source / drain feature coupled to a channel region, and the gate structure is bonded to the channel region. a backside via disposed directly below and in direct contact with the gate structure; and A first interconnect layer is disposed below the backside via and electrically coupled to the backside via, wherein a read word line is positioned at the first interconnect layer.

9. The semiconductor structure of claim 8 , wherein the first memory cell is connected to a first power line for receiving a first power supply voltage and a second power line for receiving a second power supply voltage, wherein the first power line and the second power line are positioned at a second interconnect layer disposed above the gate structure. 10 . The semiconductor structure of claim 8 , further comprising a second memory cell, wherein the backside via is in direct contact with a gate structure of a transistor in a read port portion of the second memory cell.

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