Chip structure
By introducing a connection layer and a filling structure into the wafer-level packaging structure, the problem of chip structure being easily broken during the cutting process is solved, and more efficient packaging protection and strength enhancement are achieved.
Patent Information
- Application Number
- CN202422448292.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-10-10
AI Technical Summary
In the prior art, during the wafer-level packaging process, the chip structure is easily broken during cutting and forming, resulting in abnormalities.
A wafer-level packaging structure is adopted, including a first-layer substrate, a second-layer substrate, a connecting layer and a chip module. The connecting layer is arranged around the periphery of the sealing functional area and a filling structure is arranged around it. The filling structure is located around the connecting layer to prevent the chip structure from being damaged during the cutting process.
It effectively protects the chip structure and prevents breakage and damage during the cutting process, while improving packaging efficiency and enhancing the strength and stability of the chip structure.
Smart Images
Figure CN223333778U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor packaging and testing, in particular to a chip structure. Background Art
[0002] Chip structures generally require protection to prevent accidental damage. Traditional chip packaging involves securing pre-processed and segmented individual chips within a package tube, connecting the chip contacts to the electrical pins on the package tube via wire bonding, and finally encapsulating them with insulating packaging material or adding a cover. With the advancement of semiconductor manufacturing processes, wafer-level packaging (WLP) has been developed to increase integration and reduce chip manufacturing costs. This technology involves packaging and testing the entire wafer before cutting it into individual finished chip structures. The chip structure is prone to cracking and abnormalities during the cutting process. Utility Model Content
[0003] One of the purposes of the present invention is to provide a chip structure to solve the technical problems of chip structures in the prior art.
[0004] In order to achieve one of the purposes of the above-mentioned utility model, one embodiment of the utility model provides a wafer-level packaging structure, including a first-layer substrate, a second-layer substrate, a connecting layer, and a chip module arranged on at least one of the first-layer substrate and the second-layer substrate; the connecting layer connects the first-layer substrate and the second-layer substrate, the chip module has a sealing functional area, the connecting layer is arranged around the periphery of the sealing functional area, and the chip structure also includes a filling structure arranged around the periphery of the connecting layer.
[0005] As a further improvement of an embodiment of the present invention, the outer peripheral surface of the filling structure and the outer peripheral surface of the first substrate and / or the second substrate are located in the same plane.
[0006] As a further improvement of an embodiment of the present invention, the chip structure includes a bonding layer provided at the connection between the connection layer and the first substrate and / or the second substrate.
[0007] As a further improvement of an embodiment of the present invention, the connection layer is formed on the first substrate, and the chip structure includes a bonding layer fixedly connecting the connection layer and the second substrate.
[0008] As a further improvement of one embodiment of the present invention, the chip module is arranged on the first layer substrate, the first layer substrate has a first surface forming the sealing functional area, the second layer substrate includes a base and a circuit layer arranged on the base, and the surface of the circuit layer is connected to the first surface through a connecting layer.
[0009] As a further improvement of one embodiment of the present invention, a filling groove is formed on the first surface, the filling structure fills the filling groove, the connecting layer separates the filling groove and the sealing functional area, and the bonding layer is further sealed between the filling groove and the sealing functional area.
[0010] As a further improvement of an embodiment of the present invention, the non-functional area of the circuit layer is at least partially connected to the filling structure.
[0011] As a further improvement of an embodiment of the present invention, at least one of the first substrate and the second substrate is penetrated to form a gap along the thickness direction, and the gap corresponds to the filling structure along the thickness direction.
[0012] As a further improvement of an embodiment of the present invention, the outer wall surface of the notch has an inclined surface, and the inclined surface is inclined away from the end of the filling structure toward the direction close to the sealing functional area.
[0013] As a further improvement of an embodiment of the present invention, the filling structure extends into the gap.
[0014] Compared with the prior art, the utility model provides a chip structure, including a connecting layer arranged around the periphery of the sealing functional area and a filling structure arranged around the periphery of the connecting layer. The filling structure is used to protect the internal chip module to prevent accidental damage on the one hand, and on the other hand, it can prevent damage to the chip structure when the chip structure is cut to form during the wafer-level packaging process. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a planar schematic diagram of the chip structure in one embodiment of the present invention.
[0016] Figure 2 It is a cross-sectional schematic diagram of the chip structure in one embodiment of the present invention.
[0017] Figure 3 It is a cross-sectional schematic diagram of a chip structure in another embodiment of the present invention.
[0018] Figure 4 It is a planar schematic diagram of the first wafer in one embodiment of the present invention.
[0019] Figure 5 It is a planar schematic diagram of a wafer-level packaging structure in one embodiment of the present invention.
[0020] Figure 6 It is a cross-sectional schematic diagram of a wafer-level packaging structure in one embodiment of the present invention.
[0021] Figure 7It is a cross-sectional schematic diagram of a wafer-level packaging structure in another embodiment of the present invention.
[0022] Figure 8-9 It is the first wafer-level packaging method to form chip structures.
[0023] Figure 10 It is the second wafer-level packaging method to form the chip structure.
[0024] Figure 11 It is the third wafer-level packaging method to form chip structure. DETAILED DESCRIPTION
[0025] The present invention will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.
[0026] It should be noted that the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article or apparatus. In addition, the terms "first," "second," "third," "fourth," etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.
[0027] The terms "connected," "connected to," or any other variations thereof are intended to encompass various relative positions in a connected relationship, including direct and indirect connections. A direct connection may be established through a gas pipeline, while an indirect connection may be established through components such as valves, sensors, gas circuit components such as a brake control unit, or any other medium such as air.
[0028] See Figure 1 , is a planar schematic diagram of a chip structure 1000 provided in one embodiment of the present invention.
[0029] The chip structure 1000 includes a first substrate 10 , a second substrate 20 , a connection layer 32 , and a chip module 30 disposed on at least one of the first substrate 10 and the second substrate 20 ; the connection layer 32 connects the first substrate 10 and the second substrate 20 .
[0030] The first substrate 10 is formed by cutting a first wafer 100 along its thickness. The first wafer 100 can be manufactured using semiconductor fabrication techniques. For example, N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices are formed on a semiconductor substrate through deposition, etching, and other processes. A dielectric layer, metal interconnect structures, and pads electrically connected to the metal interconnects are formed on the devices. The first wafer 100 can be made of a third-generation semiconductor material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride, or indium gallium.
[0031] The second substrate 20 is formed by cutting the second wafer 200 along the thickness direction. The second wafer 200 can be made using semiconductor manufacturing technology. For example, N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices are formed on a semiconductor substrate through deposition, etching and other processes, and a dielectric layer, a metal interconnection structure, and a pad electrically connected to the metal interconnection junction are formed on the device. The second wafer 200 can be: lithium tantalate (LiTaO3), lithium niobate (LiNbO3), silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP).
[0032] The chip module 30 includes at least one chip, and the multiple chips may be chips with the same function; alternatively, the multiple chips may include at least two chips with different functions. The chip may include at least one of a logic chip, a memory chip, a central processing unit chip, a microprocessor chip, and an analog-to-digital conversion chip, or the chip may include at least one MEMS chip selected from the group consisting of a microphone, a pressure sensor, a velocity sensor, an acceleration sensor, and a filter, or a sensor chip capable of sensing one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals, etc.
[0033] The chip module 30 can be arranged only on the first layer substrate 10, the first layer substrate 10 is the functional substrate, and the second layer substrate 20 is the cover plate; or it can be arranged only on the second layer substrate 20, the second layer substrate 20 is the functional substrate, and the first layer substrate 10 is the cover plate; or it can be arranged on the first layer substrate 10 and the second layer substrate 20 at the same time, the first layer substrate 10 and the second layer substrate 20 are both functional substrates, and form a cover plate for each other; in actual application, it can be adjusted according to packaging requirements.
[0034] Combine Figure 2 As shown, in a specific embodiment, the first substrate 10 is provided with the chip module 30 as a functional substrate, and the second substrate 20 is a cover.
[0035] One end of the connecting layer 32 is connected to the first layer substrate 10, and the other end is bonded to the second layer substrate 20 to achieve the connection between the first layer substrate 10 and the second layer substrate 20; or one end of the connecting layer 32 is connected to the second layer substrate 20, and the other end is bonded to the first layer substrate 10 to achieve the connection between the first layer substrate 10 and the second layer substrate 20.
[0036] The chip structure 1000 includes a bonding layer disposed at the connection between the connection layer 32 and the second substrate 20 .
[0037] Specifically, one end of the connecting layer 32 is formed on the first substrate 10, and one end of the connecting layer 32 is formed on the surface of the first substrate 10 by etching or deposition. The other end of the connecting layer 32 can be bonded to the second substrate 20 by dielectric bonding without dielectric bonding, and the bonding layer is a surface layer of the connecting layer 32; or it can be bonded to the second substrate 20 by dielectric bonding, and the dielectric material can be organic glue or metal, and the bonding layer can be an organic glue layer or a metal layer.
[0038] The chip structure 1000 includes a bonding layer disposed at the connection between the connection layer 32 and the first substrate 10 .
[0039] Specifically, one end of the connecting layer 32 is formed on the second substrate 20, and one end of the connecting layer 32 is formed on the surface of the second substrate 20 by etching or deposition. The other end of the connecting layer 32 can be bonded to the first substrate 10 by dielectric bonding without dielectric bonding, and the bonding layer is a surface layer of the connecting layer 32; or it can be bonded to the first substrate 10 by dielectric bonding, and the dielectric material can be organic glue or metal, and the bonding layer can be an organic glue layer or a metal layer.
[0040] The chip structure includes a bonding layer provided at the connection between the connection layer 32 and the first substrate 10 and the second substrate 20 .
[0041] One end of the connection layer 32 is bonded to the first substrate 10 by non-dielectric bonding or dielectric bonding, and the other end of the connection layer 32 is bonded to the second substrate 20 by non-dielectric bonding or dielectric bonding. The bonding layer can be a surface layer of the connection layer 32, or can be an organic adhesive layer or a metal layer.
[0042] In a preferred embodiment, the connection layer 32 is formed on the first substrate, and the chip structure includes a bonding layer fixedly connecting the connection layer 32 and the second substrate 20 .
[0043] Specifically, combined Figure 2 As shown, one end of the connecting layer 32 is deposited on the first substrate 10. The process is simple and the connection is stable and firm. The other end of the connecting layer 32 is bonded to the second substrate 20 through a bonding layer. The bonding layer is an organic adhesive layer. In this way, the connection between the first substrate 10 and the second substrate 20 is achieved.
[0044] The chip module 30 has a sealing functional area 31 , the connection layer 32 is disposed around the periphery of the sealing functional area 31 , and the chip structure 1000 further includes a filling structure 40 disposed around the periphery of the connection layer 32 .
[0045] Each chip module 30 includes a sealing functional area 31 and a bonding pad area. The bonding pad area is electrically coupled to the sealing functional area 31 . The bonding pad area is used to electrically connect to an external circuit to connect the chip module 30 to the external circuit.
[0046] In a preferred embodiment, the outer periphery of the filling structure 40 is located in the same plane as the outer periphery of the first substrate 10 and / or the second substrate 20. In other words, the filling structure 40 constitutes part of the outer wall of the chip structure 1000 to protect the internal structure.
[0047] When the chip module 30 includes one chip, the filling structure 40 is disposed around the periphery of the one chip. When the chip module 30 includes multiple chips, the filling structure 40 is disposed around the peripheries of the multiple chips.
[0048] Combine Figure 2-3 As shown, due to different packaging methods, the outer peripheral surface of the filling structure 40 can be located in the same plane with the outer peripheral surfaces of the first layer substrate 10 and the second layer substrate 20 at the same time, or it can be located in the same plane with the outer peripheral surface of the first layer substrate 10 or the second layer substrate 20 alone.
[0049] In a preferred embodiment, the chip module 30 is disposed on the first substrate 10. The first substrate 10 has a first surface 301 forming the sealing functional area 31. The second substrate 20 includes a base and a circuit layer 21 disposed on the base. The surface of the circuit layer 21 is connected to the first surface 301 via a connection layer 32. The circuit layer 21 has a functional area and a non-functional area. The functional area of the circuit layer 21 is connected to the chip module 30.
[0050] The non-functional area of the circuit layer 21 is at least partially connected to the filling structure 40 . The filling structure 40 does not need to realize any function, and thus corresponds to the non-functional area of the circuit layer 21 .
[0051] A filling groove 33 is formed on the first surface 301, and the filling structure 40 is filled in the filling groove 33. The connecting layer 32 separates the filling groove 33 from the sealing functional area 31. The bonding layer is further sealed between the filling groove 33 and the sealing functional area 31 to prevent the filling structure 40 from entering the sealing functional area 31 and affecting the function of the chip.
[0052] In a preferred embodiment, at least one of the first substrate 10 and the second substrate 20 is penetrated to form a notch 22 along the thickness direction, and the notch 22 corresponds to the filling structure 40 along the thickness direction.
[0053] Combine Figure 3 As shown, due to the different packaging methods used during the packaging process of the chip structure 1000, the first substrate 10 and the second substrate 20 of the chip structure 1000 are different in structure after cutting, but this does not affect the presence of the filling structure 40 between the two. The specific packaging method will be described in detail below.
[0054] Combine Figure 3 As shown, the first substrate 10 is provided with a chip module 30 , and the second substrate 20 forms a notch 22 , which connects the filling groove 33 with the outside. In actual packaging, the notch 22 is used to fill the filling groove 33 with the filling structure 40 .
[0055] The outer wall of the notch 22 has an inclined surface, which slopes from the end away from the filling structure 40 toward the sealing functional area 31. On the one hand, the inclined surface has a guiding effect. On the other hand, the opening size of the notch 22 near the filling structure 40 is small. The notch 22 originally corresponds to the non-functional area of the circuit layer 21, so more functional area of the circuit layer 21 can be retained.
[0056] The filling structure 40 is generally located between the first substrate 10 and the second substrate 20 along the thickness direction. In other embodiments, the filling structure 40 also extends into the gap 22 to provide better support and protection.
[0057] The following will describe in detail the first wafer-level packaging method for forming the chip structure 1000, specifically, a wafer-level packaging method for filling a supporting material before bonding. Figure 4-6 , 8-9, where Figure 8-9 To simplify the step diagram, only the position of the filling portion 400 is shown.
[0058] S1: Provide a first wafer 100 and a second wafer 200. The first wafer 100 is provided with a plurality of chip modules 30. At least some of the chip modules 30 have a sealing functional area 31 exposed to the first surface 110 of the first wafer 100. The second wafer 200 has a substrate and a circuit layer 310 disposed on the substrate.
[0059] Combine Figure 4 As shown, the first wafer 100 is arranged with a plurality of chip modules 30 to form a device wafer, and the second wafer 200 may be formed as a cover wafer without chip modules 30. The structure of the chip module 30 is described above and will not be repeated here.
[0060] S2: forming a connection portion 320 on the first surface 110 and surrounding at least a portion of the outer periphery of the sealing functional area 31 , and forming a cutting path cavity 330 between adjacent connection portions 320 .
[0061] Combine Figure 5-6 As shown, the first wafer 100 is provided with a chip module 30, and the connecting portion 320 is formed on the first wafer 100. It can be formed on the first surface 110 by deposition or bonded to the first surface 110 via a bonding layer. The saw path cavity 330 can be formed when the first wafer 100 is formed or formed by subsequent etching.
[0062] The connecting portion 320 is annular in structure, and the cutting path cavities 330 are crisscrossed. The outer ends of the cutting path cavities 330 are connected to the outside, which is convenient for subsequent filling of support materials.
[0063] In a preferred embodiment, the cutting road cavity 330 includes several transverse cutting roads 331 that pass through horizontally, and several longitudinal cutting roads 332 that pass through longitudinally, and the transverse and longitudinal directions are horizontal and perpendicular to each other; several of the transverse cutting roads 331 are arranged along the longitudinal direction, and several of the longitudinal cutting roads 332 are arranged along the transverse direction, and the transverse cutting roads 331 and the longitudinal cutting roads 332 are cross-connected to facilitate the flow of supporting materials.
[0064] The outer ends of the cutting lane cavities 330 are connected to the outside world, including both ends of the transverse cutting lanes 331 being connected to the outside world, and both ends of the longitudinal cutting lanes 332 being connected to the outside world.
[0065] In a preferred embodiment, the width of the transverse cutting street 331 and / or the longitudinal cutting street 332 ranges from 40 mm to 200 mm. Theoretically, for the first wafer 100, the second wafer 200 and the chip module 30 of different sizes, the smaller the width of the cutting street cavity 330, the better, so as to reserve more space for the chip module 30. In actual packaging applications, due to the limitations of the process level, the width of the cutting street cavity 330 cannot be made particularly small. Common widths of the cutting street cavity 330 are 80 mm and 120 mm, ensuring a suitable width of the cutting street cavity 330 without taking up too much space on the first wafer 100.
[0066] In a preferred embodiment, the scribe line cavity 330 further includes transverse scribe lines and longitudinal scribe lines located at the periphery of the chip module 30 in the edge region.
[0067] S3: Filling the scribe line cavities 330 with support material. The scribe line cavities 330 in all regions of the first wafer 100 are filled with support material. In other words, filling portions 400 are formed in all transverse scribe lines 331 and longitudinal scribe lines 332 to enhance support.
[0068] The supporting material gradually solidifies in the scribe line cavity 330 to form a filling portion 400 .
[0069] In a preferred embodiment, the supporting material is at least one of photoresist, epoxy resin glue, and UV glue. The flowing colloid is easy to fill and has viscosity.
[0070] In a preferred embodiment, when the supporting material is photoresist, “filling the scribe line cavity 330 with the supporting material” comprises the following steps:
[0071] S31: Apply photoresist to the first surface 110 of the first wafer 100. The first wafer 100 is provided with the chip module 30 and the connecting portion 320. The first surface 110 is formed with a sealing functional area 31. When the photoresist is applied to the first surface 110, it is understood that the sealing functional area 31 and the dicing street cavity 330 will be filled with photoresist.
[0072] S32: Exposure and development are performed to form a photoresist protrusion protruding from the connection portion 320 within the scribe line cavity 330. Photoresist is a photoresist material that can be effectively removed and retained using its photoresist properties. Specifically, when using a mask for exposure and development, a suitable mask pattern is created to remove the photoresist on the surface of the connection portion 320 and the sealing functional area 31, leaving only the photoresist in the scribe line cavity 330, thereby forming a photoresist protrusion protruding from the connection portion 320.
[0073] S33 : Grinding the photoresist protrusions so that they do not protrude beyond the connecting portion 320 , otherwise it will affect the subsequent bonding of the first wafer 100 and the second wafer 200 .
[0074] In this way, in this embodiment, the scribe line cavity 330 is filled before the first wafer 100 and the second wafer 200 are bonded.
[0075] In a preferred embodiment, the support material is epoxy resin glue or UV glue, and "filling the scribe line cavity with the support material" includes the step of dispensing the epoxy resin glue or UV glue into the scribe line cavity 330. Epoxy resin glue or UV glue cannot be easily removed, so it can only be specifically dispensed directly into the scribe line cavity 330 using a glue dispenser to form the filling portion 400.
[0076] Similarly, the filling of the scribe line cavity 330 can be completed before the first wafer 100 and the second wafer 200 are bonded.
[0077] The wafer-level packaging method of filling support material before bonding is simple in process and easy to operate. It can accurately control the extent to which the support material fills the cutting path cavity 330, such as controlling the amount and position of the filled glue, to ensure good support during cutting without glue overflow.
[0078] S4: Bonding the connecting portion 320 and the second wafer 200 to form a wafer-level packaging structure 2000. Specifically, the surface of the circuit layer 210 of the second wafer 200 is bonded to the connecting portion 320, and the cutting path cavity 330 corresponds to the non-functional area of the circuit layer 210. In this way, the functional area of the circuit layer 210 is not affected.
[0079] The connecting portion 320 is formed on the surface of the first wafer 100. The end of the connecting portion 320 close to the second wafer 200 can be bonded to the surface of the circuit layer 210 of the second wafer 200 without a dielectric, or can be metal bonded, or bonded with a coated bonding adhesive. In this way, the first wafer 100 and the second wafer 200 are connected. In actual application, during the bonding connection, the first wafer 100 and the second wafer 200 are in a high temperature and high pressure environment.
[0080] In one embodiment, “bonding the connecting portion 320 and the second wafer 200” includes the following steps:
[0081] S41: Apply bonding adhesive to the connection portion 320. The bonding adhesive can be applied to the connection portion 320 or to the circuit layer surface of the second wafer 200. The chip module 30 and the connection portion 320 are provided on the first wafer 100. The connection portion 320 is formed on the first wafer 100. The wafer-level packaging structure 2000 includes the bonding adhesive disposed between the connection portion 320 and the second wafer 200.
[0082] In one embodiment, the filling portion 400 connects the first wafer 100 and the second wafer 200 along the thickness of the wafer-level packaging structure 2000. The filling portion 400 fills the scribe line cavity 330 of the first wafer 100 and is also connected to the second wafer 200. Furthermore, during the bonding process, if exposed to high temperatures, the filling portion 400 becomes a fluid colloid and further adheres to the second wafer 200.
[0083] The cutting path cavity 330 is the location where the first wafer 100 and the second wafer 200 are cut to form the chip structure 1000 after the first wafer 100 and the second wafer 200 are bonded. The cutting path cavity 330 achieves the effect of dividing several chip modules 30 from each other, realizes wafer-level packaging, simplifies the process flow, and improves packaging efficiency.
[0084] It is understood that the wafer-level package structure 2000 may be thinned before being cut to form the chip structure 1000. The backside of the first wafer 100 and / or the second wafer 200 may be thinned to a suitable thickness to ensure the performance of the chip module 30 within the first wafer 100 while reducing the package thickness.
[0085] S5: Cutting the corresponding scribe line cavities 330 to form a plurality of independent chip structures 1000. When cutting the scribe line cavities 330, since all scribe line cavities 330 are provided with filling portions 400, they provide good support. On the one hand, this prevents cracks and damage to the wafer-level packaging structure 2000 during the thinning and cutting processes; on the other hand, when the wafer-level packaging structure 2000 undergoes a wet process, the presence of the filling portions 400 prevents liquid from flowing into the scribe line cavities, which would cause corrosion of the scribe line cavities.
[0086] It can be seen that the chip structure 1000 is formed by cutting the entire wafer-level packaging structure 2000, the first layer substrate 10 is formed by cutting the first wafer 100, the second layer substrate 20 is formed by cutting the second wafer 200, the filling structure 40 is formed by cutting the filling part 400, and the connecting layer 32 is formed by cutting the connecting part 320. The structure of the chip module 30 itself will not be affected, and the chip structure 1000 formed by cutting includes at least one chip module 30.
[0087] The following briefly describes the second wafer-level packaging method for forming the chip structure 1000, specifically, a wafer-level packaging method for forming a groove and then filling the supporting material after bonding. Figure 10 As shown, to simplify the step diagram, only the position of the filling portion 400 is shown.
[0088] S1: Provide a wafer-level packaging structure 2000, which includes a first wafer 100, a second wafer 200 and a connecting portion 320 bonding the first wafer 100 and the second wafer 200, and a cutting path cavity 330 communicating with the outside is provided between at least some adjacent connecting portions 320.
[0089] It is understandable that the material and structural features of the first wafer 100 , the second wafer 200 , the connecting portion 320 and the cutting path cavity 330 are the same as above and will not be repeated here. The only difference lies in the method steps of filling the support material.
[0090] “Providing a wafer-level packaging structure 2000” further includes:
[0091] S11: providing a first wafer 100 and a second wafer 200, wherein the first wafer 100 is provided with a plurality of chip modules 30, and at least some of the chip modules 30 have a sealing functional area 310 exposed to the first surface 110 of the first wafer;
[0092] S12: forming a connecting portion 320 on the first surface 110 and surrounding at least a portion of the outer periphery of the sealing functional area 310;
[0093] S13 : bonding the first wafer 100 and the second wafer 200 .
[0094] The “bonding connection between the first wafer 100 and the second wafer 200” includes the steps of: applying bonding glue on the connecting portion 320; the connecting portion 320 is formed on the first wafer 100, and the wafer-level packaging structure 2000 includes the bonding glue located between the connecting portion 320 and the second wafer 200.
[0095] In other embodiments, the first wafer 100 and the second wafer 200 can be connected without dielectric bonding under a high temperature and high pressure environment, or the first wafer 100 and the second wafer 200 can be connected by metal bonding, and the wafer-level packaging structure 2000 includes the metal layer located between the connecting portion 320 and the second wafer 200.
[0096] In the second method, the first wafer 100 and the second wafer 200 are bonded first. Due to the covering of the second wafer 200 , only the outer end of the dicing cavity 330 is connected to the outside, rather than being completely exposed to the outside.
[0097] S2: forming a through-groove 220 along the thickness direction of the wafer-level packaging structure 2000 , wherein the through-groove 220 is connected to the scribe line cavity 330 along the thickness direction.
[0098] S3: filling the cutting street cavity 330 with supporting material through the through groove 220 . The selection of supporting material is the same as the first method. The supporting material is solidified in the cutting street cavity 330 to form a filling portion 400 .
[0099] Combine Figure 7 As shown, the second method forms a glue-filled through groove 330 by opening the first wafer 100 and / or the second wafer 200 , and a supporting material may also be filled into the through groove 330 to strengthen the support.
[0100] “Making a through groove 220 along the thickness direction in the wafer packaging structure 2000” includes the following steps:
[0101] S21: Cutting the second wafer 200 to form through grooves 220. The through grooves 220 can be selectively formed in the second wafer 200 to prevent interference with the chip module of the first wafer. The second wafer 200 includes a substrate and a circuit layer 210 disposed thereon. The connecting portion 320 connects the first surface 110 and the circuit layer 210. The dicing path cavities 330 correspond to the non-functional areas of the circuit layer 210, ensuring the integrity of the functional areas of the circuit layer 210.
[0102] In other embodiments, the through groove 220 may also be formed by etching or other methods.
[0103] In a preferred embodiment, the through groove 220 includes a transverse through groove arranged corresponding to the transverse cutting road 331 and / or a longitudinal through groove arranged corresponding to the longitudinal cutting road 332, and the transverse cutting road 331 is filled with supporting material through the transverse through groove, and / or the longitudinal cutting road 332 is filled with supporting material through the longitudinal through groove.
[0104] In a specific embodiment, the through groove 220 includes a horizontal through groove corresponding to the horizontal cutting path 331 and a longitudinal through groove corresponding to the longitudinal cutting path 332. The horizontal cutting path 331 and the longitudinal cutting path 332 are both opened and filled with supporting materials respectively. The glue line of the sprayed supporting material is required to be relatively thin relative to the horizontal and longitudinal cutting paths, and will not overflow into the horizontal and longitudinal cutting path cavities.
[0105] In this embodiment, the through-slots 220 include transverse through-slots corresponding to the transverse cut lines 331 and longitudinal through-slots corresponding to the longitudinal cut lines 332. However, only the transverse or longitudinal cut lines are filled, while the cut lines in the other direction are filled due to the fluidity of the glue. This method is suitable for situations where the glue line of the support material cannot be sprayed too fine, but the transverse or longitudinal cut lines are relatively wide, so the glue line width can be adjusted or overflow in that direction can be allowed.
[0106] In a specific embodiment, the through groove 220 includes a horizontal through groove corresponding to the horizontal cutting road 331 or a longitudinal through groove corresponding to the longitudinal cutting road 332. Due to the characteristics of the second wafer 200 or the process capability limitation, the cutting road in a certain direction cannot be opened or the opening process may easily cause damage to the second wafer 200, while the other direction is not restricted. Then, the filling support material only fills the cutting road in one direction, and the cutting road in the other direction is filled by the fluidity of the glue.
[0107] It can be seen that the scribe line cavities 330 in all areas of the first wafer 100 are filled with support materials to provide better support.
[0108] The width of the through-slot 330 is smaller than the distance between two adjacent chip modules 30 . In actual processes, the width of the through-slot 330 is smaller than the width of the dicing cavity 330 .
[0109] The through slot 220 has a first opening close to the cutting path cavity 330 and a second opening away from the cutting path cavity 330 . The size of the first opening is not larger than that of the second opening, thereby retaining more functional areas of the circuit layer of the second wafer 200 .
[0110] The through groove 220 has an inclined surface and has the function of guiding fluid. Along the thickness direction close to the cutting path cavity 330, the opening size of the through groove 220 has a tendency to gradually decrease, ensuring that the colloid gradually flows into the cutting path cavity.
[0111] Specifically, the through groove 220 comprises at least a first inverted trapezoidal groove 221 and a second inverted trapezoidal groove 222 connected along the thickness direction, and a transition plane 223 connecting the first inverted trapezoidal groove 221 and the second inverted trapezoidal groove 222. The transition plane 223 is perpendicular to the thickness direction, facilitating filling and providing good guiding and converging effects.
[0112] S4: Cutting the corresponding dicing street cavities 330 to form a plurality of independent chip structures 1000 .
[0113] Similar to the first method, the first wafer 100 and the second wafer 200 may be thinned before cutting, and the chip structure 1000 may be obtained after cutting.
[0114] The third wafer-level packaging method for forming the chip structure 1000 will be briefly described below, specifically, a wafer-level packaging method for filling the support material with suction after bonding. Figure 11 As shown, to simplify the step diagram, only the position of the filling portion 400 is shown.
[0115] S1: Provide a wafer-level packaging structure 2000, which includes a first wafer 100, a second wafer 200 and a connecting portion 320 bonding the first wafer 100 and the second wafer 200, and a cutting path cavity 330 communicating with the outside is provided between at least some adjacent connecting portions 320.
[0116] S2: Vacuuming the cutting street cavity 330 and filling the cutting street cavity 330 with support material.
[0117] In the third method, the first wafer 100 and the second wafer 200 are still bonded first. Due to the covering of the second wafer 200, the cutting path cavity 330 is only connected to the outside world at the outer end. The cutting path cavity 330 is filled by vacuuming and inputting supporting material from the outer end of the cutting path cavity 330, relying on the flow of supporting material.
[0118] It can be understood that the material structure characteristics of the above-mentioned first wafer 100, second wafer 200, connecting part 320, cutting road cavity 330 and the formed wafer-level packaging structure are also the same as the second method and will not be repeated here. The difference lies in the method steps of filling the supporting material and the fact that the second wafer 200 does not need to form a through-groove structure.
[0119] In a preferred embodiment, “providing a wafer-level packaging structure 2000” further includes:
[0120] S11: providing a first wafer 100 and a second wafer 200, wherein the first wafer 100 is provided with a plurality of chip modules 30, and at least some of the chip modules 30 have a sealing functional area 310 exposed to the first surface 110 of the first wafer;
[0121] S12: forming a connecting portion 320 on the first surface 110 and surrounding at least a portion of the outer periphery of the sealing functional area 310;
[0122] S13 : bonding the first wafer 100 and the second wafer 200 .
[0123] The “bonding connection between the first wafer 100 and the second wafer 200” includes the steps of: applying bonding glue on the connecting portion 320; the connecting portion 320 is formed on the first wafer 100, and the wafer-level packaging structure 2000 includes the bonding glue located between the connecting portion 320 and the second wafer 200.
[0124] In other embodiments, the first wafer 100 and the second wafer 200 can be connected without dielectric bonding under a high temperature and high pressure environment, or the first wafer 100 and the second wafer 200 can be connected by metal bonding, and the wafer-level packaging structure 2000 includes the metal layer located between the connecting portion 320 and the second wafer 200.
[0125] In a preferred embodiment, “evacuating the cutting street cavity 330 and filling the cutting street cavity 330 with support material” includes the following steps:
[0126] S21: placing the wafer-level packaging structure 2000 into a vacuum tank; the vacuum tank includes a vacuum space, a support material located within the vacuum space, and a connecting pipe partially disposed on the support material; the wafer-level packaging structure is located within the vacuum space, and the connecting pipe is connected to the dicing path cavity;
[0127] S22: The vacuum space is pumped to exhaust the gas in the cutting path cavity 330 , and the supporting material is then sucked in through the connecting pipe.
[0128] In this way, the entire wafer-level packaging structure 2000 is placed in a vacuum environment, and the scribe line cavity 330 has a better effect of absorbing the support material.
[0129] In other embodiments, “evacuating the cutting street cavity 330 and filling the cutting street cavity 330 with support material” includes the following steps:
[0130] S21: Evacuate the first end of the cutting street cavity 330 and fill the second end of the cutting street cavity 330 with support material. The first end and the second end are the two ends of the cutting street cavity 330 that are connected to the outside world. In this way, the process is relatively simple and the vacuum requirement is relatively low.
[0131] Specifically, vacuum is drawn at the first end of the transverse cutting street 331 and support material is filled at the second end of the transverse cutting street 331 ; or vacuum is drawn at the first end of the longitudinal cutting street 332 and support material is filled at the second end of the longitudinal cutting street 332 .
[0132] S3: Cutting the corresponding dicing street cavities 330 to form a plurality of independent chip structures 1000 .
[0133] Still similar to the second method, the first wafer 100 and the second wafer 200 can be thinned before cutting to obtain a chip structure 1000. The second substrate 20 of the chip structure 1000 will not form the above-mentioned gap 22. The third method and the first method form a complete and consistent chip structure 1000.
[0134] The beneficial effects of the present invention are: a filling portion 400 is formed in the cutting path cavity 330, which has good support and prevents the first wafer 100 and / or the second wafer 200 from being broken and damaged during the thinning and cutting process; the cutting path cavity 330 is filled to prevent liquid from entering the cutting path cavity 330 during the wet process and corroding it, thereby affecting the chip module; the chip structure 1000 formed by cutting has a filling structure 40, which enhances the strength of the chip structure 1000. The filling structure 40 is arranged around the outer periphery of the connecting layer 32 to prevent liquid from entering, thereby protecting the internal chip module 30 and preventing accidental damage.
[0135] It can be formed by referring to any of the technical solutions provided above, and will not be described here in detail.
[0136] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
[0137] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. A chip structure, characterized in that: The invention comprises a first substrate, a second substrate, a connecting layer and a chip module arranged on at least one of the first substrate and the second substrate; the connecting layer connects the first substrate and the second substrate, the chip module has a sealing functional area, the connecting layer is arranged around the periphery of the sealing functional area, and the chip structure also includes a filling structure arranged around the periphery of the connecting layer.
2. The chip structure according to claim 1, characterized in that: The outer peripheral surface of the filling structure and the outer peripheral surface of the first substrate and / or the second substrate are located in the same plane.
3. The chip structure according to claim 1, wherein: The chip structure includes a bonding layer provided at a connection between the connection layer and the first substrate and / or the second substrate.
4. The chip structure according to claim 1, wherein: The connection layer is formed on the first substrate, and the chip structure includes a bonding layer fixedly connecting the connection layer and the second substrate.
5. The chip structure according to claim 4, characterized in that: The chip module is arranged on the first substrate, the first substrate has a first surface forming the sealing functional area, the second substrate includes a base and a circuit layer arranged on the base, and the surface of the circuit layer is connected to the first surface through a connecting layer.
6. The chip structure according to claim 5, characterized in that: A filling groove is formed on the first surface, the filling structure is filled in the filling groove, the connecting layer separates the filling groove and the sealing functional area, and the bonding layer is further sealed between the filling groove and the sealing functional area.
7. The chip structure according to claim 5, characterized in that: The non-functional area of the circuit layer is at least partially connected to the filling structure.
8. The chip structure according to claim 1, wherein: A notch is formed through at least one of the first substrate and the second substrate along the thickness direction, and the notch corresponds to the filling structure along the thickness direction.
9. The chip structure according to claim 8, characterized in that: The outer wall surface of the notch has an inclined surface, and the inclined surface is inclined toward the sealing functional area away from the end of the filling structure.
10. The chip structure according to claim 9, characterized in that: The filling structure extends into the gap.