Package structure
By adopting the design of substrate clamping structure and nonlinear electric field gradient material layer in the semiconductor packaging structure, the problems of tip discharge breakdown and low heat dissipation efficiency are solved, and a high reliability and low-cost packaging solution is achieved.
Patent Information
- Application Number
- CN202421858834.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-08-02
AI Technical Summary
In semiconductor packaging structures, under high voltage and high current conditions, the electric field intensity is concentrated at the tip, leading to discharge breakdown. In addition, traditional packaging structures use many materials, are costly, bulky, and have low heat dissipation efficiency.
A clamping structure is formed by a first substrate and a second substrate. The integrated circuit achieves double-sided heat dissipation through the two side substrates. A nonlinear electric field gradient material layer is coated on the side of the first boss to prevent tip discharge. Support columns support the space between the substrates to avoid damage to the integrated circuit.
The reliability and heat dissipation efficiency of the packaging structure are improved, the problem of tip discharge breakdown is avoided, the structure is compact and the cost is low, and it is suitable for high-power and high-heat scenarios.
Smart Images
Figure CN223333784U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging, and more specifically, to a packaging structure. Background Art
[0002] During the reliability verification of semiconductor packaging structures, under high voltage and high current conditions, electric field concentration is prone to occur at right-angled tip structures. This creates a high surface charge density at the tip, resulting in a strong electric field near the tip. Discharge from the tip to the surrounding air or adjacent grounding objects can easily occur, leading to damage and failure of the semiconductor package. This electric field concentration effect is common. Traditional packaging structures use square spacers, which are associated with the tip effect. This can cause breakdown during reliability verification, leading to insulation failure in the package structure. Furthermore, the high electric field strength causes tension on polar molecules in the molding compound, accelerating its aging and ultimately shortening the package lifespan. This electric field concentration at the tip reduces the reliability of the package structure. Furthermore, traditional packaging structures use more materials, including multiple spacers for support, increasing both cost and the package itself.
[0003] Therefore, how to design a packaging structure with compact structure, excellent heat dissipation, and effective avoidance of internal tip discharge is an urgent problem to be solved at this stage. Utility Model Content
[0004] In view of this, the purpose of the present invention is to provide a packaging structure that not only solves the breakdown caused by tip discharge under high current and high voltage conditions, but also improves the heat dissipation efficiency.
[0005] The utility model provides a packaging structure, comprising: a first substrate and a second substrate arranged opposite to each other; an integrated circuit located between the first substrate and the second substrate; pins, the pins being connected to one of the first substrate and the second substrate and electrically connected to the integrated circuit; wherein, one of the first substrate and the second substrate is provided with a first boss, the first boss facing the other of the first substrate and the second substrate and corresponding to the integrated circuit; the side surface of the first boss is coated with a barrier layer.
[0006] Optionally, the other of the first substrate and the second substrate is further provided with a first groove corresponding to the first boss, and the integrated circuit is located in the first groove.
[0007] Optionally, one of the first substrate and the second substrate is further provided with a support column facing the other substrate.
[0008] Optionally, the other of the first substrate and the second substrate is provided with a second groove, and the second groove corresponds to the supporting column.
[0009] Optionally, the integrated circuit includes at least one of an IGBT, an FRD, a MOSFET, and a driver chip.
[0010] Optionally, the barrier layer is a nonlinear electric field gradient material layer with a thickness of 0.1 mm to 0.3 mm.
[0011] Optionally, the barrier layer includes one or a combination of layers selected from the group consisting of a ZnO layer, a BaTiO 3 layer, a SiO 2 layer, a TiO 2 layer, and a Fe 3 O 4 layer.
[0012] Optionally, one of the first substrate and the second substrate and the first boss are an integral structure; one of the first substrate and the second substrate and the support column are an integral structure.
[0013] Optionally, both the first substrate and the second substrate are copper-clad ceramic substrates.
[0014] Optionally, a depth of the first groove is 15% to 20% of a thickness of the integrated circuit.
[0015] Optionally, the diameter of the support column is 15% to 20% of the length of the packaging structure.
[0016] Optionally, the sum of the difference between the thickness of the integrated circuit and the depth of the first groove and the height of the first boss is not greater than the difference between the height of the support pillar and the depth of the second groove.
[0017] Optionally, solder pads are further provided on both side surfaces of the integrated circuit.
[0018] Optionally, a plastic package is further included, wherein the plastic package covers the integrated circuit, the first substrate, the second substrate, the space between the first substrate and the second substrate, and part of the pins.
[0019] Optionally, the pins extend from two opposite sides of the plastic package body, and the pins include power pins, and the power pins are located on the same side of the plastic package body.
[0020] Optionally, at least part of the surfaces of the first substrate and the second substrate are exposed from the plastic package body.
[0021] Optionally, a cross-sectional dimension of the first boss matches that of the integrated circuit, and the cross-sectional dimension of the first boss includes any one of a circle, a triangle, and a rectangle.
[0022] Optionally, the size of the first substrate is the same as or different from the size of the second substrate.
[0023] Optionally, the first boss and the supporting column are located on the first substrate, and the first groove and the second groove are both located on the second substrate.
[0024] Optionally, the second grooves include at least two, and the two second grooves are respectively located on two sides of the integrated circuit.
[0025] Optionally, the first substrate and the second substrate are both rectangular, the second grooves include at least four, the four second grooves are respectively located at the four corners of the second substrate, and the first grooves include four, the four first grooves are arrayed in the middle area of the second substrate.
[0026] Beneficial effects of the utility model:
[0027] The packaging structure provided by the utility model fixes the integrated circuit by forming a clamping structure with a first substrate and a second substrate. The integrated circuit can achieve double-sided heat dissipation through the substrates on both sides, thereby achieving a better heat dissipation effect.
[0028] Furthermore, a barrier layer is coated on the side of the first boss connected to the integrated circuit, which can effectively avoid the breakdown problem caused by tip discharge under high current and high voltage conditions, thereby enhancing the reliability of the packaging structure.
[0029] Furthermore, by supporting the space between the two substrates with the support pillars, the integrated circuit (eg, IGBT, FRD, MOSFET, driver chip) can be effectively prevented from being crushed by the first boss.
[0030] Furthermore, the first boss and one of the substrates are an integrated structure, which can solve the problem of easy displacement and complicated process of setting the first boss on the integrated circuit in the traditional structure, and there is no need to consider the welding and anti-oxidation issues of the first boss; the support column and one of the substrates are an integrated structure, which can reduce the cumbersome process flow and directly achieve the support effect.
[0031] This packaging structure is low-cost and compact, and also has a double-sided heat dissipation design, which can effectively avoid the breakdown problem caused by tip discharge under high current and high voltage conditions, and is better suitable for high-power and high-heat scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.
[0033] Figure 1 An exploded view showing the packaging structure of the first embodiment of the present invention;
[0034] Figure 2 A three-dimensional schematic diagram showing the packaging structure of the first embodiment of the present utility model;
[0035] Figure 3 A schematic top view of the packaging structure of the second embodiment of the present invention is shown;
[0036] Figure 4 A schematic diagram showing two substrates in a packaging structure according to a second embodiment of the present invention;
[0037] Figure 5 A schematic diagram showing a first substrate in a packaging structure according to a second embodiment of the present invention;
[0038] Figure 6 A schematic diagram showing a second substrate in a packaging structure according to a second embodiment of the present invention;
[0039] Figure 7 A front view showing the combination of the first substrate and the second substrate in the packaging structure of the second embodiment of the present utility model;
[0040] Figure 8 A top view showing the combination of the first substrate and the second substrate in the packaging structure of the second embodiment of the present invention is shown;
[0041] Figure 9 The packaging structure of the second embodiment of the present invention is shown along Figure 8 Schematic cross-sectional view of line AA;
[0042] Figure 10 The packaging structure of the second embodiment of the present invention is shown along Figure 8 Schematic cross-sectional view along the midline BB. DETAILED DESCRIPTION
[0043] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0045] Figure 1 and Figure 2 The exploded view and the three-dimensional schematic diagram of the packaging structure of the first embodiment of the utility model are shown respectively; in order to make the structure of each part clearer, Figure 1The plastic package 50 is omitted. The packaging structure of the first embodiment includes: a first substrate 10, a second substrate 20, an integrated circuit 30, and pins. The first substrate 10 and the second substrate 20 are arranged opposite to each other, and the integrated circuit 30 is located between the first substrate 10 and the second substrate 20. The integrated circuit 30 includes, for example, an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a fast recovery diode (FRD), a driver chip, etc. Specifically, the first substrate 10 and the second substrate 20 are, for example, copper-clad ceramic substrates (DBC), both of which are rectangular, and the surface of the first substrate 10 facing the second substrate 20 is provided with, for example, four first bosses 11 and four support columns 12, the four support columns 12 are, for example, respectively located at the four corners of the first substrate 10, and the four first bosses 11 are, for example, located in the middle area of the first substrate 10 and arranged in a 2*2 array; accordingly, the surface of the second substrate 20 facing the first substrate 10 is provided with first grooves 21 corresponding to the first bosses 11, and first grooves 21 corresponding to the support columns 12. The second groove 22 corresponds to the first groove 21, and the depth of the first groove 21 is, for example, 15% to 20% of the thickness of the integrated circuit 30. The cross-sections of the first groove 21 and the integrated circuit 30 are, for example, rectangular. The cross-sectional dimensions of the integrated circuit 30 are, for example, slightly smaller than the cross-sectional dimensions of the first groove 21, so that the integrated circuit 30 can be at least partially embedded in the first groove 21. Furthermore, the upper surface of the integrated circuit 30 is also provided with a soldering piece 31 of a corresponding size for fixing and partially electrically connecting the integrated circuit 30. Of course, the lower surface of the integrated circuit 30 is also provided with a soldering piece 31 (not shown). The shape and dimensions of the first projection 11 correspond, for example, to those of the first recess 21. The cross-section of the first projection 11 is also rectangular. As a quadrangular prism with four right-angled apexes, the first projection 11 is susceptible to electric field concentration under high voltage and current conditions, potentially discharging electricity to adjacent structures and damaging the package structure. Therefore, a barrier layer is coated on the side of the first projection 11. This barrier layer is made of a nonlinear electric field gradient material, such as ZnO, BaTiO3, SiO2, TiO2, or Fe3O4. The thickness of the barrier layer is, for example, 0.1 mm to 0.3 mm, to ensure its insulation performance. Typically, nonlinear electric field gradient materials (NFGMs) are made of a polymer matrix filled with high-dielectric-constant particles, such as barium titanate, lead zirconium titanate, or titanium oxide. The electric field in the NFG material layer is altered by the polarization current, reducing the electric field at the metallized edge.The cross-section of the second groove 22 is, for example, circular, and the cross-section of the support pillar 12 is, for example, also circular. The cross-section of the second groove 22 is, for example, slightly larger than that of the support pillar 12, so that the top of the support pillar 12 can at least partially extend into the second groove 22. The diameter of the support pillar 12 is, for example, 15% to 20% of the length of the second substrate 20 (package structure), thereby providing effective support and preventing the integrated circuit 30 in the central region of the second substrate 20 from being excessively squeezed and damaged. Specifically, the first boss 11 is, for example, a copper block, and the support pillar 12 is, for example, a copper pillar. The sum of the difference between the thickness of the integrated circuit 30 and the depth of the first groove 21 and the height of the first boss 11 is no greater than the difference between the height of the support pillar 12 and the depth of the second groove 22. That is, after the first substrate 10 and the second substrate 20 are combined, the integrated circuit 30 will not be excessively squeezed.
[0046] The pins include a first pin 41 located on a first side of the second substrate 20 and a second pin 42 located on a second side of the second substrate 20. The first side and the second side are opposite each other. A portion of the pin extends into the space between the first substrate 10 and the second substrate 20 and is connected to the second substrate 20 by soldering to achieve electrical connection with the integrated circuit 30. Of course, the number and position of the pins can be adjusted according to actual needs.
[0047] See also Figure 2 As shown, after the integrated circuit 30 and the pins are soldered and the first substrate 10 and second substrate 20 are assembled, a plastic package 50 is used to encapsulate the structure. Specifically, the plastic package 50 covers the integrated circuit 30, the first substrate 10, the second substrate 20, the space between the first substrate 10 and the second substrate 20, and the pins. At least a portion of the upper surface of the first substrate 10 and at least a portion of the lower surface of the second substrate 20 are exposed from the plastic package 50 to enhance heat dissipation. The second pins 42 on the second side of the plastic package 50 are, for example, power pins. That is, in this package structure, the power pins are located on the same side of the plastic package and are arranged opposite the other pins.
[0048] Although the packaging structure of the first embodiment has the first boss 11 , the first groove 21 , the support column 12 and the second groove 22 , according to actual needs, the packaging structure can also achieve its double-sided heat dissipation function when it is designed with only the first boss 11 .
[0049] Figure 3 A schematic top view of the packaging structure of the second embodiment of the present invention is shown; the second embodiment is similar to the first embodiment, and differs from the first embodiment only in structures such as the substrate and support columns. In the packaging structure of the second embodiment, the widths of the plastic package body 50 and the first substrate 10 are, for example, greater than those of the first embodiment.
[0050] See also Figure 4The schematic diagram of the combination of two substrates in the packaging structure of the second embodiment is shown. Although the first substrate 10 and the second substrate 20 in the second embodiment are both rectangular, their length and width dimensions are different, so as to better distinguish the two and avoid confusion between the two during production and assembly.
[0051] Figure 5 and Figure 6 Schematic diagrams of the first substrate 10 and the second substrate 20 in the packaging structure of the second embodiment are shown respectively. As can be seen from the two figures, compared with the first embodiment, the first substrate 10 in the second embodiment includes a total of 6 support pillars 12. In addition to the four support pillars 12 at the four corners, two support pillars 12 are provided in the middle of the four first bosses 11 in the 2*2 rectangular array. The two support pillars 12 are arranged in a row parallel to the side of the first substrate 10, dividing the entire first substrate 10 into two left and right areas. Figure 7 By adding a support column 12 in the middle of the first substrate 10, the left and right sides of the first boss 11 (integrated circuit 30) are provided with support columns 12. The four corners and the middle area of the package structure can all be effectively supported, better protecting the integrated circuit 30 between the two substrates and enhancing the overall strength of the package structure. Figure 5 As can be seen in the figure, barrier layers 111 are provided on the sides of the four first bosses 11 of the first substrate 10 to prevent tip discharge. Furthermore, the first bosses 11 and the support pillars 12 are, for example, integrally formed with the first substrate 10. The integral structure of the first bosses 11 and the first substrate 10 can solve the problem of easy displacement and complex process of setting bosses on integrated circuits in traditional structures, without having to consider issues such as soldering and anti-oxidation of the bosses. The integral structure of the support pillars 12 and the first substrate 10 can reduce the cumbersome process flow and directly achieve the support effect.
[0052] Furthermore, the six support pillars 12 in the second embodiment are merely exemplary. Depending on actual conditions and requirements, the number of support pillars 12 may be 2 to 8, and their positions and layouts may be adjusted based on the number of support pillars 12. Correspondingly, the number and layout of the integrated circuit 30, the first boss 11, the first recess 21, and the second recess 22 may also be adjusted based on requirements.
[0053] See also Figure 6 The first groove 21 on the second substrate 20 corresponds to the first boss 11, and the second groove 22 on the second substrate 20 corresponds to the support column 12. Therefore, the arrangement of the first groove 21 and the second groove 22 on the second substrate 20 in the second embodiment will not be described in detail.
[0054] Although the first boss 11 and the support column 12 in the second embodiment are an integral structure with the first substrate 10, according to actual needs, the first boss 11 and the support column 12 can be an integral structure with either the first substrate 10 or the second substrate 20, and the corresponding first groove 21 and second groove 22 are located on the other of the first substrate 10 and the second substrate 20.
[0055] Figure 8 A top view of the combination of the first substrate and the second substrate in the packaging structure of the second embodiment of the present invention is shown; the size of the first substrate 10 in the x-direction is, for example, larger than that of the second substrate 20, and the size of the second substrate 20 in the y-direction is, for example, larger than that of the first substrate 10, and pins (not shown in the figure) extend respectively from the first side (upper side) and the second side (lower side) of the second substrate 20 that are not covered by the first substrate 10.
[0056] Figure 9 The packaging structure of the second embodiment of the present invention is shown along Figure 8 Schematic diagram of the cross section of the AA line; Figure 9 It can be seen that the center points of the four first bosses 11 of the array on the first substrate 10 are not located at the center of the first substrate 10. The center points of the four first bosses 11 of the array are closer to the upper side of the first substrate 10. This asymmetric design makes it easy to distinguish the direction of the first substrate 10.
[0057] Figure 10 The packaging structure of the second embodiment of the present invention is shown along Figure 8 A cross-sectional view taken along line BB. The integrated circuit 30 is at least partially embedded in the first recess 21 of the second substrate 20. Support structures (support pillars 12) are located on both sides of the integrated circuit 30. The integrated circuit 30 is secured by the first protrusion 11 of the first substrate 10. The sides of the first protrusion 11 are coated with a barrier layer 111 to prevent sharp discharges at the side edges of the first protrusion 11 under high voltage conditions, thereby preventing damage to the package structure.
[0058] Of course, the design of coating the barrier layer 111 on the side surface of the first boss 11 can also be applied to other packaging structures with boss structures.
[0059] The packaging structure provided by the utility model adopts a first substrate and a second substrate to form a clamping structure to fix the integrated circuit. The integrated circuit can achieve double-sided heat dissipation through the substrates on both sides, thereby achieving a better heat dissipation effect.
[0060] Furthermore, a barrier layer is coated on the side of the first boss connected to the integrated circuit, which can effectively avoid the breakdown problem caused by tip discharge under high current and high voltage conditions, thereby enhancing the reliability of the packaging structure.
[0061] Furthermore, by supporting the space between the two substrates with the support pillars, the integrated circuit (eg, IGBT, FRD, MOSFET, driver chip) can be effectively prevented from being crushed by the first boss.
[0062] Furthermore, the first boss and one of the substrates are an integrated structure, which can solve the problem of easy displacement and complicated process of setting the first boss on the integrated circuit in the traditional structure, and there is no need to consider the welding and anti-oxidation issues of the first boss; the support column and one of the substrates are an integrated structure, which can reduce the cumbersome process flow and directly achieve the support effect.
[0063] This packaging structure is low-cost and compact, and also has a double-sided heat dissipation design, which can effectively avoid the breakdown problem caused by tip discharge under high current and high voltage conditions, and is better suitable for high-power and high-heat scenarios.
[0064] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.
[0065] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A packaging structure, characterized in that: include: a first substrate and a second substrate arranged opposite to each other; an integrated circuit, located between the first substrate and the second substrate; a pin connected to one of the first substrate and the second substrate and electrically connected to the integrated circuit; One of the first substrate and the second substrate is provided with a first boss, the first boss faces the other of the first substrate and the second substrate and corresponds to the integrated circuit; and a side surface of the first boss is coated with a barrier layer.
2. The packaging structure according to claim 1, wherein: The other of the first substrate and the second substrate is further provided with a first groove corresponding to the first boss, and the integrated circuit is located in the first groove.
3. The packaging structure according to claim 2, wherein: One of the first substrate and the second substrate is further provided with a support column facing the other substrate.
4. The packaging structure according to claim 3, wherein: The other of the first substrate and the second substrate is provided with a second groove, and the second groove corresponds to the supporting column.
5. The packaging structure according to claim 1, wherein: The integrated circuit includes at least one of an IGBT, an FRD, a MOSFET, and a driver chip.
6. The packaging structure according to claim 1, wherein: The barrier layer is a nonlinear electric field gradient material layer with a thickness of 0.1 mm to 0.3 mm.
7. The packaging structure according to claim 6, wherein: The barrier layer includes one or a combination of multiple layers selected from the group consisting of a ZnO layer, a BaTiO3 layer, a SiO2 layer, a TiO2 layer, and a Fe3O4 layer.
8. The packaging structure according to claim 3, wherein: One of the first substrate and the second substrate and the first boss are an integrated structure; one of the first substrate and the second substrate and the support column are an integrated structure.
9. The packaging structure according to claim 1, wherein: The first substrate and the second substrate are both copper-clad ceramic substrates.
10. The packaging structure according to claim 2, wherein: The depth of the first groove is 15% to 20% of the thickness of the integrated circuit.
11. The packaging structure according to claim 3, wherein: The diameter of the support column is 15% to 20% of the length of the packaging structure.
12. The packaging structure according to claim 4, wherein: The sum of the difference between the thickness of the integrated circuit and the depth of the first groove and the height of the first boss is no greater than the difference between the height of the support pillar and the depth of the second groove.
13. The packaging structure according to claim 1, wherein: Solder pads are also provided on both side surfaces of the integrated circuit.
14. The packaging structure according to claim 1, wherein: It also includes a plastic package, which covers the integrated circuit, the first substrate, the second substrate, the space between the first substrate and the second substrate, and part of the pins.
15. The packaging structure according to claim 14, wherein: The pins extend from two opposite sides of the plastic package body. The pins include power pins, and the power pins are located on the same side of the plastic package body.
16. The packaging structure according to claim 14, wherein: At least part of the surfaces of the first substrate and the second substrate are exposed from the plastic package body.
17. The packaging structure according to claim 4, wherein: The cross-sectional dimensions of the first boss match those of the integrated circuit, and the cross-sectional shape of the first boss includes any one of circular, triangular, and rectangular shapes.
18. The packaging structure according to claim 1, wherein: The size of the first substrate is the same as or different from the size of the second substrate.
19. The packaging structure according to claim 4, wherein: The first boss and the supporting column are located on the first substrate, and the first groove and the second groove are both located on the second substrate.
20. The packaging structure according to claim 4, wherein: There are at least two second grooves, and the two second grooves are respectively located on two sides of the integrated circuit.
21. The packaging structure according to claim 19, wherein: The first substrate and the second substrate are both rectangular, the second grooves include at least four, and the four second grooves are respectively located at the four corners of the second substrate. The first grooves include four, and the four first grooves are arrayed in the middle area of the second substrate.