Chip packaging structure and half-bridge module of inverter
By integrating SiC chips and IGBT chips into the same busbar and using electrochemical plating and groove design, the problems of many parts, complex processes and inconvenient wiring in inverter circuit board manufacturing are solved, and the stability and performance of the chip unit are achieved.
Patent Information
- Application Number
- CN202422602984.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-10-28
AI Technical Summary
In the prior art, different types of chips, such as SiC chips and IGBT chips, are packaged separately, resulting in a large number of parts, complex processes, and inconvenient wiring during the manufacturing process of the inverter circuit board.
Different types of chip units, such as SiC chips and IGBT chips, are integrated and embedded in the same busbar. By setting chip slots and channels on the busbar, the chip units are fixed using electrochemical plating and fixed in the chip slots through a one-time sintering process, simplifying the manufacturing process.
It achieves stable integration of chip units, simplifies the circuit board manufacturing process, reduces the number of parts and wiring complexity, and absorbs thermal expansion, avoiding thermal coupling and interference between chip units, ensuring stable performance.
Smart Images
Figure CN223333799U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of automobile parts, in particular to a chip packaging structure and a half-bridge module of an inverter. Background Art
[0002] Different types of chips are needed in automotive components such as inverters. Currently, these chips are typically packaged separately, making it difficult to manufacture circuit boards for these components.
[0003] Taking the inverter as an example, in order to adapt to different load conditions such as high voltage (typically 800V) and low voltage (typically 400V), silicon carbide (SiC) chips and insulated gate bipolar transistor (IGBT) chips are usually arranged in parallel in high-quality inverters to fully utilize the high-voltage resistance and other characteristics of SiC chips and the low power consumption and other characteristics of IGBT chips to improve the performance of the inverter and reduce costs.
[0004] At present, different types of chips such as SiC chips and IGBT chips are packaged separately. In the process of manufacturing inverter circuit boards, there are problems such as a large number of parts, complex processes, and inconvenient wiring.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Utility Model Content
[0006] In view of this, the utility model provides a chip packaging structure and a half-bridge module for an inverter, which can integrate and embed different types of chip units into the same busbar to facilitate subsequent circuit board manufacturing and solve problems such as a large number of parts, complex processes, and inconvenient wiring in the circuit board manufacturing process of automotive parts such as inverters.
[0007] According to one aspect of the present invention, a chip packaging structure is provided, comprising: a busbar, on which a plurality of chip slots are provided; a plurality of chip units, respectively embedded in the plurality of chip slots, the plurality of chip units including at least two different types of chip units; wherein an electrochemical plating layer is provided at the bottom of the chip slot, and the chip unit includes a conductive layer, a chip body and a DTS layer sequentially stacked on the electrochemical plating layer; and a groove, provided on the busbar, located between adjacent chip slots.
[0008] In some embodiments, the length of the groove is equal to the length of the chip slot, and / or the width of the groove is between 1 / 3 and 1 / 2 of the spacing between adjacent chip slots, and / or the depth of the groove is greater than the depth of the chip slot.
[0009] In some embodiments, the length L of the groove satisfies: 7mm≤L≤8mm, and / or the width W of the groove satisfies: 1mm≤W≤1.5mm, and / or the depth D of the groove satisfies: 0.25mm≤D≤0.5mm.
[0010] In some embodiments, a projected area of the electrochemical plating layer at the bottom of the chip slot is larger than a projected area of the chip unit at the bottom of the chip slot, and the electrochemical plating layer is spaced apart from a peripheral wall of the chip slot.
[0011] In some embodiments, the spacing S1 between the chip unit and the peripheral wall of the chip slot satisfies: 0.5 mm ≤ S1 ≤ 1 mm, and / or the distance S2 from the edge of the electrochemical plating layer beyond the edge of the chip unit satisfies: 5 μm ≤ S2 ≤ 10 μm.
[0012] In some embodiments, the thickness of the electrochemical plating layer is 5 μm to 10 μm, and / or the thickness of the conductive layer is 40 μm to 60 μm, and / or the thickness of the chip body is 180 μm, and / or the thickness of the DTS layer is 40 μm to 50 μm.
[0013] In some embodiments, the chip units on the busbar include a SiC chip unit and an IGBT chip unit; wherein the gate and source of the SiC chip unit and the IGBT chip unit are formed on the front side, and the drain is formed on the back side, and the SiC chip unit and the IGBT chip unit share the busbar as a drain.
[0014] According to another aspect of the present invention, a half-bridge module of an inverter is provided, comprising: a circuit board; two chip packaging structures as described in any of the above embodiments, embedded in the circuit board, wherein a transistor chip unit is embedded in each of the chip packaging structures; electrode lead lines, comprising a source lead line connected to the source of the transistor chip unit of the first chip packaging structure, a gate lead line respectively connected to the gate of the transistor chip unit of the first chip packaging structure and the gate of the transistor chip unit of the second chip packaging structure, a series lead line connecting the drain of the transistor chip unit of the first chip packaging structure and the source of the transistor chip unit of the second chip packaging structure in series, and a drain lead line connected to the drain of the transistor chip unit of the second chip packaging structure.
[0015] In some embodiments, each busbar of the chip packaging structure is formed with a step portion.
[0016] Compared with the prior art, the beneficial effects of the present invention include at least:
[0017] The chip packaging structure of the utility model embeds multiple chip units into the same busbar, wherein two different types of chip units, such as a SiC chip unit and an IGBT chip unit, are integrated and embedded into the same busbar, thereby facilitating subsequent circuit board manufacturing and solving problems such as the large number of parts, complex processes, and inconvenient wiring in the circuit board manufacturing process of automotive parts such as inverters.
[0018] In addition, the chip packaging structure of the present invention sets grooves between adjacent chip slots of the busbar. The grooves can absorb the thermal expansion of the busbar caused by the heat generated by the chip units during operation, and can reduce the thermal coupling between the chip units, avoid mutual interference between the chip units, and ensure that the chip units are firmly positioned and have stable performance.
[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0021] Figure 1 A schematic diagram showing a three-dimensional structure of a chip packaging structure in an embodiment of the present invention is shown;
[0022] Figure 2 A schematic diagram showing a partial explosion structure of a chip packaging structure in an embodiment of the present invention is shown;
[0023] Figure 3 A schematic diagram of a partial cross-sectional structure of a chip packaging structure in an embodiment of the present invention is shown;
[0024] Figure 4 A schematic top view of another chip packaging structure according to an embodiment of the present invention is shown;
[0025] Figure 5 A schematic diagram showing the chip packaging structure during the sintering process in an embodiment of the present invention;
[0026] Figure 6 A schematic cross-sectional view of a half-bridge module of an inverter in an embodiment of the present invention is shown. DETAILED DESCRIPTION
[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art.
[0028] The accompanying drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and their repeated description will be omitted.
[0029] The terms "first", "second" and similar words used in the specific description do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms "upper", "lower", "front", "back" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention. The term "plurality" means two or more, unless otherwise clearly and specifically defined. In addition, in the description of the present invention, when it is said that a device is "connected" to another device, this includes not only direct connections, but also indirect connections through other elements.
[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in different embodiments may be combined with each other.
[0031] Figure 1 A three-dimensional structure of a chip packaging structure is shown. Figure 2 The local explosion structure of the chip packaging structure is shown. Figure 3 The partial cross-sectional structure of the chip packaging structure is shown. Figure 4 A top view of another chip packaging structure is shown; Figures 1 to 4 As shown, the chip packaging structure provided by the embodiment of the present invention includes:
[0032] A busbar 10 is provided with a plurality of chip slots 11;
[0033] A plurality of chip units 20 are respectively embedded in the plurality of chip slots 11, and the plurality of chip units 20 include at least two different types of chip units;
[0034] The bottom of the chip slot 11 is provided with an electrochemical plating layer 110, and the chip unit 20 includes a conductive layer 21, a chip body 22 and a DTS layer 23 sequentially stacked on the electrochemical plating layer 110;
[0035] The slots 12 are provided on the busbar 10 and are located between adjacent chip slots 11 .
[0036] Busbar 10 is, for example, a copper busbar. Electrochemical plating layer 110 forms a metal deposit at the bottom of chip slot 11 primarily through an electrochemical reaction. Conductive layer 21 may be a silver film. Chip body 22 includes an insulating layer and electrodes attached to the insulating layer, such as a gate, source, and drain. The DTS (Die Top System) layer 23 is formed using die top system technology and includes a copper sheet and a pre-coated silver layer attached to the copper sheet.
[0037] Figure 1 and Figure 4 In the figure, three chip units 20 are shown on the busbar 10, but the present invention is not limited thereto. According to different design requirements, the number, size, type, etc. of the chip units 20 integrated on the busbar 10 can be adjusted as needed.
[0038] The chip packaging structure of the present invention embeds multiple chip units 20 into the same busbar 10, where two different types of chip units include, for example, a SiC chip unit 20a and an IGBT chip unit 20b. In this way, different types of chip units 20 are integrated and embedded into the same busbar 10, facilitating subsequent circuit board manufacturing and solving problems such as a large number of parts, complex processes, and inconvenient wiring in the circuit board manufacturing process of automotive parts such as inverters.
[0039] In addition, the chip packaging structure of the present invention is provided with a groove 12 between adjacent chip slots 11 of the busbar 10. The groove 12 can absorb the thermal expansion of the busbar 10 caused by the heat generated by the chip unit 20 during operation, and can reduce the thermal coupling between the chip units 20, avoid mutual interference between the chip units 20, and ensure that the chip units 20 are firmly positioned and have stable performance.
[0040] In some embodiments, the length of the groove 12 is equal to the length of the chip groove 11, and / or the width of the groove 12 is between 1 / 3 and 1 / 2 of the spacing between adjacent chip grooves 11, and / or the depth of the groove 12 is greater than the depth of the chip groove 11.
[0041] The length, width and depth of the groove 12 are designed to ensure that the groove 12 can stably absorb thermal expansion and reduce thermal coupling.
[0042] In some embodiments, the length of the groove 12 (set as L) satisfies: 7mm≤L≤8mm, for example, the length L of the groove 12 is 7mm, 7.6mm, 8mm, and the like; and / or, the width of the groove 12 (set as W) satisfies: 1mm≤W≤1.5mm, for example, the width W of the groove 12 is 1mm, 1.2mm, 1.5mm, and the like; and / or, the depth of the groove 12 (set as D) satisfies: 0.25mm≤D≤0.5mm, for example, the depth D of the groove 12 is 0.25mm, 0.38mm, 0.5mm, and the like.
[0043] In some embodiments, the projected area of the electrochemical plating layer 110 at the bottom of the chip slot 11 is larger than the projected area of the chip unit 20 at the bottom of the chip slot 11 , and the electrochemical plating layer 110 is spaced apart from the peripheral wall of the chip slot 11 .
[0044] The electrochemical plating layer 110 serves as a transitional layer during the sintering process of the chip unit 20. By ensuring that the projected area of the electrochemical plating layer 110 is larger than that of the chip unit 20 and that the electrochemical plating layer 110 is spaced from the peripheral wall of the chip slot 11, the chip unit 20 can be sintered and fixed in the chip slot 11 while preventing the electrochemical plating layer 110 from contacting the peripheral wall of the chip slot 11 and causing a short circuit.
[0045] In some embodiments, the spacing S1 between the chip unit 20 and the peripheral wall of the chip slot 11 satisfies: 0.5mm≤S1≤1mm, and / or the distance S2 from the edge of the electrochemical plating layer 110 beyond the edge of the chip unit 20 satisfies: 5μm≤S2≤10μm.
[0046] In this way, the projected area of the electrochemical plating layer 110 is larger than the projected area of the chip unit 20, and the electrochemical plating layer 110 is spaced apart from the peripheral wall of the chip slot 11. The spacing S1 between the chip unit 20 and the peripheral wall of the chip slot 11 is, for example, 0.5 mm, 0.7 mm, 1 mm, etc.; the distance S2 from the edge of the electrochemical plating layer 110 beyond the edge of the chip unit 20 is, for example, 5 μm, 8 μm, 10 μm, etc.
[0047] In some embodiments, the thickness of the electrochemical plating layer 110 is 5 μm to 10 μm, and / or the thickness of the conductive layer 21 is 40 μm to 60 μm, and / or the thickness of the chip body 22 is 180 μm, and / or the thickness of the DTS layer 23 is 40 μm to 50 μm.
[0048] For example, the thickness of the electrochemical plating layer 110 is 10 μm, the thickness of the conductive layer 21 is 50 μm, and the thickness of the DTS layer 23 is 50 μm, but the thickness is not limited to this. The thicknesses of the electrochemical plating layer 110, the conductive layer 21, the chip body 22, the DTS layer 23, and other layers can be adjusted appropriately according to different process technologies and performance requirements.
[0049] Furthermore, a conductive layer 21 may be stacked between the DTS layer 23 and the chip body 22; or the conductive layer and the DTS layer 23 may be combined into one.
[0050] Reference Figure 4 As shown, in some embodiments, the different types of chip units on the busbar 10 include a SiC chip unit 20a and an IGBT chip unit 20b, and may also include a diode chip 20c; wherein the gate and source of the SiC chip unit 20a and the IGBT chip unit 20b are both formed on the front side, and the drain is both formed on the back side, and the SiC chip unit 20a and the IGBT chip unit 20b share the busbar 10 as the drain.
[0051] In other embodiments, the chip unit 20 on the busbar 10 may also include any other semiconductor chip, a silicon-based chip, multiple SiC chips, multiple IGBT chips, etc. In addition, the gate, source, and drain of the chip unit 20 can be formed on the front side / back side of the chip unit 20 according to design requirements.
[0052] The manufacturing process of the chip package structure described in the above embodiment may include:
[0053] A plurality of chip slots 11 and channels 12 are provided on the busbar 10, wherein the channels 12 are located between adjacent chip slots 11;
[0054] forming an electrochemical plating layer 110 at the bottom of the chip slot 11;
[0055] The conductive layer 21, the chip body 22 and the DTS layer 23 of the chip unit 20 are sequentially stacked on the electrochemical plating layer 110;
[0056] The chip unit 20 and the busbar 10 are sintered once to form a chip packaging structure.
[0057] Traditionally, sintering and securing the chip unit 20 to the substrate requires at least two sintering processes, typically including stacking, sintering, restacking, and restintering. In the present invention, after forming an electrochemical plating layer 110 at the bottom of the chip slot 11, the stacked structure required to compose the chip unit 20, including the conductive layer 21, the chip body 22, and the DTS layer 23, is first stacked on the electrochemical plating layer 110. The chip unit 20 and busbar 10 are then sintered once, securing the chip unit 20 in the chip slot 11 in one sintering step. This reduces the number of sintering steps, simplifies the process flow, and prevents damage to some of the film layers of the chip unit 20 from repeated pressure and heat.
[0058] The primary sintering pressure is controlled between 20 MPa and 25 MPa, and the temperature is controlled between 200° C. and 250° C. For example, the primary sintering pressure is 25 MPa and the temperature is 200° C., but this is not limiting. By controlling the pressure and temperature of the primary sintering process, the chip unit 20 is ensured to be fixed in the chip slot 11 after the primary sintering.
[0059] Figure 5 The structure of the chip package structure during the sintering process is schematically shown; combined with Figures 1 to 5 As shown, in some embodiments, during a single sintering process, a buffer press (including an insulating buffer sheet 61 and a press 62) is pressed onto the chip unit 20 and the busbar 10. This ensures that the upper surface of the chip unit 20 is flush with the upper surface of the busbar 10 after sintering, facilitating the subsequent embedding of the chip package structure into the circuit board.
[0060] An embodiment of the present invention further provides a half-bridge module of an inverter, which is implemented based on the chip packaging structure described in any of the above embodiments. Figure 6 The cross-sectional structure of the inverter half-bridge module is shown; combined with Figures 1 to 6 As shown, the half-bridge module of the inverter provided by the embodiment of the present invention includes:
[0061] Circuit board 70;
[0062] A chip packaging structure is embedded in the circuit board 70, wherein each chip packaging structure has a transistor chip unit 20' embedded therein;
[0063] The electrode lead lines include a source lead line 81 connected to the source of the transistor chip unit 20' of the first chip package structure 100a, a gate lead line 82 respectively connected to the gate of the transistor chip unit 20' of the first chip package structure 100a and the gate of the transistor chip unit 20' of the second chip package structure 100b, a series lead line 83 connected in series between the drain of the transistor chip unit 20' of the first chip package structure 100a and the source of the transistor chip unit 20' of the second chip package structure 100b, and a drain lead line 84 connected to the drain of the transistor chip unit 20' of the second chip package structure 100b.
[0064] By embedding the chip packaging structure in the circuit board 70 , the conductive layer, insulating layer and other structures of the circuit board 70 can be utilized to reduce inductance, and a drive circuit layout area can be reserved on the surface of the circuit board 70 .
[0065] The transistor chip unit 20' includes, for example, a SiC chip unit and an IGBT chip unit. The SiC chip unit and the IGBT chip unit are connected to different drive circuits, respectively, so that the SiC chip unit and / or the IGBT chip unit can be controlled to operate individually or together under different operating conditions. For example, when the inverter needs to operate under full load, the SiC chip unit and the IGBT chip unit can be controlled to operate together; when the inverter needs to be connected to 800V high-voltage direct current, the SiC chip unit can be controlled to operate; and when the inverter is connected to 400V low-voltage direct current, the IGBT chip unit can be controlled to operate.
[0066] In some embodiments, each busbar 10 of the chip package structure is formed with a step portion 100. The step portion 100 increases the contact area between the busbar 10 and the circuit board 70 and stabilizes the assembly of the busbar 10 and the circuit board 70.
[0067] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: A busbar, wherein a plurality of chip slots are provided on the busbar; A plurality of chip units are respectively embedded in the plurality of chip slots, wherein the plurality of chip units include at least two different types of chip units; The bottom of the chip slot is provided with an electrochemical plating layer, and the chip unit comprises a conductive layer, a chip body and a DTS layer sequentially stacked on the electrochemical plating layer; The groove is arranged on the busbar and located between adjacent chip slots.
2. The chip packaging structure according to claim 1, wherein: The length of the groove is equal to the length of the chip slot, and / or the width of the groove is between 1 / 3 and 1 / 2 of the spacing between adjacent chip slots, and / or the depth of the groove is greater than the depth of the chip slot.
3. The chip packaging structure according to claim 2, wherein: The length L of the groove satisfies: 7 mm ≤ L ≤ 8 mm, and / or the width W of the groove satisfies: 1 mm ≤ W ≤ 1.5 mm, and / or the depth D of the groove satisfies: 0.25 mm ≤ D ≤ 0.5 mm.
4. The chip packaging structure according to claim 1, wherein: The projected area of the electrochemical plating layer at the bottom of the chip slot is larger than the projected area of the chip unit at the bottom of the chip slot, and the electrochemical plating layer is spaced apart from the peripheral wall of the chip slot.
5. The chip packaging structure according to claim 4, wherein: A distance S1 between the chip unit and the peripheral wall of the chip slot satisfies: 0.5 mm ≤ S1 ≤ 1 mm, and / or a distance S2 from the edge of the electrochemical plating layer beyond the edge of the chip unit satisfies: 5 μm ≤ S2 ≤ 10 μm.
6. The chip packaging structure according to claim 1, wherein: The thickness of the electrochemical plating layer is 5 μm to 10 μm, and / or the thickness of the conductive layer is 40 μm to 60 μm, and / or the thickness of the chip body is 180 μm, and / or the thickness of the DTS layer is 40 μm to 50 μm.
7. The chip packaging structure according to any one of claims 1 to 6, wherein: The chip units on the busbar include SiC chip units and IGBT chip units; The gate and source of the SiC chip unit and the IGBT chip unit are both formed on the front side, and the drain is both formed on the back side, and the SiC chip unit and the IGBT chip unit share the busbar as the drain.
8. A half-bridge module of an inverter, characterized in that: include: circuit boards; Two chip packaging structures according to any one of claims 1 to 7, embedded in the circuit board, wherein a transistor chip unit is embedded in each of the chip packaging structures; The electrode lead wires include a source lead wire connected to the source of the transistor chip unit of the first chip packaging structure, a gate lead wire connected to the gate of the transistor chip unit of the first chip packaging structure and the gate of the transistor chip unit of the second chip packaging structure respectively, a series lead wire connected in series to the drain of the transistor chip unit of the first chip packaging structure and the source of the transistor chip unit of the second chip packaging structure, and a drain lead wire connected to the drain of the transistor chip unit of the second chip packaging structure.
9. The half-bridge module according to claim 8, characterized in that: A step portion is formed on each busbar of the chip packaging structure.