Quantum chip packaging device

Abstract

The utility model provides a quantum chip packaging device. The quantum chip packaging device comprises a top sealing element and a lower sealing element, an upper cavity is formed in the end surface of the top sealing element close to the lower sealing element; the end face, close to the top sealing piece, of the lower sealing piece is provided with a lower cavity, and the upper cavity is communicated with the lower cavity and used for packaging the quantum chip. According to the quantum chip packaging device disclosed by the invention, a resonant cavity mode with relatively low frequency can be avoided, low-frequency resonant frequency can be eliminated in the packaging device, the processing difficulty and the processing cost of the whole mechanical structure and a circuit board in the packaging device can be reduced, and the packaging efficiency is improved. In the engineering design and analysis process, the resonant frequency problem can be processed more simply, implementation and verification are easier, standardized and large-scale production can be achieved, cost and resources are saved, and the manufacturing efficiency and consistency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum chips, and in particular to a quantum chip packaging device. Background Art

[0002] Various electromagnetic resonances can interfere with the quantum chip and the packaging device. It's important to minimize and prevent the impact of the packaging device's inherent resonant modes on the coherence of the qubit. Because the quantum chip is encapsulated in a closed cavity, the cavity has intrinsic resonant modes. If the cavity's resonant frequency is near the qubit's operating frequency, this can create strong coupling between the packaging device and the qubit, causing interference to the qubit.

[0003] The existing technical solutions for eliminating low-frequency resonant frequencies in quantum chip packaging devices have problems such as difficulty in processing and manufacturing, high cost, and difficulty in mass production. Utility Model Content

[0004] To solve the above technical problems, the present disclosure provides a quantum chip packaging device, comprising a top seal and a bottom seal; the top seal has an upper cavity on an end surface close to the bottom seal;

[0005] The end surface of the lower seal close to the top seal has a lower cavity, and the upper cavity and the lower cavity are communicated with each other for packaging quantum chips;

[0006] A lower isolating member is provided in the lower cavity, and the lower isolating member divides the lower cavity into a plurality of cavities.

[0007] After the cavity used to encapsulate the quantum chip in the quantum chip packaging device is divided into multiple small cavities, the resonance effect of each small cavity will be relatively weak. Since the volume of the small cavity is relatively small, the resonance frequency of the cavity is effectively increased, making the resonance frequency higher than the operating frequency range of the quantum chip. This can reduce or eliminate the interference of the resonance generated in the cavity on the quantum chip, which is beneficial to improving the performance of the quantum chip.

[0008] Optionally, the lower isolating member is arranged on the bottom wall of the lower cavity, the height of the lower isolating member is smaller than the depth of the lower cavity, and a lower accommodating cavity is defined between the upper end surface of the lower isolating member and the end surface with an opening in the lower cavity.

[0009] In the quantum chip packaging device, the lower cavity is divided into multiple small cavities by the lower isolation member, thereby avoiding the resonant cavity mode of lower frequencies and eliminating the low-frequency resonant frequency in the packaging device.

[0010] Optionally, the end surface of the lower seal close to the top seal has a plurality of cluster interconnect packaging areas;

[0011] Each of the cluster interconnect packaging areas has the same structure and is used to package the same cluster interconnect.

[0012] The lower seal further includes a top seal packaging area, and a plurality of the cluster interconnect packaging areas are circumferentially arranged on an outer periphery of the top seal packaging area.

[0013] The structure of each cluster interconnect packaging area in the quantum chip packaging device is the same and is used to package the same cluster interconnect, which reduces the processing difficulty and cost of the overall mechanical structure of the quantum chip packaging device and the circuit board in the packaging device.

[0014] Optionally, the lower cavity is located at the center of the lower sealing member;

[0015] Each of the cluster interconnect packaging areas is located on the outer periphery of the lower cavity, and each of the cluster interconnect packaging areas is at the same distance from the lower cavity.

[0016] The shape and size of the clustered interconnects in the quantum chip packaging device are the same, and the length of the signal transmission lines can also be the same, which facilitates large-scale production and reduces production costs.

[0017] Optionally, an upper isolator is provided in the upper cavity, and the upper isolator is arranged on the top wall of the upper cavity, and the upper isolator divides the upper cavity into multiple cavities.

[0018] The quantum chip packaging device further reduces the size of each cavity, which is beneficial to eliminating low-frequency resonant frequencies within the packaging device.

[0019] Optionally, the height of the upper isolation member is less than the depth of the upper cavity, and an upper accommodating cavity is provided between the lower end surface of the upper isolation member and the end surface with an opening in the upper cavity. The upper accommodating cavity and the lower accommodating cavity are connected to form an accommodating chamber, and the accommodating chamber is used to encapsulate the quantum chip.

[0020] The quantum chip packaging device encapsulates the quantum chip in a containing chamber to facilitate the positioning and packaging of the quantum chip.

[0021] Optionally, an upper seal is further included, wherein an upper seal hole is provided in the middle of the upper seal and passes through in a vertical direction, and the upper seal hole is configured to correspond to the top seal, one end of the upper seal hole is connected to the upper cavity, and the other end of the upper seal hole is connected to the lower cavity.

[0022] The top seal in the quantum chip packaging device can pass through the upper seal hole to be connected with the lower seal, which facilitates the positioning and installation of the top seal.

[0023] Optionally, the upper seal is provided with upper seal positioning holes penetrating in a vertical direction, the upper seal positioning holes are configured to correspond to the cluster interconnection members, and each upper seal positioning hole corresponds to one of the cluster interconnection member packaging areas.

[0024] In the quantum chip packaging device, each cluster interconnection component is respectively arranged in the corresponding upper sealing component positioning hole to realize the positioning of each cluster interconnection component and the corresponding cluster interconnection component packaging area, which is conducive to improving the assembly efficiency of the quantum chip packaging device.

[0025] Optionally, a circuit board is further included, the circuit board is located between the top seal and the lower seal, and the circuit board is provided with a plurality of circuit board packaging areas;

[0026] The circuit board packaging area is adapted to the cluster interconnect packaging area.

[0027] The size of the circuit board packaging area in the quantum chip packaging device is the same as the size of the cluster interconnect packaging area, and each circuit board packaging area matches the position of the corresponding cluster interconnect packaging area, so that the cluster interconnect passes through the upper seal positioning hole and is packaged and connected with the circuit board and the lower seal, further reducing the processing and assembly difficulty of the packaging device and reducing costs.

[0028] Optionally, a packaging cavity is provided between the upper sealing member and the lower sealing member for packaging a circuit board;

[0029] The cluster interconnect passes through the upper seal positioning hole and is connected to the circuit board packaging area and the cluster interconnect packaging area. The top seal passes through the upper seal hole and is connected to the circuit board packaging area and the lower seal, so that the cluster interconnect is arranged around the periphery of the top seal packaging area.

[0030] In the quantum chip packaging device, the circuit board is packaged by upper and lower seals, which is beneficial to protecting the circuit board and quantum chip. In addition, the cluster interconnect and the top seal both pass through the upper seal and are connected to the circuit board and the lower seal, making the overall mechanical structure of the quantum chip packaging device more compact, which is conducive to miniaturization and mass production.

[0031] The technical effects and advantages of the present disclosure are as follows:

[0032] 1. In the quantum chip packaging device, by providing an isolator to divide the larger cavity in the seal into multiple smaller cavities, the low-frequency resonance frequency in the packaging device can be eliminated, and the processing difficulty and cost of the overall mechanical structure and the circuit board in the packaging device can be reduced.

[0033] 2. In the quantum chip packaging device, by setting up isolation parts to divide the large cavity into multiple small cavities, the stability of the structure can be improved and the reliability and durability of the overall system can be enhanced.

[0034] 3. In the quantum chip packaging device, a larger cavity is divided into multiple smaller cavities by setting up multiple isolation parts. During the engineering design and analysis process, the problem of resonant frequency can be handled more simply, which is easier to implement and verify. It can also be standardized and mass-produced, saving costs and resources, and helping to improve manufacturing efficiency and consistency.

[0035] 4. The structure of each cluster interconnect packaging area in the quantum chip packaging device is the same, and it is used to package the same cluster interconnect, which reduces the processing difficulty and cost of the overall mechanical structure and the circuit board in the packaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the structure of a quantum chip packaging device provided by an embodiment of the present disclosure;

[0037] Figure 2 is an exploded diagram of the structure of a quantum chip packaging device provided by an embodiment of the present disclosure;

[0038] Figure 3 1 is a schematic structural diagram of an upper sealing member in a quantum chip packaging device provided in one embodiment of the present disclosure;

[0039] Figure 4 1 is a schematic structural diagram of a lower sealing member in a quantum chip packaging device provided in one embodiment of the present disclosure;

[0040] Figure 5 1 is a schematic structural diagram of a top seal in a quantum chip packaging device provided in one embodiment of the present disclosure;

[0041] Figure 6 1 is a schematic structural diagram of a lower sealing member in a quantum chip packaging device provided in another embodiment of the present disclosure;

[0042] Figure 7 Schematic diagram of the structure of a top seal in a quantum chip packaging device provided by another embodiment of the present disclosure.

[0043] In the figure: 100, top seal; 110, upper cavity; 120, upper spacer; 121, third isolation protrusion; 122, fourth isolation protrusion; 123, seventh isolation protrusion; 124, eighth isolation protrusion; 130, upper accommodating cavity; 140, groove; 150, top seal fixing hole; 200, lower seal; 210, lower cavity; 220, lower spacer; 221, first isolation protrusion; 222, second isolation protrusion; 223, fifth isolation protrusion; 224, sixth isolation protrusion; 230, lower accommodating cavity; 233, boss; 231, first Two fixing holes; 232, first fixing hole; 240, positioning protrusion; 300, cluster interconnect packaging area; 310, third fixing hole; 320, lower seal connection groove; 400, cluster interconnect; 500, top seal packaging area; 600, upper seal; 610, upper seal hole; 620, upper seal positioning hole; 630, upper seal packaging hole; 700, circuit board; 710, circuit board packaging area; 711, circuit board cluster hole; 712, circuit board pad; 720, circuit board center hole; 730, circuit board packaging hole; 800, small chamber. DETAILED DESCRIPTION

[0044] The present disclosure is further described below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present disclosure are provided for purposes of illustration and description and are not intended to be exhaustive or to limit the present disclosure to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to better illustrate the principles and practical applications of the present disclosure and to enable those skilled in the art to understand the present disclosure and design various embodiments with various modifications suitable for specific applications.

[0045] In the existing technology, in order to eliminate the low-frequency resonant frequency in the quantum chip packaging device, there are problems such as processing and manufacturing difficulties, high costs, and difficulty in mass production.

[0046] The present disclosure provides a quantum chip packaging device comprising a top seal and a lower seal. The top seal has an upper cavity on its end surface near the lower seal, and the lower seal has a lower cavity on its end surface near the top seal. The upper and lower cavities are interconnected and are used to package the quantum chip. A lower separator is disposed within the lower cavity, dividing the lower cavity into multiple cavities.

[0047] The quantum chip packaging device disclosed herein can avoid lower-frequency resonant cavity modes, eliminate low-frequency resonant frequencies within the packaging device, and reduce the processing difficulty and cost of the overall mechanical structure and the circuit board within the packaging device. During engineering design and analysis, the problem of resonant frequency can be handled more simply, making it easier to implement and verify. It can also be standardized and mass-produced, saving costs and resources, and helping to improve manufacturing efficiency and consistency.

[0048] refer to Figure 1 and Figure 2 The present disclosure provides a quantum chip packaging device, comprising a top seal 100 and a bottom seal 200. The top seal 100 has an upper cavity 110 (such as Figure 5 As shown), the lower seal 200 has a lower cavity 210 (as shown) on the end surface close to the top seal. Figure 4 As shown), the upper cavity 110 and the lower cavity 210 are interconnected and are used to encapsulate quantum chips.

[0049] A lower isolation member 220 is provided in the lower cavity 210, and the lower isolation member 220 divides the lower cavity 210 into multiple cavities. Since the lower isolation member 220 divides a larger lower cavity 210 into multiple smaller cavities, there is no larger cavity in the entire packaging device, thereby avoiding a lower frequency resonant cavity membrane and eliminating the low-frequency resonant frequency in the packaging device.

[0050] It is understandable that the cavity has a resonant frequency, and a large cavity can easily form a strong resonance effect in the low-frequency range. By dividing the larger cavity into multiple small cavities, the resonance effect of each small cavity will be relatively weak. Since the volume of the small cavity is relatively small, the resonant frequency of the cavity is effectively increased, making the resonant frequency higher than the operating frequency range of the quantum chip, which can reduce or eliminate the interference of the resonance generated in the cavity on the quantum chip, and is beneficial to improving the performance of the quantum chip.

[0051] Dividing the quantum chip packaging device into multiple small cavities can increase the stability of the structure and reduce the structural instability caused by large-scale external vibrations, thereby improving the reliability and durability of the overall structure.

[0052] In some embodiments of the present disclosure, multiple small cavities are of the same size, and the resonant frequency of each small cavity is fixed and the same, which can accurately control and predict the resonant frequency, and can also effectively limit and weaken the low-frequency resonant frequency. At the same time, the same size of multiple small cavities can more simply handle the resonant frequency issue during engineering design and analysis, making it easier to implement and verify, and can be standardized and mass-produced, saving costs and resources, and helping to improve manufacturing efficiency and consistency.

[0053] refer to Figure 4In some embodiments of the present disclosure, lower isolator 220 includes a plurality of isolation grooves disposed on the bottom wall of lower cavity 210. The height of lower isolator 220 is less than the depth of lower cavity 210. A lower accommodating cavity 230 is disposed between the upper end surface of lower isolator 220 and the end surface of lower cavity 210 with an opening. Lower accommodating cavity 230 is configured to accommodate and encapsulate a quantum chip. The present disclosure does not limit the shape and height of lower isolator 220 as long as it is capable of separating lower cavity 210 and encapsulating a quantum chip.

[0054] Optionally, the lower isolation member 220 includes at least one first isolation protrusion 221 and at least one second isolation protrusion 222. The first isolation protrusion 221 and the second isolation protrusion 222 are fixed to the bottom wall of the lower cavity 210. In some embodiments of the present disclosure, the first isolation protrusion 221 and the second isolation protrusion 222 have the same height, and the heights of the first isolation protrusion 221 and the second isolation protrusion 222 are less than the depth of the lower cavity 210. Furthermore, the first isolation protrusion 221 and the second isolation protrusion 222 are arranged in a cross-arrangement, where the cross-arrangement means that the first isolation protrusion 221 and the second isolation protrusion 222 can be perpendicular to each other, and the intersection angle between the first isolation protrusion 221 and the second isolation protrusion 222 can also be non-90 degrees. The intersection angle between the first isolation protrusion 221 and the second isolation protrusion 222 can be sufficient to divide the lower cavity 210 into multiple smaller cavities, and the present disclosure is not limited to this.

[0055] refer to Figure 1 、 Figure 2 as well as Figure 3 The lower seal 200 (i.e., the first lower cover) has a plurality of cluster interconnect packaging areas 300 on the end surface close to the top seal 100. Each cluster interconnect packaging area 300 has the same size and structure and is used to package a plurality of identical cluster interconnects 400. At the same time, the lower seal 200 is also provided with a top seal packaging area 500, and the plurality of cluster interconnect packaging areas 300 are arranged around the periphery of the top seal packaging area 500. Specifically, as Figure 4 As shown, four cluster interconnect packaging areas 300 surround the periphery of a top seal packaging area 500 disposed at the center of the lower seal 200 .

[0056] Specifically, each cluster interconnect packaging area 300 includes an array of first fixing holes 232 and an array of lower seal connection slots 320. The first fixing holes 232 of each cluster interconnect packaging area 300 connect to the connector of the corresponding cluster interconnect 400, thereby packaging the cluster interconnect 400. Each lower seal connection slot 320 corresponds to and is electrically connected to each connector of the cluster interconnect 400. This allows each cluster interconnect packaging area 300 to package the same cluster interconnect 400, significantly reducing the manufacturing difficulty and cost of the circuit board 700 and the overall mechanical structure packaged within the quantum chip packaging device. Furthermore, the lower cavity 210 is located in the center of the lower seal 200, while each cluster interconnect packaging area 300 is located on the periphery of the lower cavity 210. Specifically, multiple cluster interconnect packaging areas 300 are arranged around the lower cavity 210, and each cluster interconnect packaging area 300 is the same distance from the lower cavity 210.

[0057] In some embodiments of the present disclosure, a boss 233 is provided on the end surface of the lower seal 200 close to the top seal 100 , and a second fixing hole 231 is provided at the edge of the boss 233 .

[0058] refer to Figure 1 and Figure 5 In some embodiments of the present disclosure, an upper isolation member 120 is provided in the upper cavity 110 of the top seal 100 (i.e., the chip top cover). The upper isolation member 120 is provided on the top wall of the upper cavity 110. The upper isolation member 120 divides the larger upper cavity 110 into multiple smaller cavities, further avoiding the lower frequency resonant cavity membrane and eliminating the low-frequency resonant frequency in the packaging device.

[0059] Optionally, the upper isolation member 120 includes at least one third isolation protrusion 121 and at least one fourth isolation protrusion 122. The third isolation protrusion 121 and the fourth isolation protrusion 122 are fixed to the top wall of the upper cavity 110. In some embodiments of the present disclosure, the third isolation protrusion 121 and the fourth isolation protrusion 122 have the same height. In other embodiments, the third isolation protrusion 121 and the fourth isolation protrusion 122 may have different heights. The third isolation protrusion 121 and the fourth isolation protrusion 122 are arranged in a cross-arrangement, where the cross-arrangement means that the third isolation protrusion 121 and the fourth isolation protrusion 122 can be perpendicular to each other, and the intersection angle between the third isolation protrusion 121 and the fourth isolation protrusion 122 can also be non-90 degrees. The intersection angle between the third isolation protrusion 121 and the fourth isolation protrusion 122 can be sufficient to divide the upper cavity 110 into multiple smaller cavities, and the present disclosure is not limited to this.

[0060] Continue to refer Figure 4 and Figure 5, the first isolation protrusion 221, the second isolation protrusion 222, the third isolation protrusion 121 and the fourth isolation protrusion 122 are all long strips. The first isolation protrusion 221 extends from one side wall of the lower cavity 210 to the opposite side wall, and the second isolation protrusion 222 extends from the adjacent side wall of the lower cavity 210 to the opposite side wall, dividing the lower cavity 210 into four small cavities. In other embodiments, the first isolation protrusion 221 and the second isolation protrusion 222 can be set to three, four, five, etc., so the number of small cavities separated is also increased accordingly. The third isolation protrusion 121 and the fourth isolation protrusion 122 in the upper cavity 110 are also set in the same way, which will not be repeated here.

[0061] refer to Figure 5 The upper isolator 120 includes a plurality of isolation grooves disposed on the top wall of the upper cavity 110. The height of the upper isolator 120 is less than the depth of the upper cavity 110. An upper accommodating cavity 130 is disposed between the lower end surface of the upper isolator 120 and the end surface of the upper cavity 110 having an opening. The upper accommodating cavity 130 is configured to accommodate and encapsulate a quantum chip. The present disclosure does not limit the shape and height of the upper isolator 120 as long as it is capable of separating the upper cavity 110 and encapsulating the quantum chip.

[0062] refer to Figure 2 and Figure 3 An upper sealing hole 610 is provided in the middle of the upper sealing member 600 and passes through in the vertical direction. The upper sealing hole 610 is configured to correspond to the top sealing member 100 and is used to position and fix the top sealing member 100. One end of the upper sealing hole 610 is connected to the upper cavity 110, and the other end of the upper sealing hole 610 is connected to the lower cavity 210.

[0063] Among them, the upper seal 600 includes a plurality of upper seal positioning holes 620 that penetrate along the vertical direction, and the plurality of upper seal positioning holes 620 are arranged around the periphery of the upper seal hole 610. The upper seal positioning holes 620 are configured to correspond to the cluster interconnect 400 and are used to position and fix the cluster interconnect 400, and each upper seal positioning hole 620 corresponds to a cluster interconnect packaging area 300 of the lower seal 200.

[0064] refer to Figure 2The quantum chip packaging device also includes a circuit board 700, which is located between the top seal 100 and the lower seal 200, and also between the upper seal 600 and the lower seal 200. A plurality of circuit board packaging areas 710 are provided on the circuit board 700, and the circuit board packaging areas 710 are adapted to the cluster interconnect packaging areas 300 of the lower seal 200. Specifically, the circuit board packaging areas 710 correspond to the positions and structures of the cluster interconnect packaging areas 300. The circuit board packaging areas 710 cooperate with the cluster interconnect packaging areas 300 to position and connect the cluster interconnect 400, so that the cluster interconnect 400 is connected to the quantum chip. The circuit board 700 may include a fan-out circuit board, and the present disclosure does not limit the type of circuit board.

[0065] Optionally, a packaging cavity is provided between the upper seal 600 and the lower seal 200 for packaging the circuit board 700. The cluster interconnect 400 passes through the upper seal positioning hole 620 and connects to the circuit board packaging area 710 and the cluster interconnect packaging area 300. The top seal 100 passes through the upper seal hole 610 and connects to the circuit board 700 and the top seal packaging area 500, so that the cluster interconnect 400 is disposed around the outer periphery of the top seal 100.

[0066] A central hole 720 is provided in the middle of the circuit board 700, corresponding to the packaging position of the quantum chip. The size of the central hole 720 is smaller than that of the upper seal hole 610. At the four corners of the central hole 720 are provided circuit board packaging holes 730, which match the top seal fixing holes 150, which are fixed holes provided at the four corners of the bottom of the top seal 100. The top cover seal 100 and the lower seal 200 cooperate to package the quantum chip. Specifically, the upper accommodating cavity 130 and the lower accommodating cavity 230 are connected to form a accommodating chamber, which can package the quantum chip.

[0067] In some embodiments of the present disclosure, the circuit board 700 has multiple circuit board packaging areas 710, which are adapted to the cluster interconnect packaging areas 300. The size of the circuit board packaging areas 710 is the same as the size of the cluster interconnect packaging areas 300, and the distance between each circuit board packaging area 710 and the center hole 720 of the circuit board is the same, so that each cluster interconnect 400 passes through the corresponding upper seal positioning hole 620 and is connected and packaged with the circuit board packaging area 710 and the cluster interconnect packaging area 300, which is conducive to reducing the difficulty of processing and assembly of the quantum chip packaging device and reducing costs.

[0068] In some embodiments of the present disclosure, each circuit board packaging area 710 includes arranged circuit board cluster holes 711 and circuit board pads 712 arranged in a matrix shape. The circuit board cluster holes 711 correspond one-to-one to the connectors at the bottom end of the cluster interconnect 400, and the circuit board pads 712 arranged in a matrix shape correspond one-to-one to the connectors arranged in a matrix shape in the cluster interconnect 400, which is conducive to welding the cluster interconnect 400 and the circuit board 700 together, and the circuit board pads 712 and the connectors of the cluster interconnect 400 are arranged neatly, further reducing the production and assembly difficulty of the circuit board 700 and the cluster interconnect 400, which is conducive to mass production and cost reduction.

[0069] In some embodiments of the present disclosure, a circuit board 700 is disposed on the lower seal 200, and an upper seal 600 is disposed on the lower seal 200. A packaging cavity is provided between the upper seal 600 and the lower seal 200, and the packaging cavity is used to encapsulate the circuit board 700. The lower seal 200 and the upper seal 600 are fixed to each other through the second fixing holes 231 and the upper seal packaging holes 630, thereby encapsulating the circuit board 700 between the upper seal 600 and the lower seal 200.

[0070] refer to Figure 3 The upper seal 600 is provided with a groove 140 adapted to the boss 233 on the end face close to the lower seal 200, and the groove wall of the groove 140 is provided with an upper seal packaging hole 630 adapted to the second fixing hole 231. The groove 140 cooperates with the boss 233 to facilitate the positioning of the upper seal 600 and the lower seal 200. The fastener passes through the upper seal packaging hole 630 and is fixed in the second fixing hole 231 to fix the lower seal 200 to the upper seal 600, which facilitates the packaging of the upper seal 600 and the lower seal 200.

[0071] In some embodiments of the present disclosure, the upper seal 600, the circuit board 700 and the lower seal 200 are all arranged in an octagon, wherein the upper seal positioning hole 620 is located at the four sides of the upper seal 600, the circuit board packaging area 710 is located at the four sides of the circuit board center hole 720, and the bundle interconnect packaging area 300 is located at the four sides of the lower cavity 210, and in the vertical direction, each upper seal positioning hole 620, circuit board packaging area 710 and bundle interconnect packaging area 300 are adapted to each other, so that the bundle interconnect 400 can pass through the upper seal positioning hole 620 to connect with the circuit board packaging area 710 and the bundle interconnect packaging area 300.

[0072] In some embodiments of the present disclosure, the upper cavity 110, the upper seal hole 610, the circuit board center hole 720 and the lower cavity 210 correspond to each other in the vertical direction, and the packaged top seal 100 passes through the upper seal hole 610 and is connected to the circuit board 700 and the lower seal 200.

[0073] In some embodiments of the present disclosure, the upper seal 600, the circuit board 700 and the lower seal 200 may also be configured as a quadrilateral, hexagonal, circular or polygonal structure according to actual needs to meet actual packaging requirements.

[0074] refer to Figure 6 and Figure 7 In other embodiments of the present disclosure, the lower isolation member 220 includes at least one fifth isolation protrusion 223 and at least one sixth isolation protrusion 224, the fifth isolation protrusion 223 and the sixth isolation protrusion 224 are fixed to the bottom wall of the lower cavity 210, the fifth isolation protrusion 223 and the sixth isolation protrusion 224 have the same height, and the height of the fifth isolation protrusion 223 and the sixth isolation protrusion 224 is less than the depth of the lower cavity 210, wherein the fifth isolation protrusion 223 and the sixth isolation protrusion 224 are both columnar structures.

[0075] In some embodiments of the present disclosure, one fifth isolation protrusion 223 is provided, and one fifth isolation protrusion 223 is located at the center of the lower cavity 210; four sixth isolation protrusions 224 are provided, and the four sixth isolation protrusions 224 are located at the four corners of the lower cavity 210, and the four sixth isolation protrusions 224 are arranged around the fifth isolation protrusion 223. Specifically, the four sixth isolation protrusions 224 are located on a concentric circle with the fifth isolation protrusion 223 as the center, and the distance between two adjacent sixth isolation protrusions 224 is the same, so that the small chamber 800 formed between a fifth isolation protrusion 223, two adjacent sixth isolation protrusions 224 and the side wall of the lower cavity 210 close to the two sixth isolation protrusions 224 are all the same size, thereby dividing the lower cavity 210 from an overall large cavity into multiple small cavities, avoiding lower frequency resonant cavity modes, and eliminating low-frequency resonant frequencies in the quantum chip packaging device. During the engineering design and analysis process, the resonant frequency problem can be handled more simply, is easier to implement and verify, can be standardized and mass-produced, saves costs and resources, and helps to improve manufacturing efficiency and consistency.

[0076] In some embodiments of the present disclosure, the lower seal 200 is further provided with third fixing holes 310 at the four corners of the positioning protrusion 240. The third fixing holes 310 are adapted to the top seal fixing holes 150 of the top seal 100 and the circuit board packaging holes 730 of the circuit board 700. Fasteners enter the top seal fixing holes 150, the circuit board packaging holes 730 and the third fixing holes 310 in sequence to fix the top seal 100 to the circuit board 700 and the lower seal 200.

[0077] In some embodiments of the present disclosure, the upper isolation member 120 includes at least one seventh isolation protrusion 123 and at least one eighth isolation protrusion 124, and the at least one seventh isolation protrusion 123 and the at least one eighth isolation protrusion 124 are fixed to the top wall of the upper cavity 110, and the height of the at least one seventh isolation protrusion 123 and the at least one eighth isolation protrusion 124 are the same, and the height of the at least one seventh isolation protrusion 123 and the at least one eighth isolation protrusion 124 are less than the depth of the upper cavity 110, wherein the seventh isolation protrusion 123 and the eighth isolation protrusion 124 are both columnar structures.

[0078] In some embodiments of the present disclosure, one seventh isolation protrusion 123 is provided, located at the center of the upper cavity 110. Four eighth isolation protrusions 124 are provided, located at the four corners of the upper cavity 110, and the four eighth isolation protrusions 124 are arranged around the seventh isolation protrusion 123. Specifically, the four eighth isolation protrusions 124 are located on concentric circles centered on the seventh isolation protrusion 123, and the distance between each two adjacent eighth isolation protrusions 124 is the same. This ensures that the small chamber 800 formed between one seventh isolation protrusion 123, two adjacent eighth isolation protrusions 124, and the sidewall of the upper cavity 110 adjacent to the two eighth isolation protrusions 124 are all of the same size. This divides the upper cavity 110 from a single large cavity into multiple small cavities, thereby eliminating a large cavity within the entire packaging device and further preventing lower-frequency resonant cavity modes.

[0079] Obviously, the embodiments described are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field and related fields without making any creative work should fall within the scope of protection of the present disclosure. Structures, devices, and operating methods not specifically described and explained in this disclosure shall be implemented in accordance with conventional means in the field unless otherwise specified or limited.

Claims

1. A quantum chip packaging device, characterized in that: Includes top seal and bottom seal; The end surface of the top seal close to the lower seal has an upper cavity; The end surface of the lower seal close to the top seal has a lower cavity, and the upper cavity and the lower cavity are communicated with each other for encapsulating the quantum chip; A lower isolating member is provided in the lower cavity, and the lower isolating member divides the lower cavity into a plurality of cavities.

2. The quantum chip packaging device according to claim 1, characterized in that: The lower isolating member is arranged on the bottom wall of the lower cavity. The height of the lower isolating member is smaller than the depth of the lower cavity. A lower accommodating cavity is defined between the upper end surface of the lower isolating member and the end surface of the lower cavity with an opening.

3. The quantum chip packaging device according to claim 2, characterized in that: The end surface of the lower seal close to the top seal has a plurality of cluster interconnect packaging areas, each of the cluster interconnect packaging areas has the same structure and is used to package the same cluster interconnect; The lower seal further includes a top seal packaging area, and a plurality of the cluster interconnect packaging areas are circumferentially arranged on an outer periphery of the top seal packaging area.

4. The quantum chip packaging device according to claim 3, characterized in that: The lower cavity is located at the center of the lower sealing member; Each of the cluster interconnect packaging areas is located on the outer periphery of the lower cavity, and each of the cluster interconnect packaging areas is at the same distance from the lower cavity.

5. The quantum chip packaging device according to claim 3, characterized in that: An upper isolator is provided in the upper cavity and is arranged on the top wall of the upper cavity. The upper isolator divides the upper cavity into a plurality of cavities.

6. The quantum chip packaging device according to claim 5, characterized in that: The height of the upper isolator is less than the depth of the upper cavity. An upper accommodating cavity is provided between the lower end surface of the upper isolator and the end surface with an opening in the upper cavity. The upper accommodating cavity and the lower accommodating cavity are connected to form an accommodating chamber, which is used to encapsulate the quantum chip.

7. The quantum chip packaging device according to claim 6, characterized in that: It also includes an upper seal, which has an upper seal hole running through it in a vertical direction in the middle. The upper seal hole is configured to correspond to the top seal, one end of the upper seal hole is connected to the upper cavity, and the other end of the upper seal hole is connected to the lower cavity.

8. The quantum chip packaging device according to claim 7, characterized in that: The upper seal is provided with a plurality of upper seal positioning holes penetrating in a vertical direction. The upper seal positioning holes are configured to correspond to the cluster interconnection members, and each of the upper seal positioning holes corresponds to a packaging area of ​​the cluster interconnection member.

9. The quantum chip packaging device according to claim 7, characterized in that: Also included is a circuit board, the circuit board is located between the top seal and the lower seal, the circuit board is provided with a plurality of circuit board packaging areas; The circuit board packaging area is adapted to the cluster interconnect packaging area.

10. The quantum chip packaging device according to claim 9, characterized in that: A packaging cavity is provided between the upper sealing member and the lower sealing member for packaging a circuit board; The cluster interconnect passes through the upper seal positioning hole and is connected to the circuit board packaging area and the cluster interconnect packaging area, and the top seal passes through the upper seal hole and is connected to the circuit board and the top seal packaging area, so that the cluster interconnect is arranged around the periphery of the top seal.

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