Interposer

Abstract

An interposer includes a first conductive line structure, a conductive via structure electrically connected to the first conductive line structure, and a second conductive line structure forming an integral structure with the conductive via structure. A portion of the first conductive line structure may be disposed in the conductive via structure such that the first conductive line structure and the conductive via structure at least partially overlap, and the first conductive line structure and the conductive via structure share a common surface. The interposer may further include a via landing structure to electrically connect to the first conductive line structure, the via landing structure may have an elongated structure having a landing width less than the landing length.

Description

Technical Field

[0001] The embodiments of the present utility model relate to an interposer, and more particularly to an integral structure formed by a conductive circuit structure and a conductive through-hole structure thereof. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers onto a semiconductor substrate. Photolithography is then used to pattern the various material layers to form circuit components and units. Tens, hundreds, or even thousands of integrated circuits are typically fabricated on a single semiconductor wafer. Cuts are then made along dicing lines between the integrated circuits to separate the individual dies on the wafer. For example, the individual dies are often packaged separately in multi-chip modules or other types of packages.

[0003] In addition to improvements in forming smaller electronic components, developments in component packaging have also been made in an effort to provide smaller packages that occupy less area than previous packages. Examples include quad flat packs (QFPs), pin grid arrays (PGAs), ball grid arrays (BGAs), flip chips (FCs), 3-Dimensional integrated circuits (3DICs), wafer-level packages (WLPs), package-on-package (PoPs), system-on-chip (SoCs), or system-on-integrated circuit (SoIC) devices. Some 3D devices (e.g., 3D ICs, system-on-chips, and system-on-integrated circuits) are fabricated by placing chips on top of each other at the semiconductor wafer level. These 3D devices can improve integration density and offer other advantages such as higher speeds and bandwidth due to reduced interconnect lengths between stacked chips. However, many challenges remain associated with 3D devices. Utility Model Content

[0004] The purpose of the present invention is to provide an intermediary layer to solve at least one of the above problems.

[0005] An interposer provided in one embodiment of the present invention includes: a first conductive circuit structure; a conductive through-hole structure electrically connected to the first conductive circuit structure; and a second conductive circuit structure forming an integral structure together with the conductive through-hole structure.

[0006] According to one embodiment of the present invention, a portion of the first conductive circuit structure is disposed in the conductive through-hole structure, so that the first conductive circuit structure and the conductive through-hole structure at least partially overlap, and wherein the first conductive circuit structure and the conductive through-hole structure share a common surface.

[0007] According to one embodiment of the present invention, a first circuit thickness of the first conductive circuit structure is smaller than a through-hole thickness of the conductive through-hole structure, so that the first conductive circuit structure at least partially overlaps with the conductive through-hole structure along a thickness direction.

[0008] According to one embodiment of the present invention, the total space between the first conductive circuit structure and the conductive through-hole structure along the thickness direction is equal to the thickness of the through-hole.

[0009] According to one embodiment of the present invention, a first line width of the first conductive line structure is smaller than a through-hole width of the conductive through-hole structure, so that the first conductive line structure at least partially overlaps with the conductive through-hole structure along a width direction.

[0010] According to one embodiment of the present invention, the total space between the first conductive circuit structure and the conductive through-hole structure along the width direction is equal to the through-hole width.

[0011] According to one embodiment of the present invention, the first conductive circuit structure is formed on a first dielectric layer; a second dielectric layer is formed on the first dielectric layer; and the conductive through-hole structure is formed in the second dielectric layer on a portion of the first conductive circuit structure to form an electrical connection to the first conductive circuit structure.

[0012] An interposer provided in one embodiment of the present invention includes: a first dielectric layer; a second dielectric layer formed on the first dielectric layer; a first conductive circuit structure formed on the first dielectric layer and in the second dielectric layer; a conductive through-hole structure formed in the second dielectric layer; and a second conductive circuit structure, which together with the conductive through-hole structure forms an integral structure.

[0013] According to one embodiment of the present invention, the conductive via structure is formed in the second dielectric layer and on the first conductive line structure, so that the conductive via structure is electrically connected to and at least partially surrounds a portion of the first conductive line structure, and wherein a first line thickness of the first conductive line structure is less than a through-hole thickness of the conductive via structure, so that the total space between the first conductive line structure and the conductive through-hole structure along a thickness direction is equal to the through-hole thickness.

[0014] According to one embodiment of the present invention, it further includes: a third dielectric layer formed on the second dielectric layer; wherein the second conductive circuit structure is formed on the second dielectric layer and in the third dielectric layer, so that the second conductive circuit structure is electrically connected to the conductive through-hole structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A A vertical cross-sectional exploded view of components of a semiconductor package during package assembly and surface-mounting processes.

[0016] Figure 1B It is a vertical cross-sectional view of a related assembled semiconductor package embedded on the surface of a supporting substrate.

[0017] Figure 2 A vertical cross-sectional view of a portion of an interposer with increased interconnect density according to various embodiments.

[0018] Figure 3A FIG. 1 is a first vertical cross-sectional view of a portion of an additional interposer with increased interconnect density according to various embodiments.

[0019] Figure 3B In various embodiments, Figure 3A A second vertical cross-sectional view of a portion of an interposer.

[0020] Figure 3C In various embodiments, Figure 3A A top view of the electrical interconnect structure of the interposer.

[0021] Figure 3D In various embodiments, Figure 3C A bottom view of the electrical interconnect structure.

[0022] Figure 3E In various embodiments, Figure 3C A three-dimensional top perspective view of the electrical interconnect structure.

[0023] Figure 3F In various embodiments, Figure 3D A three-dimensional bottom perspective view of the electrical interconnect structure of the interposer.

[0024] Figure 4A 1 is a vertical cross-sectional view of an intermediate structure used to form an interposer in various embodiments.

[0025] Figure 4B 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0026] Figure 4C 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0027] Figure 4D 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0028] Figure 4E 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0029] Figure 4F 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0030] Figure 4G 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0031] Figure 4H 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0032] Figure 5A 1 is a vertical cross-sectional view of an intermediate structure used to form other interposer layers in various embodiments.

[0033] Figure 5B 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0034] Figure 5C 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0035] Figure 5D 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0036] Figure 5E 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0037] Figure 5F 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0038] Figure 5G 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0039] Figure 5H 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0040] Figure 5I 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0041] Figure 6AFIG. 1 is a first vertical cross-sectional view of a portion of an additional interposer with increased interconnect density according to various embodiments.

[0042] Figure 6B In various embodiments, Figure 6A A second vertical cross-sectional view of a portion of an interposer.

[0043] Figure 6C In various embodiments, Figure 6A and Figure 6B A top view of a portion of the electrical interconnect structure of the interposer.

[0044] Figure 6D In various embodiments, Figure 6A and 6B A horizontal cross-sectional view of a portion of an interposer.

[0045] Figure 7A 1 is a vertical cross-sectional view of an intermediate structure used to form other interposer layers in various embodiments.

[0046] Figure 7B 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0047] Figure 7C 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0048] Figure 7D 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0049] Figure 7E 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0050] Figure 7F 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0051] Figure 7G 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0052] Figure 7H 1 is a vertical cross-sectional view of other intermediate structures used to form an interposer in various embodiments.

[0053] Figure 8 FIG. 1 is a flow chart of a method for forming an interposer in various embodiments.

[0054] The reference numerals are as follows:

[0055] A-A', B-B', D-D': Section

[0056] 100:Semiconductor packaging

[0057] 102: Support substrate

[0058] 104: First semiconductor device

[0059] 106: Second semiconductor device

[0060] 108,108b,108c,108d: Intermediary layer

[0061] 110:Packaging substrate

[0062] 112: first solder ball

[0063] 114: Lower surface

[0064] 116,126: Upper surface

[0065] 120: first metal bump

[0066] 122: First bottom filling material part

[0067] 124: Second metal bump

[0068] 128: Second underfill material part

[0069] 130,132: Conductive bonding pads

[0070] 134: Third bottom filling material part

[0071] 204: Conductive through-hole structure

[0072] 206a: first dielectric layer

[0073] 206b: second dielectric layer

[0074] 206c: third dielectric layer

[0075] 208a: first conductive circuit structure

[0076] 208b: second conductive circuit structure

[0077] 210a: Through-hole landing structure

[0078] 214a, 214b: Through hole width

[0079] 216a: first line width

[0080] 216b: Second line width

[0081] 218a: first line thickness

[0082] 218b: Second line thickness

[0083] 220:Through hole thickness

[0084] 302: Part

[0085] 304: Common surface

[0086] 306: Surface

[0087] 400a,400b,400c,400d,400e,400f,400g,400h,500a,500b,500c,500d,500e,500f,500g,500h,500i,700a,700b,700c,700d,700e,700f,700g,700h:Intermediate structure

[0088] 402: Carrier board

[0089] 404: Open

[0090] 406: conductive seed layer

[0091] 408: Conductive material

[0092] 410: Patterned photoresist

[0093] 212a1: Landing width

[0094] 212a2: Landing Length

[0095] 800:Method

[0096] 802,804,806,808: Steps DETAILED DESCRIPTION

[0097] The following detailed description is accompanied by accompanying drawings to facilitate understanding of various aspects of the present invention. It is important to note that the various structures are shown for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity.

[0098] The following content provides different embodiments or examples that can implement different structures of the present invention. The following examples of specific components and arrangements are intended to simplify the content of the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple examples of the present invention may repeatedly use the same reference numerals for simplicity, but elements with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0099] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or the like are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is oriented differently (rotated 90 degrees or otherwise), the spatially relative adjectives used should be interpreted in that orientation. Unless otherwise noted, elements with the same reference numeral have the same material composition and thickness ranges.

[0100] In a semiconductor package, several semiconductor integrated circuit dies (i.e., chips) can typically be embedded in a common substrate, which can also be considered a package substrate. In some embodiments, the package substrate can be embedded in a supporting substrate (such as a printed circuit board) containing electrical interconnects to create an electrical connection to the semiconductor package. The semiconductor package may further include an interposer, and one or more semiconductor dies can be attached and electrically coupled to the interposer. The interposer can then be attached and electrically coupled to the package substrate, and the package substrate can be further attached to the printed circuit board. In this way, separate structures (such as semiconductor dies, interposers, package substrates, and printed circuit boards) can be produced and then assembled.

[0101] The disclosed interposer can provide an electrical interconnect structure with a higher interconnect density than a comparative interposer. With this in mind, the interposer in these embodiments can include a first conductive line structure and a conductive via structure formed on the first conductive line structure, such that the conductive via structure is electrically connected to and partially surrounds a portion of the first conductive line structure. In this manner, a portion of the first conductive line structure protrudes into the conductive via structure to overlap with the conductive via structure. Thus, the total spacing of the first conductive line structure and the conductive via structure along the thickness direction can be equal to the via thickness, and the total spacing of the first conductive line structure and the conductive via structure along the width direction can be equal to the via width. In this manner, the vertical and horizontal densities of the interconnect structure can be increased compared to a comparative interposer (which does not include overlapping line and via structures).

[0102] In one embodiment, an interposer may include a first conductive trace structure, and a conductive via structure electrically connected to the first conductive trace structure, such that a portion of the first conductive trace structure protrudes into the conductive via structure to overlap with the conductive via structure. A first trace thickness of the first conductive trace structure may be less than a via thickness of the conductive via structure, such that the first conductive trace structure at least partially overlaps with the conductive via structure along the thickness direction. Similarly, a first trace width of the first conductive trace structure may be less than a via width of the conductive via structure, such that the first conductive trace structure at least partially overlaps with the conductive via structure along the width direction.

[0103] In another embodiment, an interposer includes a first conductive trace structure, a conductive via structure electrically connected to the first conductive trace structure, and a second conductive trace structure that, together with the conductive via structure, forms a unitary structure. In some embodiments, a portion of the first conductive trace structure may be disposed within the conductive via structure, such that the first conductive trace structure and the conductive via structure at least partially overlap, thereby sharing a common surface with the conductive via structure. In other embodiments, the interposer may further include a via landing structure electrically connected to the first conductive trace structure. In some embodiments, the via landing structure may have an elongated structure, comprising a landing width that is smaller than a landing length.

[0104] In other embodiments, the interposer may include a first dielectric layer, a second dielectric layer formed on the first dielectric layer, a first conductive circuit structure formed above the first dielectric layer and within the second dielectric layer, and a conductive via structure formed within the second dielectric layer and above the first conductive circuit structure, such that the conductive via structure is electrically connected to and partially surrounds a portion of the first conductive circuit structure. The first circuit thickness of the first conductive circuit structure may be less than the via thickness of the conductive via structure, such that the total spacing between the first conductive circuit structure and the conductive via structure along the thickness direction is equal to the via thickness. Similarly, the first circuit width of the first conductive circuit structure may be less than the via width of the conductive via structure, such that the total spacing between the first conductive circuit structure and the conductive via structure along the width direction is equal to the via width.

[0105] In other embodiments, the interposer may include a first dielectric layer, a second dielectric layer formed on the first dielectric layer, a first conductive trace structure formed above the first dielectric layer and within the second dielectric layer, a conductive via structure formed within the second dielectric layer, and the second conductive trace structure and the conductive via structure forming a monolithic structure. In some embodiments, the conductive via structure may be formed within the second dielectric layer and above the first conductive trace structure, such that the conductive via structure is electrically connected to and partially surrounds a portion of the first conductive trace structure. In other embodiments, the interposer may further include a via landing structure electrically connected to the first conductive trace structure. In some embodiments, the via landing structure may have an elongated structure, with a landing width smaller than a landing length.

[0106] In one embodiment, a method for forming an interposer may include forming a first conductive circuit structure on a first dielectric layer, forming a second dielectric layer on the first conductive circuit structure, and forming a conductive via structure in the second dielectric layer and above the first conductive circuit structure, so that an electrical connection is formed between the first conductive circuit structure and the conductive via structure. The method may include forming the first conductive circuit structure such that a first circuit thickness of the first conductive circuit structure is less than a via thickness of the conductive via structure, such that a total spacing between the first conductive circuit structure and the conductive via along the thickness direction is equal to the via thickness.

[0107] In another embodiment, a method for forming an interposer may include forming a first conductive trace structure on a first dielectric layer, forming a second dielectric layer on the first conductive trace structure, forming a conductive via structure in the second dielectric layer, such that an electrical connection is formed between the first conductive trace structure and the conductive via structure, and forming the second conductive trace structure and the conductive via structure to form an integral structure. In some embodiments, the method may include forming the conductive via structure on the first conductive trace structure, such that the conductive via structure is electrically connected to and partially surrounds a portion of the first conductive trace structure. In other embodiments, the method may include forming a via landing structure electrically connected to the first conductive trace structure, such that the via landing structure has an elongated structure, wherein the elongated structure has a landing width that is less than the landing length.

[0108] Figure 1A The vertical cross-sectional exploded view shows the components of the semiconductor package 100 during the package assembly and surface-mounting processes. Figure 1B The vertical cross-sectional view of FIG1 shows the semiconductor package 100 being assembled and embedded on a surface of a support substrate 102 such as a printed circuit board. The semiconductor package 100 is merely an example of a semiconductor package, and it should be understood that similar assembly and embedding processes can be used for other types of semiconductor packages.

[0109] like Figure 1A and Figure 1B As shown, the related semiconductor package 100 may include integrated circuit semiconductor devices such as a first semiconductor device 104 and a second semiconductor device 106. During the package assembly process, the first semiconductor device 104 and the second semiconductor device 106 may be embedded on an interposer 108, and the interposer 108 containing the first semiconductor device 104 and the second semiconductor device 106 may be embedded on a package substrate 110 to form the semiconductor package 100. The semiconductor package 100 may then be embedded in a supporting substrate 102 such as a printed circuit board, and the embedding method may use an array of first solder balls 112 on a lower surface 114 of the package substrate 110 to embed the package substrate 110 in the supporting substrate 102.

[0110] The parameters that can ensure proper interconnection between the package substrate 110 and the support substrate 102 are the contact embedding surface (ie Figure 1A The degree of coplanarity between the surfaces of the first solder balls 112 (i.e., the upper surface 116 of the support substrate 102) is poor. A low coplanarity between the first solder balls 112 may cause solder cold joints (i.e., insufficient melting of the solder material, resulting in poor joints that are prone to cracking and delamination) and / or solder bridging problems (i.e., solder from one solder ball 112 contacts solder from an adjacent first solder ball 112, resulting in unintended connections such as electrical shorts during the reflow process).

[0111] Deformation of the package substrate 110, such as stress-induced warping of the package substrate 110, may cause a loss of coplanarity of the first solder balls 112 when the surface of the package substrate 110 is embedded on the support substrate 102. Deformation of the package substrate 110 is common, particularly in semiconductor packages 100 used in high-performance computing applications. These high-performance semiconductor packages 100 are large and may include multiple semiconductor devices (104, 106) embedded on the package substrate 110, which may increase the problem of warping or other deformation of the package substrate 110. These deformations pose challenges to effectively soldering these types of semiconductor package substrates 110 embedded on the support substrate 102.

[0112] The various disclosed embodiments may include semiconductor devices having a redistribution layer formed directly on an active wafer or semiconductor die, as described in detail below (see Figure 2 ). This structure can be configured to be directly bonded to the package substrate 110 without the need for a separate interposer 108. As such, the structure of the embodiment is more modular, easier to manufacture, and has fewer issues associated with stress-induced warping of the package substrate 110, as described in detail below.

[0113] In various embodiments, the first semiconductor device 104 may be a three-dimensional device such as a three-dimensional integrated circuit, a system-on-chip device, or a system-on-integrated circuit device. Three-dimensional semiconductor devices such as the first semiconductor device 104 can be formed by placing chips on chips at the semiconductor wafer level. These three-dimensional devices can reduce interconnect lengths between stacked chips, improving integration density and providing other advantages, such as higher speed and bandwidth. In some embodiments, a three-dimensional semiconductor device such as the first semiconductor device 104 can also be considered a first die stack.

[0114] The second semiconductor device 106 may be different in structure, design, and / or functionality from the first semiconductor device 104. One or more second semiconductor devices 106 may be three-dimensional semiconductor devices, which may also be considered a second die stack. In some embodiments, one or more second semiconductor devices 106 may include a memory device such as a high bandwidth memory device. Figure 1A and Figure 1B In the illustrated example, the semiconductor package 100 may include a stack of system-on-chip dies, such as a first semiconductor device 104 , and a stack of high-bandwidth memory dies, such as a second semiconductor device 106 . However, it should be understood that the semiconductor package 100 may include more or fewer semiconductor devices.

[0115] like Figure 1BAs shown, the first semiconductor device 104 and the second semiconductor device 106 can be embedded in an interposer 108. In some examples, the interposer 108 can be an organic interposer comprising a polymer dielectric material (e.g., polyimide) having a plurality of metal interconnect structures extending therethrough. In other examples, the interposer 108 can be a semiconductor interposer, such as a silicon interposer, having a plurality of interconnect structures (e.g., through-silicon vias) extending therethrough. Other suitable configurations for the interposer 108 are also within the scope of embodiments of the present invention. The interposer 108 can include a plurality of conductive bonding pads on the top and bottom surfaces of the interposer, and a plurality of conductive interconnects extending through the interposer 108 between the top and bottom bonding pads of the interposer 108. The conductive interconnects can distribute and route electrical signals between the first semiconductor device 104, the second semiconductor device 106, and the underlying package substrate 110. Therefore, the interposer 108 can be considered a redistribution layer.

[0116] A plurality of first metal bumps 120, such as microbumps, can electrically connect conductive bonding pads on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106 to conductive bonding pads on the top surface of the interposer 108. In a non-limiting embodiment, the first metal bumps 120 are in the form of microbumps (which may include a plurality of first metal stacks, such as a plurality of copper-nickel-copper stacks), which can be located on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106. A plurality of second metal stacks (such as copper-nickel-copper stacks) are located on the top surface of the interposer 108. Solder material, such as tin, can be located between each of the first and second metal stacks to electrically connect the first and second semiconductor devices 104, 106 to the interposer 108. Other suitable materials for the first metal bumps 120 are within the scope of the present invention.

[0117] After the first semiconductor device 104 and the second semiconductor device 106 are embedded in the interposer 108, a first underfill material portion 122 may be provided around the first metal bump 120 and in the space between the first semiconductor device 104, the second semiconductor device 106, and the upper surface of the interposer 108, as appropriate. Figure 1B A first underfill material portion 122 may also be provided in the space laterally separating the first semiconductor device 104 and the second semiconductor device 106 of the semiconductor package 100. In various embodiments, the first underfill material portion 122 may include an epoxy-based material, which may include a composite of a resin and a filler material.

[0118] like Figure 1BAs shown, the interposer 108 can be embedded in a packaging substrate 110, and the packaging substrate 110 can provide mechanical support for the interposer 108 and the first and second semiconductor devices 104 and 106 embedded in the interposer 108. The packaging substrate 110 can include a suitable material such as an organic material (e.g., a polymer and / or thermoplastic material), a semiconductor material (e.g., a semiconductor wafer such as a silicon wafer), a ceramic material, a glass material, combinations thereof, or the like. Other suitable substrate materials are also within the scope of embodiments of the present invention. In various embodiments, the packaging substrate 110 can include a plurality of conductive bonding pads (not shown) on the upper surface 126 of the packaging substrate 110. A plurality of second metal bumps 124 (e.g., controlled collapse chip connection solder bumps) can electrically connect the conductive bonding pads (not shown) on the lower surface of the interposer 108 to the conductive bonding pads on the upper surface 126 of the packaging substrate 110. In various embodiments, the second metal bumps 124 can include a suitable solder material such as tin, although other suitable solder materials are also within the scope of embodiments of the present invention.

[0119] A second underfill material portion 128 may be provided around the second metal bump 124 and in the space between the lower surface of the interposer 108 and the upper surface 126 of the package substrate 110 . Figure 1B In various embodiments, the second underfill material portion 128 may include an epoxy-based material, which may include a composite of a resin and a filler material. In some embodiments, the cover (not shown) Figure 1A and Figure 1B ) can be embedded in the packaging substrate 110 and can seal the upper surface and side surfaces of the first semiconductor device 104 and the second semiconductor device 106.

[0120] As described above, the package substrate 110 can be embedded in a support substrate 102 such as a printed circuit board. Other suitable support substrates 102 also fall within the scope of embodiments of the present invention. The package substrate 110 may include a plurality of conductive bonding pads 130 in the lower surface 114 of the package substrate 110. A plurality of conductive interconnects (not shown) may extend through the package substrate 110 between the lower surface 114 and the conductive bonding pads on the upper surface 126 of the package substrate 110. A plurality of first solder balls 112 (or bump structures) may electrically connect the conductive bonding pads 130 on the lower surface 114 of the package substrate 110 to the conductive bonding pads 132 on the upper surface 116 of the support substrate 102.

[0121] The conductive bonding pads 130 of the package substrate 110 and the conductive bonding pads 132 of the support substrate 102 can be made of a suitable conductive material such as copper. Other suitable conductive materials are also within the scope of embodiments of the present invention. The plurality of first solder balls 112 on the lower surface 114 of the package substrate 110 can form an array of first solder balls 112, such as a ball grid array, which includes a pattern array that corresponds to the pattern array of the conductive bonding pads 132 on the upper surface 116 of the support substrate 102. In a non-limiting example, the array of first solder balls 112 can include a grid pattern and a spacing (i.e., the distance between the center of each first solder ball 112 and the center of an adjacent first solder ball 112). In one embodiment, the spacing can be between approximately 0.8 mm and 1.0 mm, but larger or smaller spacings can also be used. The first solder balls 112 can include any suitable solder material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, alloys thereof, combinations thereof, or the like. Other suitable materials used for the first solder ball 112 also fall within the scope of the embodiments of the present invention.

[0122] In some embodiments, the lower surface 114 of the package substrate 110 may include a coating of solder resist material (not shown), which may also be considered a solder mask. The solder resist coating provides a protective coating for the package substrate 110 and any underlying circuit patterns formed on or in the package substrate 110. The solder resist coating may also inhibit solder material from adhering to the lower surface 114 of the package substrate 110 during the reflow process. In embodiments where the lower surface 114 of the package substrate 110 includes a solder resist coating, the solder resist coating may include a plurality of openings to expose the conductive bonding pads 130.

[0123] In various embodiments, each conductive bonding pad 130 in different regions of the package substrate 110 may have the same size and shape. Figure 1A and Figure 1B In some embodiments, the surface of the conductive bonding pad 130 may be substantially coplanar with the lower surface 114 of the package substrate 110, and embodiments may include a coating of solder resist material. In other embodiments, the surface of the conductive bonding pad 130 may be recessed relative to the lower surface 114 of the package substrate 110. In some embodiments, the conductive bonding pad 130 may be raised relative to the lower surface 114 of the package substrate 110.

[0124] like Figure 1A and 1BAs shown, first solder balls 112 may be provided on respective conductive bonding pads 130. In a non-limiting example, the width of the conductive bonding pad 130 may be between about 500 microns and about 550 microns (e.g., about 530 microns), and the outer diameter of the first solder ball 112 may be between about 600 microns and about 650 microns (e.g., about 630 microns). However, first solder balls 112 and / or conductive bonding pads 130 of larger or smaller sizes are also within the scope of the present invention.

[0125] The first solder reflow process may include raising the temperature of the package substrate 110 (e.g., to at least approximately 250° C.) to melt the first solder balls 112 and adhere the first solder balls 112 to the conductive bonding pads 130. After the first reflow process, the package substrate 110 may be cooled to resolidify the first solder balls 112. After the first solder reflow process, the first solder balls 112 may adhere to the conductive bonding pads 130. The vertical distance that each of the first solder balls 112 extends from the lower surface 114 of the package substrate 110 may be less than the outer diameter of the first solder balls 112 before the first reflow process. For example, when the outer diameter of the first solder balls 112 is between approximately 600 microns and approximately 650 microns (e.g., approximately 630 microns), the vertical height of the first solder balls 112 after the first reflow process may be between approximately 500 microns and approximately 550 microns (e.g., approximately 520 microns).

[0126] In various embodiments, the process of embedding the package substrate 110 onto the support substrate 102 is as follows: Figure 1B As shown, it may include aligning the package substrate 110 on the support substrate 102 so that the first solder balls 112 contacting the conductive bonding pads 130 of the package substrate 110 can be located on corresponding bonding pads (such as conductive bonding pads 132) on the support substrate. A second solder reflow process may then be performed. The second solder reflow process may include raising the temperature of the package substrate 110 (e.g., to at least approximately 250°C) to melt the first solder balls 112 and adhere the first solder balls 112 to the corresponding conductive bonding pads 132 on the support substrate 102. As the solder material cools and solidifies, surface tension causes the semi-liquid solder to maintain alignment with the support substrate 102. Once the first solder balls 112 are solidified, the package substrate 110 can be located on the upper surface 116 of the support substrate 102 at a height between approximately 0.4 mm and approximately 0.5 mm, although larger or smaller heights are still within the scope of embodiments of the present invention.

[0127] After embedding the package substrate 110 into the support substrate 102, a third underfill material portion 134 may be provided around the first solder balls 112 and in the space between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102. Figure 1BIn various embodiments, the third underfill material portion 134 may include an epoxy-based material, which may include a composite of a resin and a filler material.

[0128] Figure 2 FIG2 is a vertical cross-sectional view of a portion of an interposer 108b with increased interconnect density in various embodiments. As shown, the interposer 108b may include a first dielectric layer 206a, a second dielectric layer 206b formed on the first dielectric layer 206a, and a first conductive line structure 208a formed on the first dielectric layer 206a and within the second dielectric layer 206b. The interposer 108b may further include a conductive via structure 204 formed within the second dielectric layer 206b and above the first conductive line structure 208a, such that the conductive via structure 204 is electrically connected to and partially surrounds a portion of the first conductive line structure 208a, such as with Figures 3A to 3F Details are given below.

[0129] like Figure 2 As shown, the first conductive circuit structure 208a and the conductive via structure 204 can form a line-in-via structure.

[0130] like Figure 2 As shown, the first line thickness 218a of the first conductive line structure 208a can be smaller than the through hole thickness 220 of the conductive through hole structure 204, so that the first conductive line structure 208a and the conductive through hole structure 204 are aligned along the thickness direction (ie Figure 2 The total space in the z direction in the conductive via structure 204 is equal to the through-hole thickness 220. In this way, compared to the embodiment (not shown) in which the first conductive line structure 208a does not overlap with the conductive via structure 204, the vertical density of the electrical interconnect structure can be increased. The total thickness of the conductive via structure 204 and the first conductive line structure 208a can correspond to the thickness of the conductive via structure 204 itself. Similarly, the first line width 216a of the first conductive line structure 208a can be smaller than the through-hole width (214a, 214b) of the conductive via structure 204, so that the first conductive line structure 208a and the conductive via structure 204 are aligned along the width direction (i.e., along the width direction). Figure 2 The total space (in the x-direction) is equal to the through-hole width (214a, 214b). In this way, compared to the embodiment (not shown) in which the first conductive line structure 208a does not overlap with the space of the conductive through-hole structure 204, the horizontal density of the electrical interconnect structure can be increased.

[0131] The interposer 108b may further include a third dielectric layer 206c formed on the second dielectric layer 206b, and a second conductive circuit structure 208b formed on the second dielectric layer 206b and in the third dielectric layer 206c. The second conductive circuit structure 208b may be further electrically connected to the conductive via structure 204. Figure 2 As shown, the second conductive line structure 208 b and the conductive via structure 204 form a line-on-via structure.

[0132] Figures 3A to 3F Various drawings are provided showing portions of other embodiments of an interposer 108c with increased interconnect density in various embodiments. Figure 3A is a first vertical cross-sectional view of an embodiment of an interposer 108c, Figure 3B for Figure 3A A second vertical cross-sectional view of an embodiment of an interposer 108c, Figure 3C for Figure 3A A top view of the electrical interconnect structure of an embodiment of the interposer 108c is shown. Figure 3D for Figure 3C A bottom view of the electrical interconnect structure of an embodiment of the interposer 108c is shown. Figure 3E for Figure 3C A three-dimensional top perspective view of the electrical interconnect structure of an embodiment of the interposer 108c, and Figure 3F for Figure 3D A three-dimensional bottom perspective view of the electrical interconnect structure of an embodiment of the interposer 108c is shown. Figures 3A to 3F Embodiments and combinations of the interposer 108c Figure 2 The embodiment of the interposer 108b described above is similar. Figure 2 An embodiment of the interposer 108b with Figures 3A to 3F The method for forming the interposer 108c of the embodiment may be performed by using Figures 4A to 5I The method is detailed below.

[0133] like Figure 2 An embodiment of the interposer 108b, Figures 3A to 3F The embodiment of the interposer 108c may include a first conductive line structure 208a and a conductive via structure 204 electrically connected to the first conductive line structure 208a. The portion 302 of the first conductive line structure 208a (see FIG. Figure 3D and Figure 3F ) can protrude into the conductive via structure 204 (see Figure 3A ), so that the first conductive line structure 208a and the conductive through-hole structure 204 at least partially overlap. Figure 3A and Figure 3B As shown, the first conductive line structure 208a and the conductive via structure 204 may share a common surface 304. In this manner, the common surface 304 may be parallel to the interface between the first dielectric layer 206a and the second dielectric layer 206b. The first line thickness 218a of the first conductive line structure 208a may be smaller than the through-hole thickness 220 of the conductive via structure 204, so that the first conductive line structure 208a is thinner along the thickness direction (i.e., along the Figure 3A and Figure 3B z-direction in FIG. 2 ) at least partially overlaps with the conductive via structure 204 .

[0134] exist Figures 3A to 3F In the embodiment, the total space of the first conductive line structure 208a and the conductive through-hole structure 204 along the thickness direction can be equal to the through-hole thickness 220. In this way, the vertical density of the interconnect structure can be increased. Figures 3A to 3F As shown, the first line width 216a of the first conductive line structure 208a can be smaller than the through hole width (214a, 214b) of the conductive through hole structure 204, so that the first conductive line structure 208a is Figures 3A to 3F In the x-direction and y-direction in FIG. 2 , the conductive via structure 204 at least partially overlaps. In this way, the total space along the width direction of the first conductive line structure 208a and the conductive via structure 204 can be equal to the via width (214a, 214b). As described above, the portion 302 of the first conductive line structure 208a (see FIG. 2 ) Figure 3D and Figure 3F ) can be embedded in the conductive via structure 204 (see Figure 3A ), so that the first conductive circuit structure 208a and the conductive through-hole structure 204 share a common connection volume.

[0135] Figures 3A to 3F The embodiment of the interposer 108c may further include a second conductive line structure 208b electrically connected to the conductive via structure 204, and the second conductive line structure 208b and the first conductive line structure 208a are formed on opposite sides of the conductive via structure 204. Figures 3A to 3F For example, the first conductive line structure 208a can be formed on the bottom side of the conductive via structure 204, and the second conductive line structure 208b can be formed on the top side of the conductive via structure 204. The second conductive line structure 208b can have a second line thickness 218b and can contact the surface 306 of the conductive via structure 204. Figure 3A As shown, the surface 306 of the conductive via structure 204 can be perpendicular to the thickness direction (i.e., the z direction), so that the total space along the thickness direction of the second conductive line structure 208b and the conductive via structure 204 (such as the sum of the via thickness 220 and the second line thickness 218b) is greater than the via thickness.

[0136] Figure 4AFigure 4 is a vertical cross-sectional view of an interposer structure 400a used to form interposers (108b, 108c) in various embodiments. Interposer structure 400a may include a first dielectric layer 206a formed on a carrier 402. Various interconnect structures (e.g., redistribution layer interconnect structures) may be formed on the first dielectric layer 206a. For example, interposer structure 400a may include a plurality of first conductive trace structures 208a. Interposer structure 400a may be formed by depositing the first dielectric layer 206a on the carrier 402 and then forming the plurality of first conductive trace structures 208a.

[0137] The first dielectric layer 206a may include a dielectric polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by performing a spin coating process to deposit the first dielectric layer 206a. The deposited polymer material is then dried to form the first dielectric layer 206a. The first dielectric layer 206a may have a thickness of 2 to 40 microns, such as 4 to 20 microns. In other embodiments, the first dielectric layer 206a may include various other suitable polymers deposited by other deposition methods.

[0138] A plurality of first conductive line structures 208a can then be formed on the first dielectric layer 206a by sputter-depositing a conductive seed layer (not shown), applying and patterning a photoresist layer on the conductive seed layer to form a pattern of openings through the photoresist layer, electroplating a metal fill material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the conductive seed layer between the plated metal fill material portions. For example, the conductive seed layer can include a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer can have a thickness of 50 nm to 300 nm, while the copper seed layer can have a thickness of 100 nm to 500 nm. The metal fill material used for the first conductive line structures 208a can include copper, nickel, or a combination of copper and nickel. The metal fill material used for the first conductive line structures 208a can be deposited to a thickness of 2 μm to 40 μm, such as 4 μm to 10 μm, although greater or lesser thicknesses may also be used. In other embodiments, a blanket layer of metal fill material (not shown) may be deposited on the first dielectric layer 206a. A photoresist layer may be applied to the blanket layer of metal fill material and patterned. Using the photoresist layer as an etch mask, various first conductive line structures 208a may be formed through an etching process. For example, the photoresist layer may be removed by ashing or dissolution.

[0139] Figure 4B The method of forming the intermediate structure 400b from the intermediate structure 400a can be to form the second dielectric layer 206b on the intermediate structure 400b. Figure 4AThe second dielectric layer 206b may be formed on the intermediate structure 400a. The second dielectric layer 206b may include the same material as the first dielectric layer 206a. The material included in the second dielectric layer 206b may be different from the material included in the first dielectric layer 206a. In this regard, the second dielectric layer 206b may be a polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by a spin coating process. In other embodiments, the second dielectric layer 206b may include various other suitable polymers deposited by other deposition methods.

[0140] Figure 4C 1 is a vertical cross-sectional view of another intermediate structure 400c used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 400c from the intermediate structure 400b can be to etch the second dielectric layer 206b to form an opening 404 on each of the first conductive line structures 208a. In this regard, a patterned photoresist (not shown) can be formed on the second dielectric layer 206b. Then, an etching process can be performed to etch the portion of the second dielectric layer 206b not masked by the patterned photoresist. Figure 4C As shown, a region of the second dielectric layer 206b may be etched down to the surface of the first dielectric layer 206a to form an opening 404. In this manner, the etching process used to create the opening 404 may expose the surface of the first conductive line structure 208a.

[0141] Figure 4D A vertical cross-sectional view of another intermediate structure 400d used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 400d from the intermediate structure 400c can be to form a conductive seed layer 406 on Figure 4C The conductive seed layer 406 is formed on the intermediate structure 400c. The conductive seed layer 406 may be formed by sputtering and may include a metal material such as copper, titanium, or the like. For example, the conductive seed layer 406 may be a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may be 50 nm to 300 nm, while the thickness of the copper seed layer may be 100 nm to 500 nm. In other embodiments, the conductive seed layer 406 may be made of various other materials and thicknesses. The conductive seed layer 406 may form a conductive contact with the first conductive circuit structure 208a.

[0142] Figure 4E A vertical cross-sectional view of another intermediate structure 400e used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 400e from the intermediate structure 400d can be to deposit the conductive material 408 on Figure 4DThe conductive material 408 may be a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), deposited by electroplating. Other suitable metal filler materials also fall within the scope of embodiments of the present invention. The metal filler material may be deposited to a thickness of 2 to 40 microns, such as 4 to 10 microns, although smaller or larger thicknesses may be employed. Various other conductive materials and deposition methods may be employed in other embodiments.

[0143] Figure 4F A vertical cross-sectional view of another intermediate structure 400f used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 400f from the intermediate structure 400e can be to form a patterned photoresist 410 on Figure 4E In this regard, a blanket layer of photoresist (not shown) can be deposited on the surface of the conductive material 408 of the intermediate structure 400e. The blanket layer of photoresist can then be patterned using photolithography techniques to form a patterned photoresist 410. The patterned photoresist 410 can be used when an anisotropic etching process is performed to etch the conductive material 408, such as with Figure 4G Details are given below.

[0144] Figure 4G FIG. 4 is a vertical cross-sectional view of another intermediate structure 400g used to form interposers (108b, 108c) in various embodiments. The method of forming the intermediate structure 400g from the intermediate structure 400f can be to perform an anisotropic etching process to etch the conductive material 408. As shown in the figure, the etching process can be performed to remove the unmasked portion of the conductive material 408. Figure 4G As shown, the etching process can produce the conductive via structure 204 and the second conductive line structure 208b. In this way, the conductive via structure 204 can form an integral structure with the second conductive line structure 208b. Figure 4G As shown, a conductive connection may be formed between the conductive via structure 204 and the first conductive line structure 208 a via the connection provided by the conductive seed layer 406 .

[0145] Figure 4H A vertical cross-sectional view of another intermediate structure 400h used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 400h from the intermediate structure 400g may be to remove Figure 4G The patterned photoresist 410 of the intermediate structure 400g is removed. In this regard, the method for removing the patterned photoresist 410 can be ashing or dissolving with a solvent. Then, an additional interconnect layer can be formed on the intermediate structure 400h. The formation method can be to perform additional process steps, which are combined with Figures 4A to 4GFor example, in an additional process step, a third dielectric layer 206c may be formed on the intermediate structure 400h to form Figures 2 to 3F The final structure (see Figure 2 、 Figure 3A and Figure 3B ) can then be used as a starting point for forming additional interconnect layers, using a process that can be combined with Figures 4A to 4H The process described above is similar.

[0146] Figure 5A 1 is a vertical cross-sectional view of an intermediate structure 500a used to form an interposer (108b, 108c) in various embodiments. The intermediate structure 500a may be similar to the intermediate structure 400a. In this regard, the intermediate structure 500a may include a first dielectric layer 206a formed on the carrier 402, and a plurality of interconnect structures (such as redistribution layer interconnect structures) formed on the first dielectric layer 206a. For example, the intermediate structure 500a may include a plurality of first conductive line structures 208a. The intermediate structure 500a may be formed by depositing the first dielectric layer 206a on the carrier 402 and then forming the plurality of first conductive line structures 208a. Figure 4A In the intermediate structure 400a, the first dielectric layer 206a may include a dielectric polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by performing a spin coating process to deposit the first dielectric layer 206a.

[0147] The method for subsequently forming multiple first conductive circuit structures 208a on the first dielectric layer 206a may be sputtering deposition of a conductive seed layer (not shown), applying and patterning a photoresist layer on the conductive seed layer to form a pattern of openings through the photoresist layer, electroplating a metal filling material (such as copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the conductive seed layer between the electroplated metal filling material portions.

[0148] Figure 5B A vertical cross-sectional view of another intermediate structure 500a used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 500b from the intermediate structure 500a can be to form the conductive seed layer 406 on the Figure 5A The conductive seed layer 406 is formed on the intermediate structure 500a. The conductive seed layer 406 can be formed by sputtering a metal material such as copper, titanium, or the like. For example, the conductive seed layer 406 can be a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer can be 50 nm to 300 nm, while the thickness of the copper seed layer can be 100 nm to 500 nm. In other embodiments, the conductive seed layer 406 can be made of various other materials and thicknesses. The conductive seed layer 406 can form a conductive contact with the first conductive circuit structure 208a.

[0149] Figure 5C A vertical cross-sectional view of another intermediate structure 500c used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 500c from the intermediate structure 500b can be to form a patterned photoresist 410 on Figure 5B In this regard, a blanket layer of photoresist (not shown) may be deposited on the surface of the conductive seed layer 406 of the intermediate structure 500b. The blanket layer of photoresist may then be patterned using photolithography techniques to form a patterned photoresist 410. As shown, the patterned photoresist 410 may include openings 404 to expose portions of the conductive seed layer 406 on the first conductive line structure 208a. Conductive material 408 may then be formed in the openings 404 of the patterned photoresist 410, such as with Figure 5D Details are given below.

[0150] Figure 5D A vertical cross-sectional view of another intermediate structure 500d used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 500d from the intermediate structure 500c can be to deposit the conductive material 408 on Figure 5C The conductive material 408 may be a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), and may be deposited by electroplating. The metal filler material may be deposited to a thickness of 2 to 40 microns, such as 4 to 10 microns, although smaller or larger thicknesses may be employed. Various other conductive materials and deposition methods may be employed in other embodiments.

[0151] Figure 5E 108a, 108b, and 108c. The intermediate structure 500e is formed from the intermediate structure 500d by removing the patterned photoresist 410, and the removal method can be ashing or dissolving with a solvent. The final intermediate structure 500e includes a conductive via structure 204 formed on the conductive seed layer 406 and the first conductive line structure 208a. In this way, the conductive seed layer 406 can form a conductive contact between the first conductive line structure 208a and the conductive via structure 204. Additional interconnect structures can then be formed on the intermediate structure 500f, such as with Figures 5F to 5I The following content is described.

[0152] Figure 5F A vertical cross-sectional view of another intermediate structure 500f used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 500f from the intermediate structure 500e can be to form the second dielectric layer 206b on Figure 5EThe second dielectric layer 206b may be formed on the intermediate structure 500e. The second dielectric layer 206b may include the same material as the first dielectric layer 206a. Alternatively, the second dielectric layer 206b may include a material different from that of the first dielectric layer 206a. In this regard, the second dielectric layer 206b may be a polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by a spin coating process. In other embodiments, the second dielectric layer 206b may include various other suitable polymers deposited by other deposition methods.

[0153] Figure 5G The method of forming the intermediate structure 500g from the intermediate structure 500f can be to form another conductive seed layer 406 and a patterned photoresist 410 on the intermediate structure 500g. Figure 5F As shown in the figure, before forming the patterned photoresist 410, a conductive seed layer 406 can be formed on the upper surface of the intermediate structure 500f. The conductive seed layer 406 can be formed by sputtering a metal material such as copper, titanium, or the like, as described in detail above.

[0154] The method for forming the patterned photoresist 410 can be achieved by combining Figure 4F In this regard, a blanket layer of photoresist (not shown) may be deposited on Figure 5F The upper surface of the intermediate structure 500f is then patterned using photolithography techniques to form a patterned photoresist 410. As shown, the patterned photoresist 410 may include a plurality of openings 404 to expose portions of the conductive seed layer 406 above the conductive via structure 204 and above the second dielectric layer 206b. A conductive material 408 may then be formed in the openings 404 of the patterned photoresist 410, such as with Figure 5H Details are given below.

[0155] Figure 5H A vertical cross-sectional view of another intermediate structure 500h used to form the interposer (108b, 108c) in various embodiments. The method of forming the intermediate structure 500h from the intermediate structure 500g can be to deposit the conductive material 408 on Figure 5G The conductive material 408 may be a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), deposited by electroplating. The metal filler material may be deposited to a thickness of 2 to 40 microns, such as 4 to 10 microns, although smaller or larger thicknesses may be employed. Various other conductive materials and deposition methods may be employed in other embodiments.

[0156] Figure 5IA vertical cross-sectional view of another intermediate structure 500i used to form the interposer (108c, 108d) in various embodiments. The method of forming the intermediate structure 500i from the intermediate structure 500h can be to remove Figure 5H The patterned photoresist 410 of the intermediate structure 500h is removed. In this regard, the removal method of the patterned photoresist 410 can be ashing or solvent dissolution. As shown in the figure, the remaining portion of the conductive material 408 can form a plurality of second conductive line structures 208b. In this manner, the conductive via structure 204 and the second conductive line structures 208b can be electrically connected to each other via the conductive seed layer 406.

[0157] Then, an additional interconnect layer may be formed on the intermediate structure 500i, and the forming method may be to perform additional process steps, which may be combined with Figures 5A to 5H The process steps described above are similar. For example, an additional process step may form a third dielectric layer 206c on the intermediate structure 500i to form Figures 2 to 3F The final structure (see Figure 2 、 Figure 3A and Figure 3B ) can then be used as a starting point for forming additional interconnect layers, which can be used in conjunction with Figures 5A to 5H The process is similar to the above description.

[0158] In various embodiments, Figure 6A is a first vertical cross-sectional view of another interposer 108d with increased interconnect density, and Figure 6B for Figure 6A A second vertical cross-sectional view of a portion of the interposer. Definition Figure 6B The first plane of the cross-sectional view may be Figure 6A The section B-B' in the Figure 6A The second plane of the cross-sectional view may be Figure 6B The section A-A' in Figure 2 and 3A Intermediary layers 108b and 108c, Figure 6A and 6B The interposer 108d may include a via-on-line structure, wherein the second conductive line structure 208b may form an integral structure with the conductive via structure 204. Figure 2 and Figure 3A Compared with the interposer layers 108b and 108c, Figure 6A and Figure 6B The interposer 108d includes a via landing structure 210a that can be electrically connected to the conductive via structure 204 to replace the via-in-line structure of the interposers 108b and 108c. In this regard, the via landing structure 210a can have an elongated structure (see FIG. Figure 6C and Figure 6D), thereby increasing the contact area between the conductive via structure 204 and the via landing structure 210a. Increasing the contact area between the conductive via structure 204 and the via landing structure 210a can reduce the electrical contact resistance (compared to Figure 2 and Figure 3A interposer layers 108b and 108c), thus being advantageous for certain embodiments.

[0159] In various embodiments, Figure 6C for Figure 6A A top view of the electrical interconnect structure of the interposer 108d is shown. Figure 6D for Figure 6A A horizontal cross-sectional view of a portion of the interposer 108d. Figure 6D The plane of the cross-sectional view can be Figure 6B The cross section D-D' is shown. Figure 6C and Figure 6D As shown, the through hole landing structure 210a is arranged along the width direction (i.e., along the Figure 6A 、 Figure 6C and Figure 6D The size of the x-direction in the Figure 6B 、 Figure 6C and Figure 6D In this way, Figures 6A to 6D In the embodiment of the interposer 108d, the horizontal density of the electrical interconnect structure along the width direction can be increased. In this way, for a specific application embodiment, a trade-off is required between the electrical contact resistance and the electrical interconnect density. For example, Figure 2 and Figure 3A The embodiment of the interposer layers 108b and 108c is more advantageous for applications requiring a greater density of interconnect structures. Figure 6C and Figure 6D The embodiment of the interposer 108d is more advantageous for applications requiring lower electrical contact resistance. Thus, the selection between the various embodiments of the interposer (108b, 108c, 108d) depends on the circuit design considerations of the individual application.

[0160] like Figure 2 and 3A Examples of interposers 108b and 108c, Figure 6A and Figure 6B The interposer 108d may include a first dielectric layer 206a formed on the carrier 402, a second dielectric layer 206b formed on the first dielectric layer 206a, and a third dielectric layer 206c formed on the second dielectric layer 206b. Figure 6A and Figure 6BThe interposer 108d may further include a plurality of via landing structures 210a and a conductive via structure 204 formed on the first dielectric layer 206a and within the second dielectric layer 206b. The conductive via structures 204 and the via landing structures 210a may be separated by a conductive seed layer 406. Thus, conductive connections may be formed between the conductive via structures 204 and the via landing structures 210a via the connections provided by the conductive seed layer 406. As described above, the second conductive trace structure 208b may form an integral structure with the conductive via structure 204. In this regard, the conductive via structure 204 may be formed in the second dielectric layer 206b, and the second conductive trace structure 208b may be formed on the second dielectric layer 206b and within the third dielectric layer 206c.

[0161] like Figure 6C As shown, the electrical interconnect structure of the interposer 108d may include a plurality of second conductive line structures 208b. Figure 6C As shown, a set of second conductive line structures 208b can be electrically and mechanically connected to the via landing structure 210a. As described above, the via landing structure 210a can have an elongated structure having a width direction (i.e., along the Figure 6A 、 Figure 6C and Figure 6D The landing width 212a1 along the x direction in the longitudinal direction (i.e., along the Figure 6B 、 Figure 6C and Figure 6D In addition, the landing width 212a1 may be smaller than the landing length 212a2. Figure 6C and Figure 6D As shown, the via landing structure 210a may be shaped as an elongated oval. In other embodiments, the via landing structure 210a may have various other shapes (e.g., rectangular). As described above, the elongated structure of the via landing structure 210a increases the overlap area between the conductive via structure 204 and the via landing structure 210a, thereby reducing the electrical contact resistance between the conductive via structure 204 and the via landing structure 210a. Furthermore, reducing the landing width 212a1 may increase the horizontal density of the electrical interconnect structure along the width direction.

[0162] The smaller landing width 212a1 allows various electrical interconnect structures (such as the second conductive trace structure 208b) to be placed closer together, while the increased landing length 212a2 does not increase the horizontal density of the electrical interconnect structures because the longer dimension of the via landing structure 210a (i.e., the landing length 212a2) aligns with and overlaps the existing structure (i.e., the second conductive trace structure 208b). Thus, the reduced landing width 212a1 increases the density of the electrical interconnect structures, while the increased landing length 212a2 reduces electrical contact resistance and avoids increasing the overall density of the electrical interconnect structures.

[0163] The relative sizes of the various components of the interposer 108d can be similar to the relative sizes of the various components of the other interposers (108b, 108c) in the above-mentioned embodiments. In this regard, the via width (214a, 214b) of the conductive via structure 204 can be smaller than the via landing width 212a1, so that the conductive via structure 204 and the via landing structure 210a are aligned along the width direction (i.e., along the width direction). Figure 2 The total space of the second conductive line structure 208b (in the x-direction) is equal to the through-hole landing width 212a1. Similarly, the second line width 216b of the second conductive line structure 208b (see Figure 6C ) is smaller than the through hole landing width 212a1, so that the total space between the second conductive line structure 208b and the through hole landing structure 210a along the width direction is equal to the through hole landing width 212a1. Figure 6D As shown, the size and shape of the conductive via structure 204 are smaller than the corresponding size and shape of the via landing structure 210a.

[0164] Figure 7A For various embodiments, forming Figure 6A and Figure 6B FIG2 is a vertical cross-sectional view of an intermediate structure 700a used in conjunction with another interposer 108d. The intermediate structure 700a may be similar to the intermediate structures 400a and 500a. In this regard, the intermediate structure 700a may include a first dielectric layer 206a formed on the carrier 402, and a plurality of electrical interconnect structures (such as redistribution layer interconnect structures) formed on the first dielectric layer 206a. For example, the intermediate structure 700a may include a plurality of first conductive line structures 208a and a through-hole landing structure 210a. The intermediate structure 700a may be formed by depositing the first dielectric layer 206a on the carrier 402, and then forming the plurality of first conductive line structures 208a and the through-hole landing structure 210a.

[0165] like Figure 4A and Figure 4BIn the intermediate structures 400a and 500a, the first dielectric layer 206a may include a dielectric polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by a spin coating process to deposit the first dielectric layer 206a. Other embodiments may use other dielectric materials deposited by other deposition processes.

[0166] A plurality of first conductive line structures 208a and through-hole landing structures 210a may then be formed on the first dielectric layer 206a by sputtering and depositing a conductive seed layer (not shown), applying and patterning a photoresist layer on the conductive seed layer to form a pattern of openings through the photoresist layer, electroplating a metal fill material (such as copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the conductive seed layer between the plated metal fill material portions.

[0167] Figure 7B A vertical cross-sectional view of another intermediate structure 700b used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700b from the intermediate structure 700a may be to form the second dielectric layer 206b on Figure 7A The second dielectric layer 206b may be formed on the intermediate structure 700a. The second dielectric layer 206b may include the same material as the first dielectric layer 206a. Alternatively, the second dielectric layer 206b may include a material different from that of the first dielectric layer 206a. In this regard, the second dielectric layer 206b may be a polymer material such as polyimide, benzocyclobutene, or polybenzoxazole, and may be formed by a spin coating process. In other embodiments, the second dielectric layer 206b may include various other suitable polymers deposited by other deposition methods.

[0168] Figure 7C 1 is a vertical cross-sectional view of another intermediate structure 700c used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700c from the intermediate structure 700b can be to etch the second dielectric layer 206b to form the opening 404 on each of the via landing structures 210a. In this regard, a patterned photoresist (not shown) can be formed on the second dielectric layer 206b. Then, an etching process can be performed to etch the portion of the second dielectric layer 206b not masked by the patterned photoresist. Figure 7C As shown, a region of the second dielectric layer 206b may be etched down to the surface of the via landing structure 210a to form an opening 404. In this manner, the etching process used to create the opening 404 may expose the surface of the via landing structure 210a.

[0169] Figure 7D A vertical cross-sectional view of another intermediate structure 700d used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700d from the intermediate structure 700c may be to form the conductive seed layer 406 on the intermediate structure 700d. Figure 7C The conductive seed layer 406 may be formed on the intermediate structure 700c by sputtering and may include a metal material such as copper, titanium, or the like. For example, the conductive seed layer 406 may be a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may be 50 nm to 300 nm, while the thickness of the copper seed layer may be 100 nm to 500 nm. The conductive seed layer 406 of other embodiments may also be made of various other materials and thicknesses. The conductive seed layer 406 may form a conductive contact with the first via landing structure 210a.

[0170] Figure 7E A vertical cross-sectional view of another intermediate structure 700e used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700e from the intermediate structure 700d can be to deposit the conductive material 408 on the intermediate structure 700e. Figure 7D The conductive material 408 may be a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), deposited by electroplating. The metal filler material may be deposited to a thickness of 2 to 40 microns, such as 4 to 10 microns, although smaller or larger thicknesses may be employed. Various other conductive materials and deposition methods may also be employed in other embodiments.

[0171] Figure 7F A vertical cross-sectional view of another intermediate structure 700f used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700f from the intermediate structure 700e can be to form a patterned photoresist 410 on Figure 7E In this regard, a blanket layer of photoresist (not shown) can be deposited on the surface of the conductive material 408 of the intermediate structure 700e. The blanket layer of photoresist can then be patterned using photolithography techniques to form a patterned photoresist 410. The patterned photoresist 410 can then be used to etch the conductive material 408 during an anisotropic etching process, such as with Figure 7G Details are given below.

[0172] Figure 7G FIG. 7 is a vertical cross-sectional view of another intermediate structure 700g used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700g from the intermediate structure 700f can be to perform an anisotropic etching process to etch the conductive material 408. As shown in the figure, the etching process can be performed to remove the unmasked portion of the conductive material 408. Figure 7G As shown, the etching process can produce the conductive via structure 204 and the second conductive line structure 208b. In this way, the conductive via structure 204 can each form an integral structure with the respective second conductive line structure 208b. Figure 7GAs shown, a conductive connection may be formed between the conductive via structure 204 and the via landing structure 210 a via the connection provided by the conductive seed layer 406 .

[0173] Figure 7H A vertical cross-sectional view of another intermediate structure 700h used to form the interposer 108d in various embodiments. The method of forming the intermediate structure 700h from the intermediate structure 700g can be to remove Figure 7G The patterned photoresist 410 of the intermediate structure 700g is removed. In this regard, the removal method of the patterned photoresist 410 can be ashing or dissolving with a solvent. Then, an additional interconnect layer can be formed on the intermediate structure 700h, and its formation method can be performed by performing additional process steps, which can be combined with Figures 7A to 7G For example, in an additional process step, a third dielectric layer 206c may be formed on the intermediate structure 700h to form Figure 6A and Figure 6B The final structure (see Figure 6A and 6B ) can then be used as a starting point for forming additional interconnect layers, using a process that can be combined with 7A to 7H The process described above is similar.

[0174] Figure 8 The flowchart of method 800 for forming an interposer (108b, 108c) in various embodiments is shown. In step 802 of method 800, a first conductive trace structure 208a may be formed on a first dielectric layer 206a. In step 804 of method 800, a second dielectric layer 206b may be formed on the first conductive trace structure 208a. In step 806 of method 800, a conductive via structure 204 may be formed in the second dielectric layer 206b, establishing an electrical connection between the first conductive trace structure 208a and the conductive via structure 204. In step 808 of method 800, a second conductive trace structure 208b may be formed to form an integral structure with the conductive via structure 204.

[0175] In step 806 of the method 800 for forming the conductive via structure 204, the method 800 may further include forming the conductive via structure 204 on the first conductive line structure 208a, such that the conductive via structure 204 is electrically connected to and partially surrounds a portion of the first conductive line structure 208a. In this regard, the method 800 may further include forming a conductive seed layer 406 on the first conductive line structure 208a, and depositing a conductive material 408 on the conductive seed layer 406, such that an electrical connection is formed between the first conductive line structure 208a, the conductive seed layer 406, and the conductive material 408. In these embodiments, the method 800 may further include forming a via landing structure 210a electrically connected to the first conductive line structure 208a, and the via landing structure 210a may include an elongated structure having a landing width 212a1 that is smaller than a landing length 212a2.

[0176] In step 808 of the method 800 for forming the second conductive line structure 208b on the conductive via structure 204, the first set of steps (see Figures 4A to 4H ) or the second set of steps (see 5A to 5I In this regard, in some embodiments, the first set of steps may include forming a first patterned photoresist 410 on the surface of the conductive material 408 forming the conductive via structure 204; and etching the conductive material 408 to form the second conductive line structure 208b. In other embodiments, the second set of steps may include forming a second patterned photoresist 410 on the second dielectric layer 206b, such that the opening 404 of the second patterned photoresist 410 is located above the conductive via structure 204; and depositing a second conductive material 408 into the opening 404 of the second patterned photoresist 410, such that the second conductive material 408 forms the second conductive line structure 208b.

[0177] As shown in all figures and various embodiments of the present invention, interposers (108b, 108c, 108d) are provided. The interposers (108b, 108c, 108d) may include a first conductive trace structure 208a and a conductive via structure 204 electrically connected to the first conductive trace structure 208a. The interposers (108b, 108c, 108d) may further include a second conductive trace structure 208b, which forms a monolithic structure with the conductive via structure 204.

[0178] In various embodiments of the interposer ( 108 b , 108 c ), a portion 302 of the first conductive trace structure 208 a is disposed within the conductive via structure 204 , such that the first conductive trace structure 208 a at least partially overlaps the conductive via structure 204 . In various embodiments, the first conductive trace structure 208 a and the conductive via structure 204 share a common surface 304 . In various embodiments, the first trace thickness 218 a of the first conductive trace structure 208 a is less than the via thickness 220 of the conductive via structure 204 , such that the first conductive trace structure 208 a at least partially overlaps the conductive via structure 204 along the thickness direction (e.g., the z-direction). In these embodiments, the total spacing between the first conductive trace structure 208 a and the conductive via structure 204 along the thickness direction is equal to the via thickness 220 .

[0179] In other embodiments, the first line width 216a of the first conductive line structure 208a is smaller than the through-hole width (214a, 214b) of the conductive via structure 204, such that the first conductive line structure 208a at least partially overlaps the conductive via structure 204 along the width direction. In other embodiments, the total space between the first conductive line structure 208a and the conductive via structure 204 along the width direction is equal to the through-hole width (214a, 214b).

[0180] A first conductive line structure 208a may be formed on the first dielectric layer 206a; a second dielectric layer 206b may be formed on the first dielectric layer 206a; and a conductive via structure 204 may be formed in the second dielectric layer 206b on a portion 302 of the first conductive line structure 208a to form an electrical connection to the first conductive line structure 208a. The interposer (108b, 108c) may further include a conductive seed layer 406 formed between the first conductive line structure 208a and the conductive via structure 204. A portion 302 of the first conductive line structure 208a is embedded in the conductive via structure 204, so that the first conductive line structure 208a and the conductive via structure 204 share a common connection volume (see Figure 3A 、 Figure 3D and Figure 3F ).

[0181] In various embodiments, the second conductive line structure 208b includes a second line thickness 218b and contacts the surface 306 of the conductive via structure 204. In addition, the surface of the conductive via structure 204 can be perpendicular to the thickness direction (e.g., the z-direction), so that the first total space between the second conductive line structure 208b and the conductive via structure 204 along the thickness direction is greater than the via thickness 220 (see FIG. Figure 2 and Figure 3A). In addition, in various embodiments, the second total space of the second conductive line structure 208b and the conductive through-hole structure 204 along the thickness direction is the sum of the through-hole thickness 220 and the second line thickness 218b (see Figure 2 and Figure 3A ).

[0182] In various embodiments, the interposer (108b, 108c) may further include a via landing structure 210a electrically connected to the first conductive line structure 208a, such that the via landing structure 210a includes an elongated structure having a landing width 212a1 smaller than a landing length 212a2. For example, the via landing structure 210a may further include an elongated oval structure (see FIG. Figure 6C and 6D ).

[0183] In various embodiments, additional interposers (108b, 108c) are provided. The interposers (108b, 108c) may include a first dielectric layer 206a; a second dielectric layer 206b formed on the first dielectric layer 206a; a first conductive line structure 208a formed on the first dielectric layer 206a and within the second dielectric layer 206b; and a conductive via structure 204 formed within the second dielectric layer 206b and on the first conductive line structure 208a, such that the conductive via structure 204 is electrically connected to and at least partially surrounds a portion 302 of the first conductive line structure 208a.

[0184] In various other embodiments, additional interposers (108b, 108c) are provided. The interposers (108b and 108c) may include a first dielectric layer 206a; a second dielectric layer 206b formed on the first dielectric layer 206a; a first conductive trace structure 208a formed on the first dielectric layer 206a and within the second dielectric layer 206b; and a conductive via structure 204 formed within the second dielectric layer 206b. The interposers (108b, 108c) may further include a second conductive trace structure 208b that forms a unitary structure with the conductive via structure 204. In some embodiments, the conductive via structure 204 may be formed within the second dielectric layer 206b and above the first conductive trace structure 208a, such that the conductive via structure 204 is electrically connected to and at least partially surrounds a portion of the first conductive trace structure 208a.

[0185] In various embodiments, the first line thickness 218a of the first conductive line structure 208a is less than the through-hole thickness 220 of the conductive via structure 204, such that the total spacing between the first conductive line structure 208a and the conductive via structure 204 along the thickness direction is equal to the through-hole thickness 220. The first line width 216a of the first conductive line structure 208a can be less than the through-hole widths (214a, 214b) of the conductive via structure 204, such that the total spacing between the first conductive line structure 208a and the conductive via structure 204 along the width direction is equal to the through-hole widths (214a, 214b). The interposer (108b, 108c) can further include a third dielectric layer 206c formed on the second dielectric layer 206b. In various embodiments, the second conductive line structure 208b can be formed on the second dielectric layer 206b and within the third dielectric layer 206c, such that the second conductive line structure 208b is electrically connected to the conductive via structure 204. In other embodiments, the interposer ( 108 b , 108 c ) may further include a via landing structure 210 a electrically connected to the first conductive trace structure 208 a . Furthermore, in some embodiments, the via landing structure 210 a may include an elongated structure having a landing width 212 a 1 smaller than a landing length 212 a 2 .

[0186] The above-mentioned embodiments may provide more advantages than the conventional semiconductor package 100. In this regard, the embodiments may provide an interposer (108b, 108c, 108d) with an increased internal connection density to simplify the method of forming the semiconductor package 100. In these embodiments, the interposer (108b, 108c) may include a first conductive line structure 208a and a conductive through-hole structure 204 formed on the first conductive line structure 208a, so that the conductive through-hole structure 204 is electrically connected to and partially surrounds a portion 302 of the first conductive line structure 208a. In this manner, the portion 302 of the first conductive line structure may protrude into the conductive through-hole structure 204 to overlap with the conductive through-hole structure 204. In this way, the first conductive line structure 208a and the conductive through-hole structure 204 are connected in the thickness direction (such as Figure 2 and Figure 3A The total space of the first conductive circuit structure 208a and the conductive through-hole structure 204 along the width direction (eg, z direction) may be smaller than the through-hole thickness 220. Figure 2 and Figure 3A The total space (in the x-direction) can be equal to the through-hole width (214a, 214b). In this way, the vertical and horizontal densities of the interconnect structures can be increased.

[0187] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a foundation to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. An interposer, characterized in that: include: a first conductive circuit structure; a conductive via structure electrically connected to the first conductive circuit structure, wherein a portion of the first conductive circuit structure is disposed in the conductive via structure such that the first conductive circuit structure and the conductive via structure at least partially overlap; as well as A second conductive circuit structure forms an integral structure together with the conductive through-hole structure.

2. The interposer according to claim 1, wherein: The first conductive circuit structure and the conductive through-hole structure share a common surface.

3. The interposer according to claim 2, wherein: A first circuit thickness of the first conductive circuit structure is smaller than a through-hole thickness of the conductive through-hole structure, so that the first conductive circuit structure at least partially overlaps with the conductive through-hole structure along a thickness direction.

4. The interposer according to claim 3, wherein: A total space between the first conductive circuit structure and the conductive through-hole structure along the thickness direction is equal to the through-hole thickness.

5. The interposer according to claim 2, wherein: A first line width of the first conductive line structure is smaller than a through-hole width of the conductive through-hole structure, so that the first conductive line structure at least partially overlaps with the conductive through-hole structure along a width direction.

6. The interposer according to claim 5, wherein: A total space between the first conductive circuit structure and the conductive through-hole structure along the width direction is equal to the through-hole width.

7. The interposer according to claim 1 or 2, wherein: The first conductive circuit structure is formed on a first dielectric layer; a second dielectric layer formed on the first dielectric layer; and The conductive via structure is formed in the second dielectric layer on a portion of the first conductive circuit structure to form an electrical connection to the first conductive circuit structure.

8. An interposer, characterized in that: include: a first dielectric layer; a second dielectric layer formed on the first dielectric layer; a first conductive circuit structure formed on the first dielectric layer and in the second dielectric layer; a conductive via structure formed in the second dielectric layer; as well as A second conductive circuit structure forms an integral structure together with the conductive through-hole structure.

9. The interposer according to claim 8, wherein: The conductive via structure is formed in the second dielectric layer and on the first conductive circuit structure, so that the conductive via structure is electrically connected to and at least partially surrounds a portion of the first conductive circuit structure; and A first circuit thickness of the first conductive circuit structure is smaller than a through-hole thickness of the conductive through-hole structure, so that a total space between the first conductive circuit structure and the conductive through-hole structure along a thickness direction is equal to the through-hole thickness.

10. The interposer according to claim 8 or 9, characterized in that: Also includes: a third dielectric layer formed on the second dielectric layer; The second conductive circuit structure is formed on the second dielectric layer and in the third dielectric layer, so that the second conductive circuit structure is electrically connected to the conductive through-hole structure.

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