Integrated circuit device

Abstract

An apparatus includes first to third power / ground (PG) elements; the first group of at least three conductive tracks are located between the first and second PG conductive elements, the second group of at least three conductive tracks are located between the second and third PG conductive elements, and the conductive tracks are arranged between the first and second PG conductive elements and between the second and third PG conductive elements in equal number; the first row unit overlaps the first group; and the second row unit overlaps the second group. In the first row of units, the first unit has a first height and the height of the second unit is greater than the first height; in the second row of units, the third unit has a first height, and the height of the fourth unit is smaller than the first height; and the conductive track is configured as an in-cell PG track which is aligned with the boundary of the second cell and the fourth cell.

Description

Technical Field

[0001] An embodiment of the present utility model relates to an integrated circuit device. Background Art

[0002] Devices such as semiconductor devices can have a structure that is laid out based on functional cells. A simple layout can use cells of uniform size, such as uniform cell height. Such a layout can be simple to design, but can produce relatively large devices, such as devices with large die sizes, and thus may exhibit relatively low PPA (power, performance, and area) characteristics. Another layout can use cells of more than one size (e.g., more than one cell height), which can enable the design of relatively small devices. Utility Model Content

[0003] An embodiment of the present invention provides an integrated circuit device comprising: first, second and third power / ground (PG) conductive elements extending along a first direction; a first group of at least three conductive tracks located between the first PG conductive element and the second PG conductive element, and a second group of at least three conductive tracks located between the second PG conductive element and the third PG conductive element, the conductive tracks being arranged in equal numbers between the first PG conductive element and the second PG conductive element and between the second PG conductive element and the third PG conductive element; a first row of cells being arranged in the first direction and overlapping with the first group of at least three conductive tracks; and a second row of cells being arranged in the first direction and overlapping with the second group of at least three conductive tracks. In some embodiments, in a first row of cells, the first cell has a first height in a second direction orthogonal to the first direction, in the first row of cells, the height of the second cell is greater than the first height, in a second row of cells, the third cell shares a boundary extending in the first direction with the first cell and has the first height, in the second row of cells, the fourth cell shares a boundary extending in the first direction with the second cell and has a height less than the first height, the combined height of the second cell and the fourth cell corresponds to the combined height of the first cell and the third cell, and between the second PG conductive element and the third PG conductive element, the conductive track is aligned with the boundary extending in the first direction of the second cell and the fourth cell and is configured as an intra-cell PG track.

[0004] In some embodiments, the first row of cells and the second row of cells each have at least one active area formed in a substrate, the at least one active area extending along a first direction, and the conductive tracks are located in the lowest conductive material layer above the substrate. In some embodiments, all conductive tracks have the same size in a second direction. In some embodiments, the first cell has a first active area extending along the first direction, the second cell has a second active area extending along the first direction, and a first isolation pattern isolates the second active area from the first active area, the first isolation pattern extending along the second direction; and the third cell has a third active area extending along the first direction, the fourth cell has a fourth active area extending along the first direction, and a second isolation pattern isolates the third active area, the second isolation pattern extending along the second direction. In some embodiments, the second isolation pattern is aligned with the first isolation pattern. In some embodiments, the first isolation pattern and the second isolation pattern are each continuous polysilicon on oxide defined edge (CPODE) patterns. In some embodiments, the first cell has a first active region extending along a first direction, the second cell has a second active region extending along the first direction, and the first active region has a smaller dimension in the second direction than the second active region; and the third cell has a third active region extending along the first direction, the fourth cell has a fourth active region extending along the first direction, and the third active region has a larger dimension in the second direction than the fourth active region. In some embodiments, the second PG conductive element is aligned with a boundary extending in the second direction between the first and third cells. In some embodiments, the intra-cell PG rail is electrically connected to the second PG conductive element via a connection to the third cell or a connection between the second and third cells. In some embodiments, the fourth cell includes a transistor, and the intra-cell PG rail is electrically connected to the source of the transistor.

[0005] An embodiment of the present invention provides an integrated circuit device comprising: first, second, and third power / ground (PG) conductive elements extending along a first direction; a first group of at least three conductive tracks located between the first and second PG conductive elements, and a second group of at least three conductive tracks located between the second and third PG conductive elements, with the conductive tracks arranged in equal numbers between the first and second PG conductive elements and between the second and third PG conductive elements; a first unit having a first height in a second direction orthogonal to the first direction and overlapping with all of the first group of at least three conductive tracks; a second unit having a second height and overlapping with all of the first group of at least three conductive tracks and at least one of the second group of at least three conductive tracks, such that the second height is greater than the first height; a third unit overlapping with all of the second group of at least three conductive tracks and having the first height, such that the first unit and the third unit have the same height; and a fourth unit having a fourth height and overlapping with less than all of the second group of at least three conductive tracks, such that the combined height of the first and third units is the same as the combined height of the second and fourth units.

[0006] In some embodiments, in the fourth cell, the conductive track is configured as an intra-cell PG track extending along a first direction, and the intra-cell PG track is electrically connected to the source of the transistor. In some embodiments, the first PG conductive element, the second PG conductive element, the third PG conductive element, the first set of at least three conductive tracks, and the second set of at least three conductive tracks are formed in the same first layer, and the intra-cell PG track is connected to the second PG conductive element via an extended via connection extending in a second direction and contacting the intra-cell PG track and the second PG conductive element. In some embodiments, the first, second, third, and fourth cells each have at least one active region formed in the substrate, a diffused upper metal layer positioned above the active region, the first layer being the lowest conductive material layer above the diffused upper metal layer, and the extended via connection aligned with the diffused upper metal element and interposed between the diffused upper metal element and the first layer. In some embodiments, the first, second, third, and fourth cells each have at least one active region formed in the substrate, the fourth cell includes a transistor having a gate, and the extended via connection aligned with the gate and interposed between the gate and the first layer. In some embodiments, the filling cell extends along the second direction between the first and third cells and between the second and fourth cells, and the intra-cell PG track and the second PG conductive element are electrically connected via connections within the filling cell. In some embodiments, the first PG conductive element, the second PG conductive element, the third PG conductive element, the first group of at least three conductive tracks, and the second group of at least three conductive tracks are formed in the same first layer. The first, second, third, and fourth cells each have at least one active region formed in the substrate, a diffused upper metal layer is located above the active region, the first layer is the lowest conductive material layer above the diffused upper metal layer, and the connection is aligned with the diffused upper metal element in the filling cell and interposed between the diffused upper metal element and the first layer. In some embodiments, the height of the second PG conductive element in the second direction varies within the filling cell, and in the fourth cell, the second PG conductive element and the intra-cell PG track are integral along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a diagram of an example layout of a compatible hybrid cell structure according to an embodiment.

[0009] Figure 2 is a diagram of another example layout of a compatible hybrid cell structure according to an embodiment.

[0010] Figure 3 FIG. 1 is a diagram illustrating layouts according to an embodiment, including a layout with cells of uniform height and a layout with cells of mixed heights.

[0011] Figure 4A and Figure 4B is a diagram illustrating aspects of cells in a layout according to some embodiments.

[0012] Figure 5 is a diagram of cells in various layouts according to some embodiments.

[0013] Figure 6 is a diagram of an example of a front-end of line (FEOL) structure according to some embodiments.

[0014] Figure 7 is a diagram of an example of a back-end of line (BEOL) structure according to some embodiments.

[0015] Figure 8 is a diagram of examples of adjacent intra-cell power / ground (ICPG) tracks and examples of non-adjacent ICPG tracks, according to an embodiment.

[0016] Figure 9 is a diagram of an example layout with adjacent ICPG tracks according to one embodiment.

[0017] Figure 10A and Figure 10B is a diagram of a first example connection structure for an ICPG track according to one embodiment.

[0018] Figure 10C and Figure 10D FIG. 1 is a diagram illustrating a connection state of the slot VD2 according to an embodiment.

[0019] Figure 11A and Figure 11B is a diagram of a second example connection structure according to an embodiment.

[0020] Figure 11C and Figure 11D FIG. 1 is a diagram illustrating a connection state of a slot VIA0 according to an embodiment.

[0021] Figure 12A and Figure 12B is a diagram of a third exemplary connection structure according to an embodiment.

[0022] Figure 12C FIG. 1 is a diagram illustrating a connection state of a filling unit according to an embodiment.

[0023] Figure 13A and Figure 13B is a diagram of a fourth exemplary connection structure according to an embodiment.

[0024] Figure 13C and Figure 13D FIG. 1 is a diagram illustrating a connection state of filling units having an integral structure according to an embodiment.

[0025] Figure 14 is a diagram illustrating aspects of an example process flow for forming wide PG tracks according to one embodiment.

[0026] Figure 15 FIG. 1 is a diagram illustrating a layout according to an embodiment of the present invention.

[0027] Figure 16 is a block diagram of an electronic process control (EPC) system according to one embodiment.

[0028] Figure 17 is a block diagram of an IC manufacturing system according to one embodiment. DETAILED DESCRIPTION

[0029] This disclosure describes embodiments and examples of the subject matter set forth herein, and although specific examples of components, materials, values, steps, arrangements, etc. may be described, such examples are not limiting, and other components, materials, values, steps, arrangements, etc. are contemplated.

[0030] As used herein, unless otherwise indicated, terms preceded by "a" or "an" (or "the" when the antecedent basis is "a" or "an") designate both the singular and the plural of the term.

[0031] In addition, throughout this disclosure and the accompanying drawings, similar symbols are intended to represent similar elements, but similar symbols or other element numbers do not imply a specific hierarchy or order. Similarly, references to "first," "second," "third," etc. do not imply a specific order.

[0032] In addition, the description of a first element being "on" a second element may include a situation where the first element is directly on the second element, that is, a situation where the first element is in direct contact with the second element, and may also include a situation where an additional element is located between the first element and the second element, for example, a situation where the first element does not directly contact the second element.

[0033] Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having," and variations thereof, represent a non-exclusive inclusion. For example, a process, article, or apparatus that "comprises" a list or group of recited elements is not limited to only those elements but may include other elements not expressly listed or described.

[0034] In addition, the term "or" is inclusive rather than exclusive, such that the term "or" means "and / or" unless otherwise specified. Thus, unless otherwise specified, "A or B" means "A and / or B" and covers A alone, B alone, and both A and B.

[0035] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures, but are not intended to imply a fixed orientation. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations than the orientation depicted in the figures.

[0036] Furthermore, "source / drain(s)" may be referred to individually or collectively as a source or a drain, depending on the context.

[0037] In some embodiments, a device includes first to third power / ground (PG) elements. The device includes a first group of at least three conductive tracks between the first and second PGs and a second group of at least three conductive tracks between the second and third PGs, which are arranged in equal numbers between the first and second PG elements and between the second and third PG elements. The device includes a first row of cells overlapping with the first group and a second row of cells overlapping with the second group. In the first row of cells, the first cell has a first height and the height of the second cell is greater than the first height. In the second row of cells, the third cell has a first height and the height of the fourth cell is less than the first height. The device includes PG tracks configured as in-cells and aligned with the boundaries of the second and fourth cells. In some embodiments, the boundaries between vertically adjacent cells correspond to power or ground elements or in-cell power or ground elements.

[0038] In some embodiments, an integrated circuit and / or corresponding layout includes cells of various cell heights. In some embodiments, the various cell heights allow for greater flexibility in circuit layout. Integrated circuits and / or layouts according to some embodiments provide the benefits associated with using columns having respective cell heights while also being compatible with layout elements that use cells of uniform cell height in adjacent columns.

[0039] Figure 1 is a diagram of an example layout of a compatible hybrid cell structure according to an embodiment.

[0040] Reference Figure 1, the example layout 100 includes cells having a first cell height and cells having a cell height different from the first cell height. In some embodiments, each cell is used as a standard cell in a standard cell library. In some embodiments, the cell is used for a finFET transistor and includes a substantially parallel Figure 1 In some embodiments, the nanosheets are substantially parallel to the horizontal or X-axis of the fin pattern. Figure 1 The X-axis extension in .

[0041] Figure 1 10. In the example embodiment, cell 1010 has a first cell height, while cells 1020 and 1030 have cell heights different from the first cell height. Herein, cell 1010 is also referred to as having a medium cell height, cell 1020 is also referred to as having a small cell height, and cell 1030 is also referred to as having a large cell height. In some cases, for simplicity, cell 1010 is referred to as a medium cell, cell 1020 is referred to as a small cell, and cell 1030 is referred to as a large cell. The terms "medium," "small," and "large" merely describe relative heights relative to one another.

[0042] In some embodiments, the boundaries between vertically adjacent cells (e.g., Figure 1 The boundary between two cells 1010 in the example, parallel to the X-axis, or the boundary between cell 1030 and cell 1020, parallel to the X-axis, corresponds to a power or ground element or an intra-cell power or ground element. In some embodiments, the boundary between vertically adjacent cells is aligned with the middle of the width of the power or ground element or the intra-cell power or ground element, which is determined in the vertical dimension (parallel to the X-axis). Figure 1 the vertical axis or Y axis in the .

[0043] Figure 1 Includes power / ground (PG) rails and rails 1100. In some embodiments, the PG rails and rails 1100 extend parallel to the X-axis. In some embodiments, such as with the lower connection, for example Figure 9 、 Figure 10A 、 Figures 11A-11B 、 Figures 12A-12B and Figures 13A-13B In further detail, the PG rail extends along multiple cells, while the track 1100 extends within a cell. In some embodiments, the track 1100 does not extend into laterally adjacent cells.

[0044] In some embodiments, the PG rail and track 1100 are electrically conductive. In some embodiments, the PG rail and track 1100 are formed of metal or another electrically conductive material.

[0045] In some embodiments, the PG rail is used to provide power to circuits within the cell. In some embodiments, the PG rail is part of a power grid that provides power to a device. For example, in some embodiments, the PG rail is used to provide a first power supply voltage and a second power supply voltage, such as a first constant power supply voltage and a second constant power supply voltage. For example, in some embodiments, the PG rail is used to provide power and ground, VSS and VDD, etc. In some embodiments, rail 1100 is used to provide signals, such as control signals, to circuits formed within the cell.

[0046] exist Figure 1 In the middle, the middle unit 1010 overlaps two PG rails. Figure 1 Each middle unit 1010 also overlaps all of the tracks 1100 between each pair of adjacent PG rails.

[0047] In some embodiments, one or more tracks 1100 are used as in-cell power / ground (ICPG) tracks. In some embodiments, the ICPG track is used to provide power to circuit elements in the cell, such as transistors. In some embodiments, the ICPG track is part of a power grid. For example, in some embodiments, the ICPG track is used to provide a first power supply voltage or a second power supply voltage, such as a first constant power supply voltage or a second constant power supply voltage. For example, in some embodiments, the ICPG track is used to provide power or ground, VSS or VDD, etc.

[0048] In some embodiments, reference Figure 1 , the ICPG track is directly adjacent to the PG track. In other embodiments (described below but not in Figure 1 ), the ICPG track is not adjacent to the PG rail, that is, a track 1100 other than the ICPG track (eg, an interlayer track 1100) is inserted between the PG rail and the ICPG track.

[0049] exist Figure 1 In some embodiments, the small unit 1020 overlaps with only one PG rail. In some embodiments, the small unit 1020 overlaps with the ICPG rail, for example, at the top or bottom extent of the small unit 1020. In some embodiments, the ICPG rail of the small unit 1020 is connected to the PG rail using various structures, examples of which are described herein.

[0050] In some embodiments, the various cells include active devices, such as transistors, that receive power, such as power or ground, from the PG rail and / or the ICPG rail. For example, in some embodiments, cell 1020 includes a transistor, and Figure 1The ICPG rail is electrically connected to the source or drain of the transistor. In some embodiments, the large unit 1030 includes a first transistor having a source connected to the ICPG rail, and the small unit 1020 includes a second transistor having a source connected to the ICPG rail. In some embodiments, the first transistor and the second transistor each receive power from the ICPG rail, and the power of the ICPG rail is provided by the PG rail.

[0051] exist Figure 1 In some embodiments, the small unit 1020 overlaps all of the tracks 1100 between adjacent PG rails; however, in other embodiments, the small unit 1020 overlaps less of all of the tracks 1100 between adjacent PG rails. For example, in some embodiments, the small unit 1020 has non-adjacent ICPG tracks (described further below), and the top or bottom extent of the small unit 1020 corresponds to the non-adjacent ICPG tracks.

[0052] exist Figure 1 In FIG, the large unit 1030 overlaps the two PG rails, all the tracks 1100 between the two PG rails, and the additional track (ie, the ICPG track).

[0053] Figure 1 , the large unit 1030 is shown as overlapping an adjacent ICPG track; however, in other embodiments, the large unit 1030 overlaps with more than one additional track, for example, one or more sandwiched tracks 1100 and non-adjacent ICPG tracks.

[0054] In some embodiments, the PG rails are evenly spaced and have the same pitch throughout the layout 100. In some embodiments, the PG rails are separated by a constant number of rails 1100 throughout the layout 100, i.e., in some embodiments, the total number of rails 1100 between each pair of adjacent PG rails is constant. In some embodiments, this includes the case where the rails 1100 are used as ICPG rails. For example, Figure 1 There are a total of four tracks 1100 between each pair of adjacent PG tracks, including the case where there are three tracks 1100 and one ICPG track between an adjacent pair of PG tracks.

[0055] The constant number of tracks 1100 in layout 100 can be viewed as the number of tracks per row of cells. In some embodiments, layout 100 has cells (e.g., middle cell 1010) arranged in rows in layout 100. In some embodiments, each row has the same number of tracks 1100.

[0056] Figure 2 is a diagram of another example layout of a compatible hybrid cell structure according to an embodiment.

[0057] exist Figure 2In the example layout 200, the cells having a first cell height and cells having a cell height different from the first cell height are shown. Figure 1 As shown. Figure 2 The middle unit 1010 has a first unit height, and the small unit 1020 and the large unit 1030 have unit heights different from the first unit height, such as Figure 1 shown.

[0058] In some embodiments, the combined height of a unit 1020 having a small height and a unit 1030 having a large height is the same as twice the height of the middle unit 1010 , ie, the same as the combined height of two units 1010 having the middle unit height.

[0059] Figure 2 The medium unit 1040 may be referred to as having an extra large unit height. For simplicity, the unit 1040 having an extra large unit height may be referred to as an extra large unit herein. The terms "medium," "small," "large," and "extra large" describe heights relative to one another.

[0060] In some embodiments, the diversity of different cells (i.e., a diversity of cells of different cell heights) allows for greater flexibility in circuit layout. In some embodiments, this greater flexibility can enable performance improvements, such as faster speed, lower power consumption, and / or reduced circuit or die area. For example, in some embodiments, small cells 1020 can enable circuit elements that exhibit relatively low power consumption, medium cells 1010 can enable general driving coverage with relatively moderate area requirements, and large cells 1030 and extra-large cells 1040 can enable relatively high speed. In some embodiments, a variety of cell heights are implemented in layout 200 to enable circuit designs with overall enhanced PPA through greater driving coverage.

[0061] exist Figure 2 In , some units are highly combined with the above units. For example, Figure 2 Included are double mid-height units 1011. In addition, Figure 2 A unit 1050 having a unit height corresponding to the combined unit height of a small unit 1020 and a large unit 1030, ie, large+small, is included, and is referred to as a double unit (ie, twice the height of the medium unit 1010). Figure 2A unit 1060 is included, having a unit height corresponding to the combined unit height of a small unit 1020, an extra-large unit 1040, and another small unit 1020 (i.e., small + extra-large + small). The unit height of unit 1060 corresponds to the triple height of medium unit 1010 (i.e., unit 1060 has a unit height corresponding to the combined unit height of three medium units 1010), and unit 1060 is referred to as a triple unit. It should be understood that the terms "medium," "small," "large," and "extra-large" describe heights relative to one another.

[0062] exist Figure 2 In the example, each middle unit 1010 overlaps two PG rails, and each middle unit 1010 also overlaps all the tracks 1100 between each pair of adjacent PG rails, as shown in FIG. Figure 1 As shown. Figure 2 In, such as Figure 1 Likewise, the small cell 1020 overlaps only one PG rail, while the large cell 1030 overlaps two PG rails, all tracks 1100 between the two PG rails, and the additional track. The large cell 1030 overlaps more than one additional track.

[0063] exist Figure 2 In the embodiment, the supercell 1040 overlaps two PG rails, all tracks 1100 between the two PG rails, and two additional tracks (ie, two ICPG tracks). In some embodiments, the supercell 1040 overlaps more than two additional tracks.

[0064] In some embodiments, dual cell 1050 and triple cell 1060 each have a cell height corresponding to a spacing of more than two PG rails, eg, three PG rails for dual cell 1050 and four PG rails for triple cell 1060 .

[0065] The layout 200 includes cells having a cell height corresponding to the spacing of the PG rails, the spacing of the PG rail and the ICPG rail, and the spacing of the two ICPG rails.

[0066] In layout 200, each pair of adjacent PG rails has the same number of tracks 1100 between them, some of which are designated as ICPG tracks. Figure 2 Four tracks are shown between each pair of adjacent PG rails, either tracks 1100 or a combination of tracks 1100 and ICPG tracks. Layout 200 shows four tracks for descriptive purposes only; the number of tracks is not limited to four.

[0067] In some embodiments, the PG rail and / or track 1100 is formed in the lowest layer of conductive material above the substrate. In some embodiments, the lowest layer of conductive material above the substrate is a first metal layer or a metal zero (M0) layer.

[0068] In some embodiments, at the M0 layer, the same number of M0 tracks are located between all PG rails. As described below, in some embodiments, some M0 tracks are connected to the power / ground grid to serve as ICPG tracks.

[0069] Figure 3 FIG. 1 is a diagram illustrating layouts according to an embodiment, including a layout with cells of uniform height and a layout with cells of mixed heights.

[0070] Figure 3 is a diagram of an example layout 250 , where shared aspects are layout 100 and layout 200 , relative to a layout UC having cells of uniform height and a layout HC having cells of mixed height.

[0071] As a review, another layout design approach uses a series of cell rows where all cells in all rows have a uniform cell height and all rows have the same number of rails per row. This can be referred to as a uniform cell layout UC. In an example of a uniform cell layout UC, power rails (e.g., rails providing VDD and VSS) are uniformly spaced throughout the layout. In an example, a layout designed using a uniform cell row is formed using, for example, all medium height cells (mh), all long height cells (th), or all short height cells (sh), such that the cells of each row of the layout have the same cell height, for example, all rows are medium height cells, all rows are long height cells, or all rows are short height cells. As an example, Figure 3 A uniform cell layout UC with medium-height cells (mh) is shown, including dual medium-height cells (2×mh). Taking the characteristics of medium-height cells as a reference, a layout using tall cells can achieve relatively enhanced speed while occupying a relatively large area. Since the overall die size may be larger, it is undesirable to use a larger area in some cases. On the other hand, again using medium-height cells as a reference, a layout using short cells can achieve a relatively small area while providing relatively lower speed.

[0072] A second layout design approach is to use rows of cells having uniform cell heights within each row, but having different cell heights within different rows, and having different active area widths and / or numbers of tracks for rows of different heights, also referred to as a hybrid cell layout HC. In an example of a hybrid cell layout HC, power rails (e.g., rails providing VDD and VSS) are separated by a first distance or a second distance different from the first distance. In an example, a layout using a hybrid cell row design is formed using rows with different cell heights, for example, an alternating arrangement of rows in which long height cells (th) and short height cells (sh) alternate row by row, and within each row, all cells have the same height. For example, Figure 3 A layout HC is shown having long-height cells (th) in alternating rows, short-height cells (sh) in alternating rows, and multiple-height cells (tsh) having a cell height corresponding to the combined height of a long-height cell (th) and a short-height cell (sh). In an example of a mixed cell layout HC, alternating rows of different cell heights are provided, wherein a first row having a larger height has a first number of tracks, while a second row having a smaller height has a second number of tracks, the second number of tracks being smaller than the first number of tracks, and the first number of tracks and the second number of tracks are arranged alternately. Compared to a uniform cell row design, the mixed cell row design in some embodiments allows for greater speed in circuit design or layout within a smaller area.

[0073] On the other hand, in some embodiments, the first and second methods described above can be used together in the layout 250. In some embodiments, in the layout 250, a series of rows all have the same number of tracks (see Figure 1 and Figure 2 In the example of the track 1100 in FIG. 25 , there are cells with different cell heights. In the layout 250 , the power rails (e.g., the rails providing VDD and VSS) are uniformly spaced throughout the layout, e.g., with Figure 3 The uniform cell rows in the UC are arranged in the same manner as in the UC, and the power rails providing VDD and VSS are spaced apart in the height direction of the cell by a spacing corresponding to the height of the base cell (e.g., a medium-height cell (mh)). In some embodiments, the layout 250 thus also accommodates dual medium-height cells (2×mh).

[0074] Additionally, in some embodiments, layout 250 includes cells having cell heights that are greater than and / or less than the cell height of medium-height cells, and whose cell heights are not integer multiples of the medium-height cells. For example, in some embodiments, layout 250 includes cells having cell heights corresponding to the long-height cells (th) and short-height cells (sh) of the mixed cell row layout HC, although it may be advantageous to include even taller and shorter cells in layout 250. For example, layout 250 may include longer-height cells (tth) having a cell height greater than the cell height of the long-height cells (th), and shorter-height cells (ssh) having a cell height less than the cell height of the short-height cells (sh). In some embodiments, the cell height of the longer-height cells (tth) is less than twice the height of the medium-height cells (mh). In some embodiments, the cell height of the shorter-height cells (ssh) is less than the cell height of the medium-height cells (mh).

[0075] In some embodiments, as combined Figure 1 and Figure 2As depicted, one or more rails 1100 are used as intra-cell power / ground (ICPG) rails, with the ICPG rails corresponding to locations where the longer height cell (tth) and the shorter height cell (ssh) meet. For example, in some embodiments, along Figure 3 The conductive tracks positioned by the horizontal dashed lines in the layout 250 are designated as ICPG tracks and are powered from a power rail that provides VSS to the ICPG tracks for the shorter height cells (ssh). In some embodiments, cells having a cell height corresponding to a combination of cell heights are also used, for example, cells (ttssmh) having a cell height corresponding to a longer height cell (tth), a shorter height cell (ssh), and a medium height cell (mh) as shown in the layout 250, and / or cells (ttssh) having a cell height corresponding to a combined height of a longer height cell (tth) and a shorter height cell (ssh).

[0076] In some embodiments, layout 250, like layouts 100 and 200, can provide the benefits associated with using rows with varying cell heights, as in layout HC, while also being compatible with layout elements that use cells of uniform cell height in adjacent rows, as in layout UC. In some embodiments, layout 250 can enable a layout or circuit design that more closely resembles an ideal design. Thus, for example, layout 250, like layouts 100 and 200, can provide PPA enhancement by providing increased driver coverage. Furthermore, layout 250, like layouts 100 and 200, can allow for the use of cells (ssh) whose cell height is shorter than the short-height cells (sh) of layout HC.

[0077] As a specific example, a D flip-flop with scan input (SDFQ) circuit can be formed using a uniform cell layout UC, a mixed cell layout HC, and layout 250. The SDFQ can include multiple devices, some of which are located in the critical path and others that are not. An SDFQ formed using the HC layout can have a better overall PPA than an SDFQ formed using the UC layout. For example, the speed / area ratio of the HC layout can be better than that of the UC layout. However, the HC layout can introduce some difficulties. For example, when a given device in the critical path is formed in a short height cell (sh) rather than a long height cell (th), the given device may be formed to include, for example, a single finFET rather than the more preferred two finFETs due to, for example, routing requirements that make placement of the given device in the long height cell difficult. Such row limitations can result in a dragging effect on device performance, such as a reduction in speed or an increase in power consumption and / or area. On the other hand, layout 250 can provide a greater number of cell height options to optimize critical paths (compared to the single cell height of medium-height cells (mh) of layout UC and the two cell heights of long-height cells (th) and short-height cells of layout HC, to the three cell heights of medium-height cells (mh), taller-height cells (tth), and shorter-height cells (ssh) of layout 250, and note that the taller-height cells (tth) of layout 250 can improve drive coverage relative to the long-height cells (th) of layout HC), which may be advantageous in terms of cell height selection and / or routing connections (e.g., M0 routing connections). Moreover, in some embodiments, layout 250 enables the use of a cell grouping approach compared to the row-based approach used for layout UC and layout HC.

[0078] Again by way of specific example, the layout UC may be designed to have four M0 tracks between each pair of adjacent PG tracks (e.g., Figure 3 The layout HC can be designed to have alternating groups of four M0 tracks and three M0 tracks between each pair of adjacent PG rails (e.g., a group of four M0 tracks between VDD and VSS for long height cells (th) and a group of three M0 tracks between VDD and VSS for Figure 3 ), and the layout 250 can be designed to have four M0 tracks between each pair of adjacent PG tracks (e.g., Figure 3There is a set of four M0 traces between each adjacent pair of VDD and VSS in the layout 250). In layout HC, the cell height may be increased relative to layout UC (i.e., the long height cell (th) of layout HC may be longer than the medium height cell (mh) of layout UC), but this is accompanied by reduced height cells (short height cells (sh)) in layout HC with a smaller number of M0 tracks (three), and an entire row of short height cells (sh) with a smaller number of M0 tracks (three). On the other hand, in some embodiments, in layout 250, the reduced height cells (i.e., shorter height cells (ssh)) are equipped with their own ICPG tracks, so that adjacent cells in the row direction do not need to be restricted to a smaller number of tracks. Therefore, although layout HC has an entire row of short height cells (sh), layout 250 allows reduced height cells to be mixed with cells having other heights and the resulting greater number of tracks 1100. The following is combined Figure 2 and Figure 5 to describe in more detail.

[0079] Figure 4A and Figure 4B is a diagram illustrating aspects of cells in a layout according to some embodiments.

[0080] In some embodiments, reference Figure 4A and Figure 4B , the cell height is limited to the vertical dimension (parallel to Figure 2 In some embodiments, in a cell, the active areas (e.g., N-type active areas and P-type active areas) are referred to as oxide-defined (OD) areas. In some embodiments, the active areas have a height in the vertical dimension defined as the OD width, i.e., the measurement of the OD width is determined in the vertical dimension, i.e., parallel to the Y axis, and the active areas extend along the row direction, i.e., parallel to the X axis. In some embodiments, the active areas are separated by OD spaces (here, the measurement of the OD space is determined in the vertical dimension, i.e., parallel to the Y axis). In some embodiments, the cell height is equal to 2*(maximum OD width + minimum OD space). Another way to describe this relationship is that if the cell height is set or predefined, the OD width may be limited by the cell height.

[0081] In some embodiments, active regions in laterally adjacent cells are isolated from each other by isolation patterns. In some embodiments, the isolation patterns are continuous polysilicon on oxide definition edge (CPODE) patterns. In some embodiments, the isolation patterns in two adjacent rows are aligned parallel to the Y-axis.

[0082] In some embodiments, the lateral boundaries of the cell are defined by a CPODE pattern.

[0083] exist Figure 4B In the example, “U” represents a cell structure in a layout with cells of uniform height, and “H” represents a cell structure in a layout with cells of mixed height. Figure 4B As shown in the cell structure "H" in FIG, in some embodiments, the OD width within the cell is varied at the CPODE to, for example, adjust performance. In some embodiments, a nanosheet structure is used to vary the OD width at the location of the CPODE. In some embodiments, the addition of additional CPODE increases the cell area.

[0084] It should be understood that, in general, OD width can dominate cell PPA, and larger OD width can lead to higher speed / energy / leakage (e.g., speed and switching energy can increase with increasing OD width, while leakage power and speed can increase with increasing OD width).

[0085] Figure 5 is a diagram of cells in various layouts according to some embodiments.

[0086] Reference Figure 5 As an example, a layout Uca with uniform height cells is shown with four M0 tracks. In the layout UCa, all cells are shown to have the same OD width "a", ie the width of the active area along the Y axis is "a".

[0087] Figure 5 Included are a first layout HCa and a second layout HCb having cells of uniform cell height within each row but different rows having respective different active area widths (OD widths) (layout HCa), or having respective different OD widths and respective different numbers of tracks per row (layout HCb).

[0088] Figure 5 Also included is a layout 250b according to an embodiment wherein different rows have the same number of tracks per row (as an example, 4 M0 tracks per row are shown for layout 250b) but different OD widths.

[0089] It should be understood that Figure 5 The layout shown in shows various track numbers and various OD widths for descriptive purposes only, and the layout is not limited to the track numbers or OD widths shown.

[0090] In layout UCa with uniform height cells, each cell overlaps four M0 tracks, and each cell has an active area of ​​the same OD width ("a").

[0091] In a similar manner to layout UCa, layout 250b has four M0 tracks and includes cells having an OD width of "a".

[0092] In layouts HCa and HCb, some OD widths vary from row to row (OD widths "b1" and "b2" in the rows of layout HCa, and OD widths "b3" and "b4" in the rows of layout HCb). The OD width "b1" of layout HCa can be greater than the OD width "a" of layout UCa, and the OD width "b2" of layout HCa can be smaller than the OD width "a" of layout UCa. The OD width "b3" of layout HCb can be greater than the OD width "b1" of layout HCa, and the OD width "b4" of layout HCb can be smaller than the OD width "b2" of layout HCa.

[0093] In a manner similar to layouts HCa and HCb, in some embodiments, layout 250b has cells with varying OD widths. In some embodiments, layout 250b includes cells with OD width "a", as described above, and also includes cells with OD widths "b3" and "b4". Thus, in some embodiments, the cells of layout 250b have OD widths corresponding to both layout UCa and layout HCb, but layout HCb has 3 M0 tracks in the entire row of cells within OD width "b4", while layout 250b can use M0 tracks as ICPG tracks on a cell-by-cell basis, so cells with OD width "b4" in layout 250b can be adjacent to cells with more M0 tracks (e.g., four M0 tracks) and a larger OD width (e.g., "a") in the row direction.

[0094] In some embodiments, in the layout 250b, the sum of the dimensions (parallel to the Y axis) of the two OD widths "b3" and the two OD widths "b4" is equal to or less than the sum of the dimensions (parallel to the Y axis) of the four OD widths "a". Figure 2 , in some embodiments, Figure 2 The sum of the OD widths (measured parallel to the Y-axis direction) of the triple cell 1060 is equal to or less than six times the OD width "a" in layout 250b (as described above, the triple cell 1060 can have a cell height corresponding to the combined cell height of the three middle cells 1010).

[0095] Figure 6 is a diagram of an example of a front-end of line (FEOL) structure according to some embodiments.

[0096] Figure 6 is a diagram of examples of front-end-of-line (FEOL) structures for a single-height structure ("M"), a double-height structure ("S+L"), and a triple-height structure ("S+XL+S").

[0097] Reference Figure 6, the cell height is shown for a single height structure ("M"); this cell height may be referred to as a standard cell height.

[0098] In some embodiments, the standard cell height is equal to 2*(W sh,max +W space,min In some embodiments, the minimum OD space (W space,min ) can be set according to the process and can be set to the minimum OD space for all cells in the layout. In some embodiments, the minimum OD width (W sh,min ) can be the minimum width that meets the design rules or process.

[0099] If the standard cell height is fixed and the minimum OD space (W space,min ) is set by the process, it can be understood that if the following conditions are met, the OD width in the standard cell cannot be greater than (W sh,max ): Standard unit height = 2*(W sh,max +W space,min ).

[0100] In the double height structure ("S+L") and triple height structure ("S+XL+S"), the OD width distribution may change, while the minimum OD spacing remains unchanged. In some embodiments, the maximum OD width in the double height structure and / or triple height structure is greater than that in the single height structure. sh,max .For example, Figure 6 W in double height structure and / or triple height structure N3 and W P3 Greater than Figure 6 W in a single height structure sh,max In some embodiments, W N3 and W P3 The increase of W N1 and W P1 In some embodiments, Figure 6 W in double height structure and / or triple height structure N1 and W P1 Less than Figure 6 W in a single height structure sh,max .

[0101] In a triple height structure ("S+XL+S"), the XL portion may have the maximum OD width, but is limited by the four minimum OD widths of the S portion. That is, the OD width may be distributed between two S portions and one XL portion in order to maximize the OD width in the XL portion while maintaining the minimum OD width in the two S portions. That is, referring to column 2 ("S+XL+S") in the triple height structure, the sum of the OD widths (measured parallel to the Y-axis direction) of the triple height structure may be equal to or less than six times the maximum OD width of the single height structure (6 times W). sh,max In some embodiments, the N-type active region and the P-type active region have different widths, for example, N4 and W P4 The widths can be different from each other in triple height configuration ("S+XL+S").

[0102] Furthermore, the maximum sum of OD widths of the same row may be fixed. For example, referring to column 1 in a double height structure ("S+L"), the following relationship may hold true:

[0103] W N1 +W P1 +W P3 +W N3 ≤4*W sh,max

[0104] Referring to column 2 in the triple height structure ("S+XL+S"), some embodiments satisfy the following relationship:

[0105] W N2 +W P2 +W P4 +W N4 +W P6 +W N6 ≤6*W sh,max

[0106] exist Figure 6 In the embodiment, various OD widths may change (or turn) at the CPODE pattern, polysilicon (PO) pattern, or active region.

[0107] Figure 7 is a diagram of an example of a back-end of line (BEOL) structure according to some embodiments.

[0108] Figure 7 It is a diagram showing an aspect of the M0 layer in which a PG track and an M0 track are formed.

[0109] exist Figure 7In some embodiments, the number of M0 tracks in each row is the same. In some embodiments, the minimum M0 width (determined parallel to the Y axis) is determined by the process layout or design rules. In some embodiments, different M0 tracks may have different widths. In some embodiments, the minimum spacing between M0 tracks (determined parallel to the Y axis) is determined by the process layout or design rules.

[0110] exist Figure 7 In , the width of the PG track (determined parallel to the Y-axis) is denoted as PG width.

[0111] In some embodiments, Figure 7 In the structure shown, the cell height of the BEOL in row 1 satisfies the following relationship:

[0112] Unit height = total M0 width + total M0 space + PG width

[0113] In some embodiments, the above relationship also holds true for row 2.

[0114] In some embodiments, all M0 tracks have the same width and all M0 spaces have the same width, and the cell height of the BEOL satisfies the following relationship:

[0115] Unit height = n*(M0 width + M0 space) + M0 space + PG width

[0116] For the above relations, "n" represents the number of M0 orbitals.

[0117] In some embodiments, Figure 7 The uniform height unit structure ("U") shown on the left corresponds to Figure 5 The cells of the layout 250 have an OD width “a”.

[0118] In some embodiments, Figure 7 The hybrid unit structure ("H") shown on the right corresponds to Figure 5 The layout 250 has cells with OD widths “b3” and “b4”, and for this structure, one of the M0 tracks can be designated as an ICPG track.

[0119] Figure 8 is a diagram of examples of adjacent intra-cell power / ground (ICPG) tracks and examples of non-adjacent ICPG tracks, according to an embodiment.

[0120] Figure 8 Expanded Figure 7 An example showing Figure 7 The unit structures "U" and "H" have adjacent ICPG (in Figure 8ICPG_a in FIG), and a hybrid unit structure “H_2” with non-adjacent ICPG tracks (in FIG). Figure 8 denoted as ICPG_na in [1].

[0121] In some embodiments, in each of the uniform cell structure "U" and the hybrid cell structures "H" and "H_2", the PG rails are separated by the same number of tracks. That is, in some embodiments, the total number of tracks 1100 and ICPG tracks between each pair of PG rails is the same.

[0122] exist Figure 8 In the figure, dimensions A, B, C, D, E, and F describe the relationship between the FEOL and BEOL structures. In some embodiments, these relationships enable correspondence between cell heights and, for example, M0 tracks, thereby providing electrical connections from short height cells to ICPG tracks, etc. In some embodiments, dimensions A, B, C, D, E, and F satisfy the following relationship:

[0123] A=n*(M0 width+M0 space)+M0 space+PG width

[0124] A=2*(OD width+OD space)

[0125] A=B

[0126] C=(n+m)*(M0 width+M0 space)+2*M0 space+1.5*PG width

[0127] D=(nm)*(M0 width+M0 space)+0.5*PG width

[0128] E = 2*(OD width_lg + OD space)

[0129] F = 2*(OD width_sm + OD space)

[0130] A+B=C+D=E+F

[0131] C≥E

[0132] D≥F

[0133] For the above relationship, the terms "M0 width", "M0 space" and "PG width" are as follows: Figure 7 In addition, “n” represents the number of M0 tracks 1100, as shown in FIG. Figure 7 As shown; "m" represents the number of interlayer M0 tracks 1100_s, that is, the number of M0 tracks between non-adjacent ICPG (ICPG_na) and the corresponding PG track; "OD width_lg" represents the larger OD width, while "OD width_sm" represents the smaller OD width in the hybrid unit structure "H" and "H_2".

[0134] Among them, the relations C ≥ E and D ≥ F are intended to ensure that short height cells can be connected to the ICPG track.

[0135] As mentioned above, in some embodiments, PG track is a part of the power grid that provides power to device, and can be one or more tracks 1100 (that is, it can be M0 track) in M0 layer to be used as or be designated as intra-cell power / ground (ICPG) track. Various examples of connection between PG track and ICPG track are described below. However, first, further description of ICPG track according to an embodiment will be provided.

[0136] Figure 9 is a diagram of an example layout with adjacent ICPG tracks according to one embodiment.

[0137] exist Figure 9 In the example layout 300, the cell rows, PG rails, track 1100 and ICPG rails are included. In some embodiments, the rows are parallel to Figure 9 The X-axis in the Figure 9 In some embodiments, the lateral boundaries of the cells are defined by CPODE patterns. In some embodiments, the PG rails are aligned with the horizontal boundaries that run parallel to the horizontal lines between cells above / below each other in layout 300. Figure 9 The X-axis extension in .

[0138] In some embodiments, the PG rail is used to provide power or ground to the circuit formed in the cell, track 1100 is used to provide a signal to the circuit formed in the cell, and the ICPG track is used to provide power or ground to the circuit formed in the cell. In some embodiments, one or more tracks 1100 are designated as (i.e., used as) ICPG tracks.

[0139] In some embodiments, the length of the track 1100 is different from the length of the ICPG track, and the length refers to the direction in which the row extends, such as horizontally or parallel to the Figure 9 In some embodiments, the length of the ICPG track is substantially sufficient to span the entire width of the corresponding cell.

[0140] exist Figure 9 In the layout 300 of FIG. 1 , a single cell width is shown by way of example.

[0141] In some embodiments, the PG rail extends beyond the cell width. In some embodiments, the PG rail extends the entire length of a row having multiple or many cells. In some embodiments, the PG rail has a dimension, as determined parallel to the X-axis, that is at least as large as the combined lateral dimensions of two adjacent cells (as determined parallel to the X-axis). In some embodiments, the PG rail has a dimension, as determined parallel to the X-axis, that is at least as large as the combined lateral dimensions of three or more adjacent cells (as determined parallel to the X-axis).

[0142] In some embodiments, the length of the track 1100 in the cell varies according to the internal connection type of the circuit in the cell, for example, and the length of the ICPG track is substantially enough to span the entire width of the cell. In some embodiments, track 1100 and ICPG track do not extend to the adjacent cells in the lateral direction. In some embodiments, track 1100 is shorter than ICPG track, as determined horizontally or parallel to the X-axis. In some embodiments, the ICPG track has the size determined parallel to the X-axis, which is equal to the size of the corresponding cell determined parallel to the X-axis. In some embodiments, the ICPG track has the size determined parallel to the X-axis, which is less than the size of the corresponding cell determined parallel to the X-axis, but greater than the longest non-ICPG track 1100 in the cell, as determined parallel to the X-axis.

[0143] In some embodiments, the PG rail, track 1100 and ICPG track are formed in the same layer. For example, in some embodiments, the PG rail, track 1100 and ICPG track are all formed in the M0 layer.

[0144] In some embodiments, the ICPG track formed as the M0 power rail is not broken, so that the hybrid row area has a long M0 track (ICPG) on the small OD side.

[0145] Figure 10A and Figure 10B is a diagram of a first example connection structure for an ICPG track according to one embodiment.

[0146] Figure 10A 4 is a diagram of a layout 400 that includes a version of the above layout 300. The layout 400 includes a first embodiment of connecting the ICPG track to the PG track. Figure 10A , shaded cells represent hybrid rows.

[0147] In layout 400, the ICPG track corresponds to the boundary extending parallel to the X-axis direction between two cells vertically adjacent to each other. For example, layout 400 includes adjacent ICPG tracks, which correspond to the boundary in the X-axis direction between the long height cell (th) and the short height cell (sh) vertically adjacent to each other. The long height cell (th) and the short height cell (sh) are mixed row cells. In some embodiments, the ICPG track is configured to maintain a power supply voltage, which is provided to the source of the first transistor in the long height cell (th) and is provided to the source of the second transistor in the short height cell (sh).

[0148] In layout 400, PG track extends beyond cell width. In certain embodiments, PG track extends the entire length of the row with multiple or many cells. In certain embodiments, the length of the track 1100 in the cell varies according to the type of internal connection of the circuit in the cell, for example, and the length of the ICPG track is substantially enough to span the entire width of the cell. In certain embodiments, the track 1100 in the long height and short height cells (th, sh) and the ICPG track at its border do not extend into the adjacent cells in the lateral direction. In certain embodiments, as determined horizontally or parallel to the X-axis, the track 1100 in the long height and short height cells (th, sh) is shorter than the ICPG track at its border. In certain embodiments, the ICPG track at the border of the long height and short height cells (th, sh) has a size determined parallel to the X-axis, which is equal to the size determined parallel to the X-axis of the long height and short height cells (th, sh). In some embodiments, the ICPG track at the boundary of the long height and short height cells (th, sh) has a dimension as determined parallel to the X-axis that is smaller than the dimension of the long height and short height cells (th, sh) as determined parallel to the X-axis, but larger than the longest non-ICPG track 1100 in either of the long height and short height cells (th, sh), as determined parallel to the X-axis.

[0149] exist Figure 10A In the example, connection 1400 is used to form an electrical connection between the ICPG rail and the PG rail. Figure 10A , multiple connections 1400 are shown. In some embodiments, one or more connections 1400 are provided for each ICPG track.

[0150] For example, layout 400 also shows a cell having two ICPG tracks (denoted as ICPGa and ICPGb for clarity) and two tracks 1100. In some embodiments, the connection of ICPG track ICPGb also results in the connection of the sandwiched ICPG track ICPGa by way of connection 1400. That is, in some embodiments, connection 1400 connects both ICPG tracks ICPGa and ICPGb to the PG rail.

[0151] Figure 10B is a diagram of an example connection 1400 according to one embodiment.

[0152] In some embodiments, connection 1400 is an extension or slot-like form of a connection that connects a metallization layer (e.g., a diffusion-above metal (MD) layer) to the PG rail, the extension also connecting track 1100 (i.e., ICPG) to the PG rail. In some embodiments, the extension has a longitudinal dimension extending in a direction parallel to the Y-axis. In some embodiments, connection 1400 is a slot-like extension of a diffusion-above via (VD) layer connection (e.g., a VD2 connection) between the MD layer and the PG rail. In some embodiments, the VD2 layer is a layer between the OD (active area) and the M0 layer. In some embodiments, the VD2 layer includes a connection that connects the OD to the PG rail.

[0153] In some embodiments, the MD layer has conductive elements extending parallel to the Y-axis direction. Figure 10B In FIG, the MD layer is shown with conductive elements MD1, MD2, MD3, MD4, MD5, and MD6. In some embodiments, connection 1400 is a slot VD2 connection that extends along the conductive elements in the MD layer to connect the PG rail in M0 to the ICPG rail in M0. As an example, Figure 10B It is shown that groove VD2 set along MD3 connects and connects the ICPG track in M0 to the PG rail in M0.

[0154] exist Figure 10A and Figure 10B In some embodiments, the VD2 connection is used to connect the MD and PG rails (M0_PG), and the groove VD2 extending above the MD facilitates connection to the ICPG track (intra-unit M0_PG connection).

[0155] In addition to the above, in some embodiments, the connection of the ICPG track ICPGb connected by the slot VD2 also results in the connection of the ICPG track ICPGa sandwiched. Therefore, it is possible to retain the use of the slot VD2 connection to connect non-adjacent PG rails (e.g., ICPGb) when the overall M0 wiring resources are sufficient for large units.

[0156] Figure 10C and Figure 10D FIG. 1 is a diagram illustrating a connection state of the slot VD2 according to an embodiment.

[0157] exist Figure 10C In the VD2 slot, the connection is used to connect the adjacent ICPG track to the PG track in M0. Figure 10C In (a), the trench VD2 connection is located above the MD, and in (b), the trench VD2 connection is located above the polysilicon.

[0158] Referring to (a), MD covers the epitaxial layer to provide lower resistance. MD is connected to the epitaxial layer, and VD2 is connected to the PG rail.

[0159] In the structure shown in (a), when slot VD2 is implemented, it may be too close to the MD of another cell, which may lead to time-dependent dielectric breakdown (TDDB) issues. For example, if VD2 is a power signal and the opposite MD is an internal signal of another cell, there may be a voltage difference, which may cause leakage or dielectric breakdown.

[0160] To help avoid this leakage or dielectric breakdown, refer to Figure 10C In (b), VD2 can be changed to be on the polysilicon or gate region. By moving the trench VD2 connection to the polysilicon, the TDDB problem can be reduced or eliminated.

[0161] When the slot VD2 is on the polysilicon, the power signal should be isolated from the polysilicon signal. Figure 10C In (b), the structure shown includes a protective cap (helmet) that isolates the polysilicon. In some embodiments, a protective cap is used on the polysilicon, regardless of whether trench VD2 is used. In some embodiments, the protective cap is nitride. In (b), VG is connected to a signal rail (e.g., as a via to the gate).

[0162] Reference Figure 10D In some embodiments, the slot VD2 connection is formed to satisfy the following relationship:

[0163] The ratio of M0_W / M0_S is in the range of about 0.8 to about 1.2

[0164] The ratio of PG_W / M0_W is in the range of about 1 to about 1.25

[0165] slotVD2_W>0.5*PG_W+m*(M0_S+M0_W)+M0_S+0.5*M0_W

[0166] The ratio of slotVD2_W / VD2_W is in the range of about 2 to about 5

[0167] Helmet_W>0.5*(OD_S+OD_W)

[0168] For the above relationship, M0_W is the width of M0 determined parallel to the Y axis; M0_S is the width of the M0 space (the space between adjacent M0 tracks) determined parallel to the Y axis; PG_W is the width of the PG track determined parallel to the Y axis; slotVD2_W is the width in the slot VD2 connection determined parallel to the Y axis; VD2_W is the width of the VD2 connection determined parallel to the Y axis; Helmet_W is the width of the protective cover determined parallel to the Y axis; OD_S is the width of the space between adjacent active areas (OD areas) determined parallel to the Y axis; OD_W is the width of the active area (OD area) determined parallel to the Y axis; "m" represents the number of sandwiched M0 tracks 1100_s, that is, the number of M0 tracks between non-adjacent ICPG (ICPG_na) and the corresponding PG rails.

[0169] Figure 11A and Figure 11B is a diagram of a second example connection structure according to an embodiment.

[0170] Figure 11A is a diagram of a layout 500A according to an embodiment. The layout 500A includes a second implementation where the ICPG rail is connected to the PG rail.

[0171] exist Figure 11A In the example, slot connection 1500a is used to form an electrical connection between the ICPG rail and the PG rail. Figure 11A In, multiple slot connections 1500a are provided. In certain embodiments, a slot connection 1500a or more than one slot connection 1500a is provided for each ICPG track.

[0172] In some embodiments, slot connection 1500a is an extension of the VIA0 connection between the ICPG track in M0 and the PG track in M0, that is, the VIA0 connection is extended into a slot. In some embodiments, the VIA0 layer is located between the M0 layer and the M1 layer, and the M1 layer is disposed above the M0 layer. In some embodiments, the conductive elements in the M1 layer extend in a direction generally orthogonal to the extension direction of the conductive elements in the M0 layer.

[0173] In some embodiments, the slot connection 1500a is aligned with a power delivery network (PDN) island. In some embodiments, the PDN island is located in the M1 layer. In some embodiments, multiple PDN islands are provided. In some embodiments, the PDN islands are spaced apart by a distance. Figure 11A In some embodiments, the PDN spacing is uniform in the layout, so that PDN islands appear at regular intervals.

[0174] In some embodiments, the trench connection 1500a has a longitudinal direction parallel to the Y-axis direction and parallel to the extension direction of the PDN island.

[0175] Although layout 500A is shown as including slot connections 1500a, in other embodiments discrete connections 1500b are implemented, also as shown in layout 500A.

[0176] Figure 11B is a diagram of a layout 500B according to an embodiment. Layout 500B includes another example of a second implementation of an ICPG track connected to a PG rail.

[0177] exist Figure 11B In FIG. 1 , multiple discrete connections 1500b are implemented to connect non-adjacent ICPG rails to the PG rail, such that the sandwiched rail (ie, rail 1100) is not connected to the PG rail.

[0178] Figure 11C and Figure 11D FIG. 1 is a diagram illustrating a connection state of a slot VIA0 according to an embodiment.

[0179] exist Figure 11C In the example, (a) includes a slotted VIA0 connection and (b) includes a discrete VD2 connection.

[0180] Reference Figures 11A-11C In some embodiments, the connection in the VIA0 layer is used to connect M0_PG and M1_PG (ie, the M1 layer PG conductive element), and the trench VIA0 is extended to facilitate ICPG connection.

[0181] In some embodiments, VIA0 connections are formed to correspond to the M1 layer. To avoid conflicts with cell pins, in some embodiments, VIA0 connections are only placed where PDN (power delivery network) islands are present. In some embodiments, PDN islands are located at fixed intervals (spacing), and corresponding VIA0 connections are placed accordingly.

[0182] In addition, refer to Figure 11C In structure (b), in some embodiments, the VIA0 connection used for pickup is also used to connect the PG rail to a non-adjacent ICPG rail.

[0183] Reference Figure 11D In some embodiments, the slot VIA0 connection is formed to satisfy the following relationship:

[0184] The ratio of M0_W / M0_S is in the range of about 0.8 to about 1.2

[0185] The ratio of PG_W / M0_W is in the range of about 1 to about 2.5

[0186] slotV0_W>0.5*PG_W+M0_S+0.5*M0_W

[0187] The ratio of slotV0_W / V0_W is in the range of about 2 to about 5

[0188] For the above relationship, M0_W is the width of M0 determined parallel to the Y axis; M0_S is the width of the M0 space (the space between adjacent M0 tracks) determined parallel to the Y axis; PG_W is the width of the PG rail determined parallel to the Y axis; slotV0_W is the width in the slot VIA0 connection determined parallel to the Y axis; V0_W is the width of the VIA0 connection determined parallel to the Y axis.

[0189] Figure 12A and Figure 12B is a diagram of a third exemplary connection structure according to an embodiment.

[0190] Figure 12A is a diagram of a layout 600A according to an embodiment. Layout 600A includes a third implementation where the ICPG rail is connected to the PG rail.

[0191] exist Figure 12A In FIG. 6 , the layout 600A has a filler cell 1600, which is indicated by a dotted line. In some embodiments, the filler cell 1600 is located at the junction of the rows of cells with different heights. For example, referring to FIG. Figure 1 and Figure 12A In some embodiments, the filling unit 1600 is located in the middle unit 1010 (see Figure 1 The first row at the junction between the middle unit 1010 in the upper part of the middle unit 1010) and the large unit 1030, and is located in the middle unit 1010 (see Figure 1 The second row is at the junction between the middle cell 1010 in the lower middle portion and the small cell 1020. In some embodiments, one of the filling cells 1600 is provided at each junction of the uniform height cell and the mixed height cell.

[0192] Filler cells 1600 may have double the cell height. For example, in some embodiments, the dimension of a filler cell (as measured parallel to the Y-axis) is twice the height of the middle cell 1010.

[0193] In some embodiments, the width of the filling unit 1600 (eg, measured parallel to the X-axis) is determined by the device manufacturing process or process node.

[0194] exist Figure 12A In some embodiments, the ICPG rail is connected to the PG rail using the VD2 connection in filler cell 1600. In some embodiments, the ICPG rail is connected to the PG rail at its opposite end.

[0195] In some embodiments, the VD2 connection for the long height cell (th) and the short height cell (sh) (mixed row cell) is located in the fill cell 1600 of the laterally adjacent long height cell (th) and short height cell (sh).

[0196] In some embodiments, layout 600A is used with a cell grouping approach, where long cells and short cells are placed in adjacent rows with an x-padding constraint, or padding cells with a width as determined parallel to the x-axis.

[0197] Figure 12B is a diagram of a layout 600B according to an embodiment. Layout 600B includes another example of a third implementation of an ICPG track connected to a PG rail.

[0198] exist Figure 12B In FIG, filler unit 1600 is used to form a connection to connect non-adjacent or sandwiched ICPG tracks (ICPG_na) to the PG rail.

[0199] In some embodiments, layout 600B is used with a cell grouping method.

[0200] Figure 12C FIG. 1 is a diagram illustrating a connection state of a filling unit according to an embodiment.

[0201] exist Figure 12C In structures (a) and (b), a padding cell is provided at each junction of the uniform height cell ("U") and the mixed height cell ("H"). In some embodiments, the padding cell is used to connect the M0_PG to the M0_PG within the cell (i.e., to the ICPG track) using the VD2 connection. Figure 12C In the structure (b), the filling unit designed to be picked up is used to connect the PG track with a non-adjacent ICPG track (i.e., with ICPG_na).

[0202] Figure 13A and Figure 13B is a diagram of a fourth exemplary connection structure according to an embodiment.

[0203] Figure 13A is a diagram of a layout 700A according to an embodiment. Layout 700A includes a fourth implementation where an ICPG rail is connected to a PG rail.

[0204] exist Figure 13ALayout 700A includes filler cells 1600. In some embodiments, filler cells 1600 have double the cell height. For example, in some embodiments, the size of the filler cells (as measured parallel to the Y-axis) is twice the height of the middle cell 1010. In some embodiments, the width of filler cells 1600 (as measured parallel to the X-axis) is determined by the device manufacturing process or process node.

[0205] As above combination Figures 12A-12B As discussed, in some embodiments, the filler cells 1600 are located at the junctions of cells having different heights in the row direction. In some embodiments, a filler cell is provided at each junction of uniform height cells and mixed height cells.

[0206] In some embodiments, the filler cell is used to connect the M0_PG to the intra-cell M0_PG (ie, to the ICPG track). Figure 13A In some embodiments, the ICPG track and the PG track are formed as an integral conductive element, such as in the M0 layer. In other words, in some embodiments, the ICPG track and the PG track are sewn together in the M0 layer. In some embodiments, the ICPG track and the PG track are sewn together along the entire length of the ICPG track, such as Figure 13A As shown by the dotted arrow.

[0207] In some embodiments, the change in the height of the integrated ICPG track-PG rail (as determined parallel to the Y-axis) is performed at the filling cell 1600. In some embodiments, the filling cell 1600 is located at the junction of cells with different heights, and the change in the height of the integrated ICPG track-PG rail occurs in the filling cell 1600. In some embodiments, the change in the height of the integrated ICPG track-PG rail (as determined parallel to the Y-axis) occurs in a filling cell laterally adjacent to a long height cell (th) and a short height cell (sh).

[0208] In some embodiments, layout 700A is used with a cell grouping method.

[0209] Figure 13B is a diagram of a layout 700B according to an embodiment. Layout 700B includes another example of a fourth implementation of an ICPG track connected to a PG rail.

[0210] Figure 13B FIG is a diagram of a layout 700B having a filler cell 1600. Figures 12A-12B As shown, in some embodiments, the filling cell 1600 is located at the junction of cells having different heights in the row direction.

[0211] exist Figure 13BIn some embodiments, non-adjacent ICPG tracks and PG tracks are formed as an integral conductive element, such as in the M0 layer. In some embodiments, this also connects the sandwiched track 1100, such as Figure 13B Thus, in some embodiments, the two ICPG tracks and the PG track can be stitched together as an integrated conductive element in the M0 layer.

[0212] Moreover, as mentioned above, Figure 13A As discussed, in some embodiments, the change in the height of the two ICPG tracks-PG rails of one body is performed at the filling unit 1600. In some embodiments, the filling unit 1600 is located at the junction of cells with different heights, and the change in the height of the two ICPG tracks-PG rails of one body occurs in the filling unit 1600.

[0213] In some embodiments, layout 700B is used with a cell grouping method.

[0214] Figure 13C and Figure 13D FIG. 1 is a diagram illustrating a connection state of filling units having an integral structure according to an embodiment.

[0215] Reference Figure 13C In the structure (a) and (b), in some embodiments, a filling unit (Padding) is provided at each junction of a uniform height unit ("U") and a mixed height unit ("H"). In some embodiments, the change of the height (as determined parallel to the Y axis) of the integrated ICPG track-PG rail is carried out at the filling unit 1600.

[0216] Reference Figure 13C In structure (b), in some embodiments, the connection between non-adjacent ICPG tracks ICPG_na and PG tracks also results in the connection of sandwiched ICPG tracks ICPG through an integrated conductive element in the M0 layer. Therefore, it is possible to retain the use of an integrated conductive element in the M0 layer to connect non-adjacent PG tracks (e.g., ICPG_na) when the overall M0 wiring resources are sufficient for large units.

[0217] Reference Figure 13D In some embodiments, the integrated PG rail / ICPG is formed to satisfy the following relationship:

[0218] The ratio of M0_W / M0_S is in the range of about 0.8 to about 1.2

[0219] The ratio of PG_W / M0_W is in the range of about 1 to about 2.5

[0220] PG_jog_W <PG_W+(m+1)*(M0_S+M0_W)

[0221] The ratio of PG_jog_S / M0_S is greater than or equal to 1

[0222] For the above relationship, M0_W is the width of M0 determined parallel to the Y axis; M0_S is the width of the M0 space (the space between adjacent M0 tracks) determined parallel to the Y axis; PG_W is the width of the (unextended) PG track, as determined parallel to the Y axis; PG_jog_W is the width of the extended PG track, that is, the integrated PG track / ICPG structure, as determined parallel to the Y axis; "m" represents the number of sandwiched M0 tracks 1100_s, that is, the number of M0 tracks between non-adjacent ICPGs (ICPG_na) and the corresponding PG track.

[0223] Figure 14 is a diagram of stages in a manufacturing process according to an embodiment.

[0224] exist Figure 14 In the M0 layer manufacturing process, the ICPG track and the PG track are formed into an integrated conductive element, for example in the M0 layer. Figure 14 In the figure, (a) is a diagram of the M0 layer manufacturing process, and (b) is a diagram of a wide PG rail, ie, an integrated PG rail / ICPG structure, formed by a modified M0 layer manufacturing process according to an embodiment.

[0225] Reference Figure 14 In (a), in some embodiments, the M0 layer fabrication process includes film deposition and patterning operations, followed by spacer formation operations, hard mask etching operations, metal deposition, and chemical mechanical polishing (CMP) operations.

[0226] In some embodiments, the film deposition and patterning operations include forming a film stack. In some embodiments, the film stack includes an interlayer dielectric film (ILD), which is sequentially stacked, a low-k dielectric film (LK), a first tetraethoxysilane layer (TEOS), a hard mask layer (HM), a second tetraethoxysilane layer (TEOS), an amorphous silicon layer (A-Si), a bottom anti-reflective coating layer (BARC), and a photoresist layer (PR). In some embodiments, the photoresist layer is patterned, and in a spacer formation operation, the photoresist pattern is used to form a spacer pattern in a first etching process, wherein the second TEOS layer and the hard mask layer are patterned. In some embodiments, the remaining photoresist pattern, BARC layer, and A-Si layer are then removed. In some embodiments, the spacer pattern includes patterns in the second TEOS and the hard mask layer. In some embodiments, a hard mask etching operation forms a pattern in the first TEOS and the low-k dielectric layer. In some embodiments, any remaining amorphous silicon, hard mask, and first TEOS layer are then removed. In some embodiments, the metal deposition and CMP operations include depositing one or more metal layers over the pattern in the first TEOS and the pattern in the low-k dielectric layer, and chemically mechanically polishing the resulting structure until the topmost surface of the low-k dielectric layer and the topmost surface of the resulting metal structure (in some embodiments, this is the M0 layer) are exposed. In some embodiments, depositing one or more metal layers over the pattern in the first TEOS and the low-k dielectric layer includes depositing a barrier layer and depositing the metal layer over the barrier layer. In some embodiments, the barrier layer helps prevent metal from diffusing from the metal layer. In some embodiments, the barrier layer is one or more of TaN or TiN, or includes one or more of TaN or TiN. In some embodiments, the metal layer deposited over the barrier layer is one or more of Cu or Co, or includes one or more of Cu or Co.

[0227] Reference Figure 14 (b) in the embodiment, the modified M0 layer manufacturing process includes film deposition and patterning operations, followed by spacer formation operations, as described above in combination with Figure 14 Then, before performing the above-mentioned hard mask etching operation and metal deposition and chemical mechanical polishing (CMP) operations, a spacer cutting operation is performed in some embodiments. That is, in some embodiments, the modified M0 layer manufacturing process includes film deposition and patterning operations, followed by spacer formation operations, spacer cutting operations, hard mask etching operations, and metal deposition and chemical mechanical polishing (CMP) operations.

[0228] In a modified M0 layer fabrication process according to an embodiment, the film deposition and patterning operations include the formation of a film stack, and the spacer formation operations include the formation of a spacer pattern, as described above in conjunction with Figure 14As described in (a) above.

[0229] In some embodiments, during a spacer cutting operation, a layer to be patterned is deposited over the spacer structure, and a portion of the layer to be patterned is removed, for example, by forming a second photoresist layer over the layer to be patterned, patterning the second photoresist layer to form a second photoresist pattern, and etching the layer to be patterned using the second photoresist layer to form a layer pattern of spacers that exposes the spacer pattern. In some embodiments, the exposed spacers are then removed, for example, by an etching process, while the remaining spacers of the spacer pattern remain covered and protected by the layer pattern.

[0230] Then, in some embodiments, the above combination Figure 14 The hard mask etch and metal deposition and CMP operations are performed in the manner discussed in (a).

[0231] As a result of removing the exposed spacers, in some embodiments, the metal deposition and CMP operations produce a structure in which wide conductive elements, ie, wide PG rails, are formed in the M0 layer.

[0232] Figure 15 FIG. 1 is a diagram illustrating a layout according to an embodiment of the present invention.

[0233] Reference Figure 15 (and refer to Figure 8 ), designing a layout according to one embodiment includes an operation (a) of determining a cell height "A". In some embodiments, the determination of the cell height "A" takes into account the width of the M0 track (M0_width), the width of the M0 space (M0_space), the width of the PG track (PG_width), the number of M0 tracks (n), the OD width (OD_width), and the width of the OD space (OD_space).

[0234] In some embodiments, the cell height, i.e., dimension "A," satisfies the following relationship:

[0235] A=n*(M0 width+M0 space)+M0 space+PG width

[0236] A=2*(OD width+OD space)

[0237] In some embodiments, designing the layout further includes operation (b) of determining a maximum OD width, determining a minimum OD width, and determining a cell height of a hybrid cell structure after determining the cell height “A”.

[0238] In some embodiments, the values ​​determined for the maximum OD width, the minimum OD width, and the cell height of the hybrid cell structure are evaluated (the cell height of the hybrid cell structure is in the range of Figure 8 Indicated by dimensions E and F). For example, refer to Figure 8 In some embodiments, dimension "B" is set equal to "A", and the check is as above Figure 8 Dimensions "A", "B", "C", "D", "E", and "F" in (operation (C)) are determined to determine whether they satisfy the following relationship:

[0239] A=n*(M0 width+M0 space)+M0 space+PG width

[0240] A=2*(OD width+OD space)

[0241] C=(n+m)*(M0 width+M0 space)+2*M0 space+1.5*PG width

[0242] D=(nm)*(M0 width+M0 space)+0.5*PG width

[0243] E=2*(OD width_lg+OD space)

[0244] F=2*(OD width_sm+OD space)

[0245] A+B=C+D=E+F

[0246] C≥E

[0247] D≥F

[0248] For the above relationship, the terms "M0 width", "M0 space" and "PG width" are as follows: Figure 7 In addition, “n” represents the number of M0 tracks 1100, as shown in FIG. Figure 7 As shown; "m" represents the number of sandwiched M0 tracks 1100_s, that is, the number of M0 tracks between non-adjacent ICPG (ICPG_na) and the corresponding PG track; OD width_lg represents the larger OD width, and OD width_sm represents the smaller OD width in the hybrid unit structure "H" and "H_2".

[0249] If the above relationship of "A" to "F" is not satisfied, in some embodiments, one or more values ​​in the layout design are modified, for example, by modifying one or more parameters of the maximum OD width, the minimum OD width, and the cell height of the hybrid cell structure, and then re-evaluating the dimensions "A" to "F" (operation (c)) to determine whether they satisfy the above relationship.

[0250] In some embodiments, the design layout further includes, after dimensions "A" to "F" pass the evaluation in operation (c), checking operation (d) to see if the cell ( Figure 8 Whether the M0 wiring resources (n-1-m) of F) are sufficient (as mentioned above, "n" represents the number of M0 tracks and "m" represents the number of sandwiched M0 tracks).

[0251] In some embodiments, if the wiring resources of the small cell M0 are found to be insufficient, the layout design is modified, for example, by modifying one or more parameters of the maximum OD width, the minimum OD width, and the cell height of the hybrid cell structure, and re-evaluated.

[0252] In some embodiments, the design layout further includes, after finding that the cell M0 routing resources are sufficient, determining which M0 tracks will be designated as ICPG tracks, including designating the M0 tracks as adjacent (operation (e); see also Figure 8 ICPG_a) or non-adjacent (operation (f); see also Figure 8 of ICPG_na).

[0253] In some embodiments, the design layout further includes, for adjacent ICPG tracks (e.g., Figure 8 ICPG_a), select a connection structure to provide power / ground to the adjacent ICPG track, for example, to connect the adjacent ICPG track to the PG rail. In some embodiments, the connection structure is, for example, a slot VD2 connection structure, a slot VIA0 connection structure, a fill pick connection structure, or an M0 stitch connection structure. In some embodiments, other wiring structures may also be used. Figures 10A-10D An example of the groove VD2 connection structure is described. Figures 11A-11D An example of the slot VIA0 connection structure is described. Figures 12A-12C An example of a fill pick-up connection structure is described. Figures 13A-13D and Figure 8 An example of an M0 suture connection structure is described.

[0254] In some embodiments, the design layout further includes, for non-adjacent ICPG tracks (e.g., Figure 8 ICPG_na), select a connection structure to provide power / ground to non-adjacent ICPG tracks, for example, connecting non-adjacent ICPG tracks to PG rails.

[0255] In some embodiments, for the case where non-adjacent ICPG tracks are implemented and large cell M0 routing resources are considered sufficient (see Figure 15In (g)), the connection structure is, for example, a slot VD2 connection structure, a slot VIA0 connection structure, a fill pick connection structure, or an M0 stitch connection structure. In some embodiments, other wiring structures may also be used.

[0256] In some embodiments, for cases where non-adjacent ICPG tracks are implemented and it is believed that large cell M0 routing resources may be insufficient (see Figure 15 In (h)), the connection structure is, for example, a slot VIA0 connection structure or a fill pick-up connection structure. In some embodiments, other wiring structures may also be used.

[0257] Figure 16 is a block diagram of an electronic process control (EPC) system according to one embodiment.

[0258] Figure 16 2 is a block diagram of an electronic process control (EPC) system 2000 according to one embodiment. In some embodiments, the EPC system 2000 is used to implement the methods described herein for generating cell layouts according to one or more embodiments. In some embodiments, the EPC system 2000 is a general-purpose computing device, for example, including a hardware processor 2002 and a non-transitory, computer-readable storage medium 2004. In some embodiments, the computer-readable storage medium 2004 is encoded with (i.e., stores) computer program code (or instructions) 2006 (i.e., an executable instruction set), among other things. In some embodiments, the computer program code 2006 is executed by the processor 2002 to (at least partially) implement at least a portion of the EDA tools described herein according to one or more embodiments to implement a portion or all of the methods (hereinafter referred to as the proposed processes and / or methods).

[0259] In some embodiments, processor 2002 is electrically coupled to computer-readable storage medium 2004 via bus 2018. In some embodiments, processor 2002 is also electrically coupled to I / O interface 2012 via bus 2018. In some embodiments, network interface 2014 is further electrically coupled to processor 2002 via bus 2018. In some embodiments, network interface 2014 is connected to network 2016, enabling processor 2002 and computer-readable storage medium 2004 to connect to external components via network 2016. In some embodiments, processor 2002 is configured to execute computer program code 2006 encoded in computer-readable storage medium 2004 to enable EPC system 2000 to perform part or all of the proposed processes and / or methods. In some embodiments, processor 2002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0260] In some embodiments, the computer-readable storage medium 2004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 2004 includes semiconductor memory or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 2004 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disk (DVD).

[0261] In some embodiments, the computer-readable storage medium 2004 stores computer program code 2006 configured to enable the EPC system 2000 (where such execution (at least in part) represents an EPC tool) to perform some or all of the processes and / or methods described herein. In some embodiments, the computer-readable storage medium 2004 further stores information that facilitates the performance of some or all of the processes and / or methods described herein. In some embodiments, the computer-readable storage medium 2004 stores processor control data 2008, including, for example, control algorithms for enabling statistical process control (SPC) and / or model predictive control (MPC) based on various process controls, active cell data, transition cell data, uniformity algorithms, layout data, constants, target ranges, set points, and program code.

[0262] In some embodiments, EPC system 2000 includes an I / O interface 2012. In some embodiments, I / O interface 2012 is coupled to external circuitry. In some embodiments, I / O interface 2012 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor keys for communicating information and commands to processor 2002.

[0263] In some embodiments, in EPC system 2000, a network interface 2014 is coupled to processor 2002. In some embodiments, network interface 2014 enables EPC system 2000 to communicate with a network 2016 connected to one or more other computer systems. In some embodiments, network interface 2014 includes a wireless network interface, such as Bluetooth, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet, universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In some embodiments, part or all of the proposed process and / or method is implemented in two or more EPC systems 2000.

[0264] In some embodiments, the EPC system 2000 is configured to receive information via the I / O interface 2012. In some embodiments, the information received via the I / O interface 2012 includes one or more of instructions, data, design rules, process performance history, target ranges, set points, and / or other parameters for processing by the processor 2002. In some embodiments, the information is communicated to the processor 2002 via the bus 2018. In some embodiments, the EPC system 2000 is configured to receive information related to a user interface (UI) via the I / O interface 2012. In some embodiments, the information is stored in the computer-readable storage medium 2004 as the UI 2010.

[0265] In some embodiments, some or all of the proposed processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the proposed processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, some or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented as a software application that is part of an EPC tool. In some embodiments, some or all of the proposed processes and / or methods are implemented as a software application used by the EPC system 2000.

[0266] In some embodiments, the processes and / or methods are implemented in the functional form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and the like.

[0267] Figure 17 is a block diagram of an IC manufacturing system according to one embodiment.

[0268] Figure 17 1 is a block diagram of an integrated circuit (IC) manufacturing system 2100 and an IC manufacturing process related thereto according to some embodiments. Based on a layout diagram according to one embodiment, the IC manufacturing system 2100 according to one embodiment is used to manufacture components in a layer of a semiconductor mask and / or a semiconductor integrated circuit. In some embodiments, the IC manufacturing process is implemented, for example, according to the above combination. Figure 15 Aspects of designing a layout according to an embodiment are discussed in detail.

[0269] In some embodiments, IC manufacturing system 2100 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 2160, such as a design studio (design team) 2120, a mask room 2130, and an IC manufacturing plant / fab ("fab") 2150. In some embodiments, the entities in IC manufacturing system 2100 are connected via a communication network. In some embodiments, the communication network is a single network or a variety of different networks, such as an intranet and the Internet. In some embodiments, the communication network includes wired and / or wireless communication channels. In some embodiments, each entity interacts with one or more of the other entities and provides services to and / or receives services from one or more of the other entities. In some embodiments, a single, larger company owns two or more of design studio 2120, mask room 2130, and IC fabrication plant 2150. In some embodiments, two or more of the design room 2120, the mask room 2130, and the IC fabrication facility 2150 are co-located in a common facility and utilize common resources.

[0270] In some embodiments, the design office 2120 generates an IC design layout 2122. In some embodiments, the IC design layout 2122 includes various geometric patterns designed for the IC device 2160. In some embodiments, the geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various components of the IC device 2160 to be fabricated. In some embodiments, the various layers are combined to form various IC features. For example, in some embodiments, a portion of the IC design layout 2122 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) (e.g., openings for active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and bond pads), as well as various material layers disposed on the semiconductor substrate. In some embodiments, the design office 2120 implements an appropriate design process to generate the IC design layout 2122. In some embodiments, the design process includes one or more of logical design, physical design, or placement and routing. In some embodiments, the IC design layout 2122 is presented in the form of one or more data files containing information on the geometric patterns. For example, in some embodiments, IC design layout 2122 is expressed in a GDSII file format or a DFII file format.

[0271] In some embodiments, mask chamber 2130 includes operations for mask data preparation 2132 and mask fabrication 2144. In some embodiments, mask chamber 2130 uses IC design layout 2122 to create one or more masks based on IC design layout 2122 for fabricating various layers of IC device 2160. In some embodiments, mask chamber 2130 performs mask data preparation 2132, translating IC design layout 2122 into a representative data file (RDF). In some embodiments, mask data preparation 2132 supplies the RDF to mask fabrication 2144. In some embodiments, mask fabrication 2144 includes a mask writer. In some embodiments, the mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) or semiconductor wafer). In some embodiments, mask data preparation 2132 manipulates IC design layout 2122 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication facility 2150. Although mask data preparation 2132 and mask fabrication 2144 are shown as separate elements, in some embodiments, mask data preparation 2132 and mask fabrication 2144 may be collectively referred to as mask data preparation.

[0272] In some embodiments, mask data preparation 2132 includes optical proximity correction (OPC), which utilizes lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, crosstalk, other process effects, and the like). In some embodiments, OPC adjusts the IC design layout 2122. In some embodiments, mask data preparation 2132 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution adjustment features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography (ILT) is utilized, which treats OPC as an inverse imaging problem.

[0273] In some embodiments, mask data preparation 2132 includes a mask rule checker (MRC) that checks the IC design layout 2122, which has undergone the OPC process, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure that sufficient margins are in place to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 2122 to compensate for the constraints imposed during mask fabrication 2144, which may undo some of the modifications implemented by OPC to satisfy the mask creation rules.

[0274] In some embodiments, mask data preparation 2132 includes lithography process checking (LPC), which simulates the processes to be performed by IC fabrication facility 2150 to fabricate IC device 2160. In some embodiments, LPC simulates this process based on IC design layout 2122 to fabricate a simulated finished device, such as IC device 2160. In some embodiments, process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. In some embodiments, LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated finished device has been fabricated using LPC, if the simulated device's shape is not sufficiently similar to meet design rules, OPC and / or MRC are repeated to further refine IC design layout 2122.

[0275] For clarity, the above description of mask data preparation 2132 has been simplified. It should be understood that mask data preparation 2132 may include additional features, such as modifying logic operations (LOPs) of IC design layout 2122 according to manufacturing rules. In addition, the processes applied to IC design layout 2122 during mask data preparation 2132 may be performed in a variety of different orders.

[0276] In some embodiments, after and during mask data preparation 2132, a mask or group of masks is fabricated based on the modified IC design layout 2122. In some embodiments, mask fabrication 2144 includes performing one or more photolithographic exposures based on the IC design layout 2122. In some embodiments, an electron beam (e-beam) or a mechanism comprising multiple electron beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout 2122. In some embodiments, the mask is formed using various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. In some embodiments, a radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) applied to a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, the mask is formed using phase shift technology. In some embodiments, in a phase shift mask (PSM), various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In some embodiments, the phase shift mask is an attenuated PSM or an alternating PSM. In some embodiments, the mask produced by mask fabrication 2134 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 2153, in an etching process to form various etched regions in the semiconductor wafer 2153, and / or in other suitable processes.

[0277] In some embodiments, IC fabrication facility 2150 performs wafer fabrication 2152. In some embodiments, IC fabrication facility 2150 is a semiconductor foundry. In some embodiments, IC fabrication facility 2150 comprises an IC fabrication enterprise comprising one or more fabrication facilities for fabricating a variety of different IC products. For example, in some embodiments, IC fabrication facility 2150 comprises one or more fabrication facilities for front-end fabrication (front-end-of-line (FEOL)) of multiple IC products, one fabrication facility for back-end fabrication (back-end-of-line (BEOL)) of interconnects and packaging for IC products, and one fabrication facility for other services.

[0278] In some embodiments, a device includes: first, second and third power / ground (PG) conductive elements extending along a first direction; a first group of at least three conductive tracks are located between the first PG conductive element and the second PG conductive element, and a second group of at least three conductive tracks are located between the second PG conductive element and the third PG conductive element, and the conductive tracks are arranged in equal numbers between the first PG conductive element and the second PG conductive element and between the second PG conductive element and the third PG conductive element; a first row of cells is arranged in the first direction and overlaps with the first group of at least three conductive tracks; and a second row of cells is arranged in the first direction and overlaps with the second group of at least three conductive tracks. In some embodiments, in a first row of cells, the first cell has a first height in a second direction orthogonal to the first direction; in the first row of cells, the second cell has a height greater than the first height; in a second row of cells, the third cell shares a boundary extending in the first direction with the first cell and has the first height; in the second row of cells, the fourth cell shares a boundary extending in the first direction with the second cell and has a height less than the first height; the combined height of the second and fourth cells corresponds to the combined height of the first and third cells; and between the second and third PG conductive elements, the conductive track is aligned with the boundary extending in the first direction of the second and fourth cells and is configured as an intra-cell PG track. In some embodiments, the first and second rows of cells each have at least one active region formed in the substrate, the at least one active region extending along the first direction, and the conductive track is located in the lowest conductive material layer above the substrate. In some embodiments, all conductive tracks have the same dimensions in the second direction. In some embodiments, the first cell has a first active region extending along a first direction, the second cell has a second active region extending along the first direction, a first isolation pattern isolates the second active region from the first active region, and the first isolation pattern extends along the second direction; the third cell has a third active region extending along the first direction, the fourth cell has a fourth active region extending along the first direction, a second isolation pattern isolates the third active region, and the second isolation pattern extends along the second direction. In some embodiments, the second isolation pattern is aligned with the first isolation pattern. In some embodiments, the first isolation pattern and the second isolation pattern are each continuous polysilicon on oxide defined edge (CPODE) patterns. In some embodiments, the first cell has a first active region extending along the first direction, the second cell has a second active region extending along the first direction, and the first active region has a smaller dimension in the second direction than the second active region; the third cell has a third active region extending along the first direction, the fourth cell has a fourth active region extending along the first direction, and the third active region has a larger dimension in the second direction than the fourth active region. In some embodiments, the second PG conductive element is aligned with the boundary between the first and third cells extending in the second direction.In some embodiments, the intra-cell PG rail is electrically connected to the second PG conductive element via a connection of the third cell or a connection between the second cell and the third cell. In some embodiments, the fourth cell includes a transistor, and the intra-cell PG rail is electrically connected to the source of the transistor.

[0279] In some embodiments, a device includes: first, second, and third power / ground (PG) conductive elements extending along a first direction; a first set of at least three conductive tracks located between the first and second PG conductive elements, and a second set of at least three conductive tracks located between the second and third PG conductive elements, with the conductive tracks arranged in equal numbers between the first and second PG conductive elements and between the second and third PG conductive elements; a first unit having a first height in a second direction orthogonal to the first direction and overlapping all conductive tracks of the first set of at least three conductive tracks; a second unit having a second height and overlapping all conductive tracks of the first set of at least three conductive tracks and overlapping at least one conductive track of the second set of at least three conductive tracks, such that the second height is greater than the first height; a third unit overlapping all conductive tracks of the second set of at least three conductive tracks and having a first height, such that the first unit and the third unit have the same height; and a fourth unit having a fourth height and overlapping less than all conductive tracks of the second set of at least three conductive tracks, the combined height of the first and third units being the same as the combined height of the second and fourth units. In some embodiments, in the fourth cell, the conductive track is configured as an intra-cell PG track extending along a first direction, and the intra-cell PG track is electrically connected to the source of the transistor. In some embodiments, the first PG conductive element, the second PG conductive element, the third PG conductive element, the first set of at least three conductive tracks, and the second set of at least three conductive tracks are formed in the same first layer, and the intra-cell PG track is connected to the second PG conductive element via an extended via connection extending in a second direction and contacting the intra-cell PG track and the second PG conductive element. In some embodiments, the first, second, third, and fourth cells each have at least one active region formed in the substrate, a diffused upper metal layer positioned above the active region, the first layer being the lowest conductive material layer above the diffused upper metal layer, and the extended via connection aligned with the diffused upper metal element and interposed between the diffused upper metal element and the first layer. In some embodiments, the first, second, third, and fourth cells each have at least one active region formed in the substrate, the fourth cell includes a transistor having a gate, and the extended via connection aligned with the gate and interposed between the gate and the first layer. In some embodiments, the filling unit extends along the second direction between the first unit and the third unit and between the second unit and the fourth unit, and the PG track in the unit is electrically connected to the second PG conductive element through a connection in the filling unit.In some embodiments, the first PG conductive element, the second PG conductive element, the third PG conductive element, the first group of at least three conductive tracks, and the second group of at least three conductive tracks are formed in the same first layer. The first cell, the second cell, the third cell, and the fourth cell each have at least one active region formed in the substrate. The diffused upper metal layer is located above the active region. The first layer is the lowest conductive material layer above the diffused upper metal layer, and the connection is aligned with the diffused upper metal element in the fill cell and is interposed between the diffused upper metal element and the first layer. In some embodiments, the height of the second PG conductive element in the second direction varies within the fill cell, and in the fourth cell, the second PG conductive element is integral with the PG track within the cell along the first direction.

[0280] In some embodiments, a method of manufacturing an integrated circuit device includes: forming first, second, and third power / ground (PG) conductive elements extending along a first direction; forming a first group of at least three conductive tracks between the first PG conductive element and the second PG conductive element, and forming a second group of at least three conductive tracks between the second PG conductive element and the third PG conductive element, the conductive tracks being formed in equal numbers between the first PG conductive element and the second PG conductive element and between the second PG conductive element and the third PG conductive element; forming circuits in a first row of cells, the first row of cells being arranged in the first direction and overlapping with the first group of at least three conductive tracks; and forming circuits in a second row of cells, the second row of cells being arranged in the first direction and overlapping with the second group of at least three conductive tracks. In some embodiments, in a first row of cells, the first cell has a first height in a second direction orthogonal to the first direction, the second cell in the first row has a height greater than the first height, the third cell in the second row shares a boundary extending in the first direction with the first cell and has the first height, the fourth cell in the second row shares a boundary extending in the first direction with the second cell and has a height less than the first height, the combined height of the second and fourth cells corresponds to the combined height of the first and third cells, and between the second and third PG conductive elements, a conductive track is aligned with the boundary extending in the first direction between the second and fourth cells and is formed as an intra-cell PG track. In some embodiments, forming a circuit in the first row of cells includes forming a first transistor in the second cell such that the source of the first transistor is electrically connected to the intra-cell PG track; forming a circuit in the second row of cells includes forming a second transistor in the fourth cell such that the source of the second transistor is electrically connected to the intra-cell PG track; and forming the intra-cell PG track includes forming at least one of a first electrical connection or a second electrical connection to electrically connect the intra-cell PG track to the second PG conductive element. In some embodiments, forming the first electrical connection includes forming an extended via connection extending along the second direction and connecting the intra-cell PG track and the second PG conductive element, wherein the first PG conductive element, the second PG conductive element, the third PG conductive element, the first group of at least three conductive tracks, and the second group of at least three conductive tracks are formed in the same first layer. In some embodiments, forming the second electrical connection includes forming a connection connecting the intra-cell PG track and the second PG conductive element, wherein the connection is formed in a filler cell, and the filler cell extends along the second direction between the first cell and the third cell and between the second cell and the fourth cell.

[0281] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device comprising: First, second and third power / ground (PG) conductive elements extend along a first direction; A first group of at least three conductive tracks are located between the first PG conductive element and the second PG conductive element, and a second group of at least three conductive tracks are located between the second PG conductive element and the third PG conductive element, wherein the conductive tracks are arranged in equal numbers between the first PG conductive element and the second PG conductive element and between the second PG conductive element and the third PG conductive element; A first row of cells is arranged in the first direction and overlaps the first set of at least three conductive tracks; as well as A second row of cells is arranged in the first direction and overlaps the second set of at least three conductive tracks; in: In the first row of cells, the first cells have a first height in a second direction orthogonal to the first direction, In the first row of cells, the height of the second cell is greater than the first height, In the second row of cells, a third cell shares a boundary extending in the first direction with the first cell and has the first height, In the second row of cells, a fourth cell shares a boundary extending in the first direction with the second cell and has a height less than the first height, a combined height of the second cell and the fourth cell corresponds to a combined height of the first cell and the third cell, and Between the second PG conductive element and the third PG conductive element, a conductive track is aligned with the boundary of the second cell and the fourth cell extending in the first direction and is configured as an intra-cell PG track.

2. The integrated circuit device according to claim 1, wherein: Each of the first row unit and the second row unit has at least one active region formed in the substrate, and the at least one active region extends along the first direction, and The conductive tracks are located in the lowest layer of conductive material above the substrate.

3. The integrated circuit device according to claim 1, wherein: All conductive tracks have the same dimensions in the second direction.

4. The integrated circuit device according to claim 1, wherein: The first unit has a first active region extending along the first direction, the second unit has a second active region extending along the first direction, and a first isolation pattern isolates the second active region from the first active region, and the first isolation pattern extends along the second direction; and The third unit has a third active region extending along the first direction, the fourth unit has a fourth active region extending along the first direction, a second isolation pattern isolates the third active region, and the second isolation pattern extends along the second direction.

5. The integrated circuit device according to claim 4, wherein: The second isolation pattern is aligned with the first isolation pattern.

6. The integrated circuit device according to claim 1, wherein: The first unit has a first active region extending along the first direction, the second unit has a second active region extending along the first direction, and a size of the first active region in the second direction is smaller than a size of the second active region in the second direction; and The third unit has a third active region extending along the first direction, the fourth unit has a fourth active region extending along the first direction, and a size of the third active region in the second direction is larger than a size of the fourth active region in the second direction.

7. An integrated circuit device comprising: First, second and third power / ground (PG) conductive elements extend along a first direction; A first group of at least three conductive tracks are located between the first PG conductive element and the second PG conductive element, and a second group of at least three conductive tracks are located between the second PG conductive element and the third PG conductive element, wherein the conductive tracks are arranged in equal numbers between the first PG conductive element and the second PG conductive element and between the second PG conductive element and the third PG conductive element; The first unit has a first height in a second direction orthogonal to the first direction and overlaps all conductive tracks of the first group of at least three conductive tracks; The second unit has a second height and overlaps with all conductive tracks of the first set of at least three conductive tracks and overlaps with at least one conductive track of the second set of at least three conductive tracks, such that the second height is greater than the first height; a third unit overlapping all conductive tracks of the second set of at least three conductive tracks and having the first height, such that the first unit and the third unit have the same height; as well as The fourth cell has a fourth height that overlaps less than all of the second set of at least three conductive tracks, and the combined height of the first cell and the third cell is the same as the combined height of the second cell and the fourth cell.

8. The integrated circuit device according to claim 7, wherein: In the fourth unit: The conductive track is configured as an intra-cell PG track extending along the first direction, and the intra-cell PG track is electrically connected to the source of the transistor.

9. The integrated circuit device according to claim 8, wherein: The first PG conductive element, the second PG conductive element, the third PG conductive element, the first group of at least three conductive tracks, and the second group of at least three conductive tracks are formed in the same first layer, and The intra-cell PG rail is connected to the second PG conductive element through an extended via connection extending in the second direction and contacting the intra-cell PG rail and the second PG conductive element.

10. The integrated circuit device according to claim 9, wherein: Each of the first unit, the second unit, the third unit, and the fourth unit has at least one active region formed in a substrate. A diffused upper metal layer is located above the active area, The first layer is the lowest conductive material layer above the diffused upper metal layer, and The extended via connection is aligned with the diffusion upper metal element and is between the diffusion upper metal element and the first layer.

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