SiC MOSFET device with split gate structure

Abstract

The SiC MOSFET device with the split gate structure comprises an N + substrate layer, an N-epitaxial layer, a gate oxide layer, a Poly layer, an isolation dielectric layer and a front electrode metal layer which are sequentially arranged from bottom to top, the N-epitaxial layer is internally provided with a pair of P-body regions which respectively extend downwards from the top surface of the N-epitaxial layer; the first N + region extends downwards from the top surface of the P-body region; the first P + region extends downwards from the top surface of the P-body region and is connected with the side part of the first N + region; the second P + region extends downwards to the lower part of the P-body region along the inner side of the P-body region, and wraps the corner of the inner side of the P-body region; the second N + region extends downwards from the top of the second P + region and is connected with the P-body region; the bottom surface of the gate oxide layer is respectively connected with the first N + region, the P-body region and the second N + region; the Poly layer is arranged on the top surface of the gate oxide layer; the switching performance of the device can be improved to a certain extent, and the switching loss is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFET device with a split-gate structure. Background Art

[0002] As a third-generation semiconductor material, SiC material has characteristics such as a wide bandgap and high breakdown field strength. This makes SiC devices more voltage-resistant than Si devices of the same power level, but its gate oxide is also more susceptible to breakdown. Because SiC's bandgap is three times that of Si, for the same threshold voltage, the gate oxide thickness of SiC MOSFET devices is thinner than that of SiMOSFET. As a result, the gate oxide layer of SiC MOSFETs must withstand higher electric field strengths, resulting in reduced gate oxide reliability.

[0003] Gate oxide reliability is primarily a function of both gate-source reliability and gate-drain reliability. One way to improve gate-source reliability is to perform NO annealing after the gate oxide layer is formed to reduce the interface state density. This NO annealing can reduce the interface state density by more than an order of magnitude compared to before annealing. Gate-drain reliability is primarily reflected in the device's reverse blocking performance. In the blocking state of a SiC MOSFET structure, the P-body and N-epitaxial layer form a space charge region that withstands reverse voltage. The maximum electric field is concentrated at the top of the JFET region, just below the gate oxide. The smaller the JFET region width, the more pronounced the pinch-off effect, the smaller the electric field strength in the gate oxide layer, and the better the device reliability. However, the smaller the JFET region width, the greater the on-resistance, which affects the device's on-resistance. Therefore, developing a SiC MOSFET structure that can both improve gate oxide reliability and reduce on-resistance is a pressing technical challenge. Utility Model Content

[0004] In response to the above problems, the utility model provides a SiC MOSFET device with a split-gate structure, which effectively shields strong electric fields, enhances device withstand voltage, and improves gate oxide reliability without affecting on-resistance.

[0005] The technical solution of the utility model is:

[0006] A SiC MOSFET device with a split-gate structure includes, from bottom to top, an N+ substrate layer, an N- epitaxial layer, a gate oxide layer, a Poly layer, an isolation dielectric layer, and a front electrode metal layer;

[0007] The N-epitaxial layer is provided with:

[0008] A pair of P-body regions are provided, each extending downward from the top surface of the N-epitaxial layer;

[0009] a first N+ region extending downward from a top surface of the P-body region;

[0010] a first P+ region extending downward from a top surface of the P-body region and connected to a side of the first N+ region;

[0011] a second P+ region extending downward along the inner side of the P-body region to below the P-body region and wrapping the inner corner of the P-body region;

[0012] a second N+ region extending downward from a top portion of the second P+ region and connected to the P-body region;

[0013] The bottom surface of the gate oxide layer is connected to the first N+ region, the P-body region and the second N+ region respectively; the Poly layer is arranged on the top surface of the gate oxide layer;

[0014] An ohmic contact alloy layer is provided on the top surface of the first N+ region and the first P+ region; the ohmic contact alloy layer (11) is separated from the gate oxide layer and the Poly layer by an isolation dielectric layer.

[0015] Specifically, the bottom of the isolation dielectric layer is connected to the N-epitaxial layer, the first N+ region and the Poly layer.

[0016] The ohmic contact alloy layer is respectively located on the left and right sides of the isolation dielectric layer, and the side surfaces thereof are in contact with the isolation dielectric layer.

[0017] The bottom of the isolation dielectric layer is connected to the N-epitaxial layer, the first N+ region and the Poly layer.

[0018] The ohmic contact alloy layer is respectively located on the left and right sides of the isolation dielectric layer, and the side surfaces thereof are in contact with the isolation dielectric layer.

[0019] Specifically, the gate oxide layer has a thickness of 40-60 nm.

[0020] Specifically, the thickness of the Poly layer is 800 nm.

[0021] Specifically, the depth of the P-body region is 0.8-1.5 μm.

[0022] In the reverse blocking mode of the present invention, the second P+ region forms a PN junction with the first N+ region, which can shield strong electric fields, increase the device's withstand voltage, and reduce the gate oxide electric field. At the same time, the P+ region in the area below the P-body can reduce the risk of breakdown at the corners of the P-body region, thereby protecting the gate oxide and improving device reliability. An N+ conductive region, namely the second N+ region, is provided around the channel to reduce the on-resistance of the current path. By adopting a split gate form, the overlapping area between the gate and the N- withstand voltage region can be reduced, thereby achieving the purpose of reducing the gate capacitance, which can improve the switching performance of the device to a certain extent and reduce switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure for preparing N-epitaxial layer;

[0024] Figure 2 It is a schematic diagram of the structure of the preparation of the P-body region;

[0025] Figure 3 It is a schematic diagram of the structure for preparing the first N+ region;

[0026] Figure 4 It is a schematic diagram of the structure for preparing the first P+ region;

[0027] Figure 5 It is a schematic diagram of the structure for preparing the second P+ region;

[0028] Figure 6 It is a schematic diagram of the structure for preparing the second N+ region;

[0029] Figure 7 It is a schematic diagram of the structure for preparing a gate oxide layer;

[0030] Figure 8 It is a structural diagram of preparing the Poly layer;

[0031] Figure 9 1. It is a schematic diagram of the structure for preparing an isolation dielectric layer;

[0032] Figure 10 1. It is a schematic diagram of the structure for preparing an ohmic contact alloy layer;

[0033] Figure 11 It is a schematic diagram of the structure for preparing the front electrode metal layer;

[0034] In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the P-body region, 4 is the first N+ region, 5 is the first P+ region, 6 is the second P+ region, 7 is the second N+ region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0036] The present invention is described below with reference to Figures 1-11;

[0037] A method for preparing a SiC MOSFET device with a split-gate structure comprises the following steps:

[0038] Step 1: epitaxially grow an N-epitaxial layer 2 on the N+ substrate layer 1, and sequentially implant into the N-epitaxial layer 2 to form a P-body region 3, a first N+ region 4, and a first P+ region 5;

[0039] Specifically, such as Figure 1-2 As shown, an N-epitaxial layer 2 is formed by epitaxial growth on the N+ substrate layer 1, and a P-body region 3 is formed on the top of the N-epitaxial layer 2 by ion implantation, with a concentration range of 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um, such as Figure 2 As shown;

[0040] like Figure 3 As shown, SiO2 is used as a mask to implant N ions into the P-body region 3 multiple times to form the first N+ region 4 with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um, and RCA cleaning is performed after the injection is completed;

[0041] like Figure 4 As shown, using SiO2 as a mask, Al ions are implanted multiple times into the P-body region 3 to form the first P+ region 5 with a concentration range of 1E 18 cm -2 -1E 19 cm -2 The injection depth is 0.4-0.8um, and the mask is removed after the injection is completed;

[0042] Step 2, such as Figure 5 As shown, a second P+ region 6 connected to the P-body region 3 is formed on the top of the N-epitaxial layer 2 by multiple Al ion implantations, with a concentration range of 1E 18 cm -2 -1E 19 cm -2, the injection depth is 1-1.7um;

[0043] Step three, such as Figure 6 As shown, a second N+ region 7 is formed by multiple N ion implantations on the top of the second P+ region 6, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the implantation depth is 0.2-0.4um; then a thin layer of graphite is deposited on the surface of the device as protection, and annealed at a high temperature of 1650℃-1690℃ for 15 minutes to activate the implanted ions;

[0044] Step 4: Figure 7 As shown, a gate oxide layer 8 is grown on top of the N-epitaxial layer 2 by dry oxygen thermal oxidation and a Poly layer 9 is deposited on the gate oxide layer 8;

[0045] Specifically, the gate oxide layer 8 is grown to a thickness of 40-60 nm and is annealed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the density of the gate oxide layer and reduce defects.

[0046] like Figure 8 As shown, a Poly layer 9 is deposited on the gate oxide layer 8 by LPCVD method with a thickness of 800nm ​​to serve as a gate electrode.

[0047] Step five, such as Figure 9 As shown, an isolation dielectric layer 10 covering the Poly layer 9 is deposited on the N-epitaxial layer 2 to isolate the gate electrode and the source electrode metal;

[0048] Step six, such as Figure 10 As shown, a layer of Ni metal is sputtered on the first N+ region 4 and the first P+ region 5 as the source ohmic contact metal layer 11, and then annealed at a high temperature of 1000°C for 5 minutes to form an alloying treatment with the first N+ region 4 and the first P+ region 5;

[0049] Step seven, such as Figure 11 As shown, a front electrode metal layer 12 is formed on the isolation dielectric layer 10 and the ohmic contact alloy layer 11 by Al metal sputtering to serve as a source electrode lead.

[0050] In this case, the P-body region 3, the first N+ region 4, the first P+ region 5, the second P+ region 6 and the second N+ region 7 are all at the same potential, which can not only improve the reliability of the gate oxide, but also enhance the voltage resistance and short-circuit tolerance of the device.

[0051] At the same time, the implantation depth of the second P+ region 6 is greater than that of the P-body region 3 to protect the corners of the P-body region. The implantation depth of the second N+ region 7 is 0.3-0.4 times that of the second P+ region 6, which not only protects the gate oxide and improves gate oxide reliability, but also reduces the on-resistance of the device.

[0052] A SiC MOSFET device with a split-gate structure includes, from bottom to top, an N+ substrate layer 1, an N- epitaxial layer 2, a gate oxide layer 8, a Poly layer 9, an isolation dielectric layer 10, and a front electrode metal layer 12;

[0053] The N-epitaxial layer 2 is provided with:

[0054] A pair of P-body regions 3 are provided, each extending downward from the top surface of the N-epitaxial layer 2;

[0055] A first N+ region 4 extends downward from the top surface of the P-body region 3 and is spaced apart from the side and bottom surfaces of the P-body region 3;

[0056] A first P+ region 5 extends downward from the top surface of the P-body region 3 and is connected to the side of the first N+ region 4; a gap is provided between the bottom surface of the first P+ region 5 and the bottom surface of the P-body region 3;

[0057] The second P+ region 6 extends downward along the inner side of the P-body region 3 to the bottom of the P-body region 3 and wraps the inner corner of the P-body region 3;

[0058] a second N+ region 7 extending downward from the top of the second P+ region 6 and connected to the P-body region 3;

[0059] The bottom surface of the gate oxide layer 8 is connected to the first N+ region 4, the P-body region 3 and the second N+ region 7 respectively; the Poly layer 9 is arranged on the top surface of the gate oxide layer 8;

[0060] Specifically, the gate oxide layer 8 is configured in the form of two split gates, located above the P-body 3, the first N+ region 4, and the second N+ region 7, with the bottom thereof in contact with the N-epitaxial layer 2;

[0061] An ohmic contact alloy layer 11 is provided on the top surfaces of the first N+ region 4 and the first P+ region 5 ; the ohmic contact alloy layer 11 is separated from the gate oxide layer 8 and the Poly layer 9 by an isolation dielectric layer 10 .

[0062] The bottom surface of the ohmic contact alloy layer 11 is connected to the first N+ region 4 and the first P+ region 5 .

[0063] The bottom of the isolation dielectric layer 10 is connected to the N- epitaxial layer 2 , the first N+ region 4 and the Poly layer 9 .

[0064] The ohmic contact alloy layer 11 is located on the left and right sides of the isolation dielectric layer 10 , and the side surfaces thereof are in contact with the isolation dielectric layer 10 .

[0065] Regarding the content disclosed in this case, the following points need to be explained:

[0066] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0067] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to form new embodiments;

[0068] The above are only specific implementation methods disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A SiC MOSFET device having a split-gate structure, characterized in that: The device comprises, from bottom to top, an N+ substrate layer (1), an N- epitaxial layer (2), a gate oxide layer (8), a Poly layer (9), an isolation dielectric layer (10), and a front electrode metal layer (12); The N-epitaxial layer (2) is provided with: A pair of P-body regions (3) are provided, each extending downward from the top surface of the N-epitaxial layer (2); a first N+ region (4) extending downward from the top surface of the P-body region (3); a first P+ region (5), extending downward from the top surface of the P-body region (3) and connected to a side portion of the first N+ region (4); A second P+ region (6) extends downward along the inner side of the P-body region (3) to below the P-body region (3) and wraps around the inner corner of the P-body region (3); a second N+ region (7), extending downward from the top of the second P+ region (6) and connected to the P-body region (3); The bottom surface of the gate oxide layer (8) is respectively connected to the first N+ region (4), the P-body region (3) and the second N+ region (7); An ohmic contact alloy layer (11) is provided on the top surfaces of the first N+ region (4) and the first P+ region (5); the ohmic contact alloy layer (11) is separated from the gate oxide layer (8) and the Poly layer (9) by an isolation dielectric layer (10).

2. The SiC MOSFET device with a split-gate structure according to claim 1, wherein: The bottom of the isolation dielectric layer (10) is connected to the N-epitaxial layer (2), the first N+ region (4) and the Poly layer (9); The ohmic contact alloy layer (11) is respectively located on the left and right sides of the isolation dielectric layer (10), and the side surfaces are in contact with the isolation dielectric layer (10).

3. The SiC MOSFET device with a split-gate structure according to claim 1, wherein: The gate oxide layer (8) has a thickness of 40-60 nm.

4. The SiC MOSFET device with a split-gate structure according to claim 1, wherein: The thickness of the Poly layer (9) is 800 nm.

5. The SiC MOSFET device with a split-gate structure according to claim 1, wherein: The depth of the P-body region (3) is 0.8-1.5 μm.

Images