Photoelectric converter, sensing device and electronic equipment

Abstract

The utility model provides a photoelectric converter, a sensing device and electronic equipment, and belongs to the technical field of semiconductors. The photoelectric converter includes a substrate; the plurality of photoelectric conversion units are formed in the substrate, each photoelectric conversion unit comprises a first semiconductor region and a second semiconductor region, and a PN junction is formed on a contact interface between the first semiconductor region and the second semiconductor region; each isolation structure is arranged between every two adjacent photoelectric conversion units, each isolation structure comprises a deep trench isolation structure, and each deep trench isolation structure comprises a first trench extending into the substrate from the surface of the substrate, and an insulating material and a semiconductor material which are filled in the first trench. According to the invention, crosstalk between adjacent photoelectric conversion units can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a photoelectric converter, a sensing device, and an electronic device. Background Art

[0002] Single-photon detection is a key technology for detecting weak optical signals. Its core lies in its ability to detect photons, the smallest quantum of light energy. This technology has broad application prospects in areas such as optical ranging, 3D imaging, and autonomous driving radar. Currently, single-photon detection devices primarily include avalanche photodiodes, photomultiplier tubes, vacuum avalanche photodiodes, enhanced photodiodes, superconducting single-photon detectors, and superconducting transition edge sensors. Silicon-based single-photon avalanche diodes (SPADs) have become one of the more mature detection devices in the industry due to their high quantum efficiency and strong environmental adaptability.

[0003] SPAD devices typically consist of a substrate, a neutral region, and a depletion region. Under reverse bias, incident photons generate electron-hole pairs within the device. These carriers are separated and collected by the electric field, forming a photogenerated current. When the reverse bias exceeds the avalanche breakdown voltage, carriers are ionized by impact to generate new carriers, creating an avalanche effect that enables the detection of single photons. However, SPAD devices generate a large number of photons and electron-hole pairs during operation. The recombination and propagation of these carriers can cause optical crosstalk (O-XT) and electrical crosstalk (E-XT), seriously affecting device performance.

[0004] Currently, SPAD device isolation processes primarily include shallow trench isolation (STI) and deep trench isolation (DTI). STI no longer meets the requirements for good electrical and optical isolation, while DTI, while capable of achieving complete electrical isolation, has limited effectiveness in suppressing optical crosstalk. Furthermore, while metal-filled isolation, such as tungsten (W) / aluminum (Al), can effectively reduce crosstalk, it requires high equipment requirements and is costly, making it difficult to implement on existing production lines and equipment. Utility Model Content

[0005] To overcome the problems existing in the related art, this specification provides a photoelectric converter, a sensing device, and an electronic device to reduce crosstalk between adjacent photoelectric conversion units.

[0006] According to a first aspect of the present disclosure, there is provided a photoelectric converter, comprising:

[0007] substrate;

[0008] A plurality of photoelectric conversion units are formed in the substrate, the photoelectric conversion units comprising a first semiconductor region and a second semiconductor region, wherein a contact interface between the first semiconductor region and the second semiconductor region forms a PN junction;

[0009] An isolation structure is provided between two adjacent photoelectric conversion units and is used to reduce crosstalk between the two adjacent photoelectric conversion units. The isolation structure includes a deep trench isolation structure, and the deep trench isolation structure includes a first trench extending from the surface of the substrate to the substrate and an insulating material and a semiconductor material filled in the first trench. A first isolation layer and a second isolation layer are provided in the first trench. The first isolation layer is coated on the periphery of the second isolation layer, and the first isolation layer is formed on the sidewall of the first trench. The first isolation layer includes an insulating material, and the second isolation layer includes a semiconductor material.

[0010] In some exemplary embodiments of the present disclosure, the band gap width of the semiconductor material filled in the first trench is 1.12 eV-1.65 eV.

[0011] In some exemplary embodiments of the present disclosure, the semiconductor material filled in the first trench includes polysilicon.

[0012] In some exemplary embodiments of the present disclosure, the isolation structure is provided at the periphery of the first semiconductor region and the second semiconductor region;

[0013] The deep trench isolation structure further includes a second trench extending from the substrate surface into the substrate and an insulating material and a semiconductor material filled in the second trench;

[0014] Wherein, the second groove is arranged around the periphery of the first groove, or the second groove intersects with the first groove.

[0015] In some exemplary embodiments of the present disclosure, the semiconductor material filled in the second trench includes polysilicon.

[0016] In some exemplary embodiments of the present disclosure, the orthographic projection of the first groove and / or the second groove on the plane where the substrate is located is a sawtooth shape or a wavy shape.

[0017] In some exemplary embodiments of the present disclosure, the isolation structure further comprises a shallow trench isolation structure, wherein the shallow trench isolation structure comprises a third trench extending from the substrate surface into the substrate and a metal material filled in the third trench;

[0018] The depth of the third groove is smaller than the depth of the first groove, and the orthographic projections of the third groove and the first groove on the plane where the substrate is located do not overlap.

[0019] In some exemplary embodiments of the present disclosure, a depth of the third trench is greater than a depth of a PN junction formed by contact between the first semiconductor region and the second semiconductor region.

[0020] In some exemplary embodiments of the present disclosure, the substrate has a concentration gradient region formed by adjusting the doping concentration in the substrate, and the concentration gradient region is used to guide carriers into an avalanche region formed by the PN junction under a high reverse bias.

[0021] In some exemplary embodiments of the present disclosure, the substrate is a P-type substrate, and the doping concentration of the concentration gradient region forms a gradient distribution from low concentration to high concentration from the PN junction to the periphery of the substrate.

[0022] In some exemplary embodiments of the present disclosure, the photoelectric conversion unit further includes a third semiconductor region, wherein the third semiconductor region is configured to guide carriers into an avalanche region formed by the PN junction under a high reverse bias voltage.

[0023] In some exemplary embodiments of the present disclosure, in the thickness direction of the substrate, the third semiconductor region is located below the PN junction, and the second semiconductor region is located below the first semiconductor region;

[0024] The third semiconductor region has the same doping type as the first semiconductor region, and the doping concentration of the third semiconductor region is lower than the doping concentration of the first semiconductor region; or

[0025] The third semiconductor region has the same doping type as the second semiconductor region and the substrate, and the doping concentration of the third semiconductor region is lower than the doping concentration of the second semiconductor region and higher than the doping concentration of the substrate.

[0026] In some exemplary embodiments of the present disclosure, in the thickness direction of the substrate, the second semiconductor region is located below the first semiconductor region;

[0027] The photoelectric conversion unit further includes:

[0028] a first electrode connected to the first semiconductor region;

[0029] A second electrode and a third electrode, both connected to the substrate;

[0030] Wherein, the first electrode and the second electrode are used to apply a reverse bias voltage to form an avalanche region at the PN junction;

[0031] The third electrode is located on a side of the second electrode away from the first electrode, and is used to apply a voltage to guide carriers into an avalanche region formed by the PN junction under a high reverse bias voltage.

[0032] In some exemplary embodiments of the present disclosure, when the deep trench isolation structure further includes a second trench, the third electrode is connected to the surface of the substrate between the first trench and the second trench.

[0033] According to a second aspect of the present disclosure, a sensing device is provided, comprising the photoelectric converter according to the first aspect, wherein the sensing device acquires relevant information by sensing an optical signal received by the photoelectric converter.

[0034] According to a third aspect of the present disclosure, an electronic device is provided, comprising the sensing device according to the second aspect, wherein the electronic device is configured to execute a corresponding function based on relevant information acquired by sensing an electrical signal by the sensing device.

[0035] The technical solution provided by the present disclosure may have the following beneficial effects:

[0036] The photoelectric converter provided by the present invention realizes deep isolation between the photoelectric conversion units through a first groove extending from the surface of the substrate to the interior of the substrate. The insulating material and semiconductor material filled in the first groove can effectively reduce the electrical crosstalk and optical crosstalk between the photoelectric conversion units. Among them, the insulating material has a high resistivity, which can effectively prevent the leakage of current between the photoelectric conversion units, achieve effective electrical isolation and improve the electrical performance and stability of the device. The introduction of polycrystalline silicon can effectively reduce the optical crosstalk between adjacent photoelectric conversion units. Polycrystalline silicon not only has a low refractive index, but also has a certain light absorption capacity, which can absorb photons released by the PN junction avalanche region. This design effectively reduces the propagation and reflection of photons between the photoelectric conversion units, thereby significantly reducing optical crosstalk.

[0037] Furthermore, the isolation structure disclosed herein can be fabricated using existing processes and equipment. Insulating materials (such as silicon dioxide) are commonly used in semiconductor manufacturing processes, with mature deposition and processing techniques. The use of these materials ensures the isolation structure's insulation performance while aligning with existing processes. Polysilicon is also widely used in semiconductor manufacturing for structures such as transistor gates, and its deposition and processing techniques are mature, eliminating the need for new equipment and processes.

[0038] The photoelectric converter provided by the present disclosure can effectively reduce electrical crosstalk and optical crosstalk between photoelectric conversion units without increasing additional equipment costs, thereby improving the performance of the photoelectric converter.

[0039] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0041] Figure 1 FIG. 1 is a schematic cross-sectional view of a photoelectric converter in an exemplary embodiment of the present disclosure.

[0042] Figure 2 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0043] Figure 3 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0044] Figure 4 FIG. 1 is a schematic top view of a photoelectric converter in an exemplary embodiment of the present disclosure.

[0045] Figure 5 FIG. 1 is a schematic top view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0046] Figure 6 FIG. 4 is a schematic top view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0047] Figure 7 FIG. 4 is a schematic top view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0048] Figure 8 FIG. 4 is a schematic top view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0049] Figure 9 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0050] Figure 10 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0051] Figure 11 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0052] Figure 12 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0053] Figure 13 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0054] Figure 14 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0055] Figure 15 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0056] Figure 16 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0057] Figure 17 FIG. 4 is a schematic cross-sectional view of a photoelectric converter in another exemplary embodiment of the present disclosure.

[0058] Description of Reference Numerals

[0059] 100-substrate; 200-photoelectric conversion unit; 210-first semiconductor region; 220-second semiconductor region; 230-third semiconductor region; T1-first electrode; T2-second electrode; T3-third electrode; 300-isolation structure; 300a-deep trench isolation structure; 310-first trench; 311-first isolation layer; 312-second isolation layer; 320-second trench; 321-third isolation layer; 322-fourth isolation layer; 300b-shallow trench isolation structure; 330-third trench. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0062] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0063] In this disclosure, terms such as "perpendicular" and "equal" refer to perpendicularity and equality within the range of process tolerance, not absolute perpendicularity and equality. Process tolerance can be within ±10% or ±5%. For example, if a first direction and a second direction are perpendicular, it can be understood that the angle between the first direction and the second direction can be 90°±5°.

[0064] Early SPAD devices had large cell sizes (20μm-50μm), and a front-side illumination (FSI) architecture was used to achieve high photon detection efficiency (PDE). Due to the large cell size, crosstalk (XT) was less pronounced, and standard shallow trench isolation (STI) processes (with a depth of approximately several hundred nanometers) were typically used to isolate the cells. However, as cell size continues to shrink, crosstalk becomes increasingly problematic, necessitating the consideration of better cell isolation solutions in device design.

[0065] Related technologies utilize deep trench isolation (DTI) technology, which creates isolation by filling the deep trench with oxide, metal (such as W or Al), and high-k (HK) dielectric materials. The high reflectivity of metal significantly reduces crosstalk by approximately an order of magnitude. However, this advanced process requires high-aspect-ratio metal filling equipment and glue layer growth equipment, necessitating significant capital investment (approximately 10 million yuan), making it difficult for most companies to implement in the early stages of technology development.

[0066] Based on this, Figure 1 、 Figure 2 、 Figure 4 and Figure 5As shown, an embodiment of the present disclosure provides a photoelectric converter, including a substrate 100, a plurality of photoelectric conversion units 200, and an isolation structure 300. The plurality of photoelectric conversion units 200 are formed within the substrate 100. The photoelectric conversion units 200 include a first semiconductor region 210 and a second semiconductor region 220. The contact interface between the first semiconductor region 210 and the second semiconductor region 220 forms a PN junction. The isolation structure 300 is provided between two adjacent photoelectric conversion units 200 to reduce crosstalk between the two adjacent photoelectric conversion units 200. The isolation structure 300 includes a deep trench isolation structure 300a. The deep trench isolation structure 300a includes a first trench 310 extending from the surface of the substrate 100 into the substrate 100, and an insulating material and a semiconductor material filling the first trench 310.

[0067] The photoelectric converter provided by the present disclosure realizes deep isolation between the photoelectric conversion units 200 through the first groove 310 extending from the surface of the substrate 100 to the interior of the substrate 100. The insulating material and semiconductor material filled in the first groove 310 can effectively reduce the electrical crosstalk and optical crosstalk between the photoelectric conversion units 200. Among them, the insulating material has a high resistivity, which can effectively prevent the leakage of current between the photoelectric conversion units 200, achieve effective electrical isolation and improve the electrical performance and stability of the device. The introduction of polycrystalline silicon can effectively reduce the optical crosstalk between adjacent photoelectric conversion units 200. Polycrystalline silicon not only has a low refractive index, but also has a certain light absorption capacity, which can absorb photons released by the PN junction avalanche region. This design effectively reduces the propagation and reflection of photons between the photoelectric conversion units 200, thereby significantly reducing optical crosstalk.

[0068] In addition, the isolation structure 300 disclosed herein can be completed using existing processes and equipment. ) is a commonly used material in semiconductor manufacturing, with mature deposition and processing techniques. The use of this material ensures the insulation performance of isolation structure 300 while aligning with existing processes. Polysilicon is also widely used in semiconductor manufacturing for structures such as transistor gates, and its deposition and processing techniques are mature, eliminating the need for new equipment and processes.

[0069] The photoelectric converter provided by the present disclosure can effectively reduce electrical crosstalk and optical crosstalk between the photoelectric conversion units 200 without increasing additional equipment costs, thereby improving the performance of the photoelectric converter.

[0070] The various parts of the photoelectric converter provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings:

[0071] The photoelectric converter provided by the present disclosure can be a single-photon detection device, such as an avalanche photodiode, a photomultiplier tube, a vacuum avalanche photodiode, an enhanced photodiode, etc. The photoelectric converter can be used in optical communications, imaging technology, 3D sensing, biomedical imaging, spectral analysis and other fields. The photoelectric converter can adopt a back-illuminated structure, that is, light is incident from the back of the device and directly reaches the photosensitive area. Compared with the front-illuminated structure, the back-illuminated structure does not need to pass through metal electrodes or other circuit structures, avoiding the light blocking problem common in the front-illuminated structure, significantly improving the absorption efficiency of photons, especially in the detection of long-wave bands (such as infrared light).

[0072] The photoelectric converter disclosed herein includes a substrate 100, a photoelectric conversion unit 200, and an isolation structure 300. There are multiple photoelectric conversion units 200, and the isolation structure 300 is used to reduce crosstalk between adjacent photoelectric conversion units 200.

[0073] The substrate 100 can be a P-type substrate or an N-type substrate. A P-type substrate can be achieved by doping the silicon substrate 100 with trivalent ions (such as boron), which has a higher hole concentration and a lower electron concentration. SPAD devices using a P-type substrate typically have lower dark current and higher sensitivity, making them suitable for photon detection under low-light conditions, such as in quantum communications and single-photon imaging. An N-type substrate can be achieved by doping the silicon substrate 100 with pentavalent ions (such as phosphorus or arsenic), which has a higher electron concentration and a lower hole concentration. SPAD devices using an N-type substrate typically have higher carrier mobility and response speed, making them suitable for applications requiring high frequency and high bandwidth, such as LiDAR and 3D imaging.

[0074] The photoelectric conversion unit 200 is a basic unit for achieving photoelectric conversion. Each photoelectric conversion unit 200 is formed within the substrate 100. Multiple photoelectric conversion units 200 can be arranged within the substrate 100 in a specific arrangement. This arrangement can be a regular array or other specific geometric arrangement. This disclosure does not limit the specific arrangement to accommodate different design requirements and applications.

[0075] like Figures 1 to 3 As shown, a single photoelectric conversion unit 200 includes a first semiconductor region 210 and a second semiconductor region 220. A PN junction is formed at the interface between the first semiconductor region 210 and the second semiconductor region 220. Under reverse bias, the PN junction can efficiently detect incident photons and amplify the signal of a single photon to a detectable level through the avalanche multiplication effect.

[0076] The first semiconductor region 210 and the second semiconductor region 220 can be stacked in the substrate 100, such as being stacked in the substrate 100 along the thickness direction of the substrate 100. The doping types of the first semiconductor region 210 and the second semiconductor region 220 are opposite. For example, the first semiconductor region 210 can be P-type doped and the second semiconductor region 220 can be N-type doped, or the first semiconductor region 210 can be N-type doped and the second semiconductor region 220 can be P-type doped. The specific setting can be based on actual application requirements and scenarios. Optionally, the first semiconductor region 210 can be located above the second semiconductor region 220, that is, in an area close to the front surface of the substrate 100. In one embodiment, the substrate 100 is a P-type substrate, the first semiconductor region 210 is located above the second semiconductor region 220, the first semiconductor region 210 is N-type doped, and the second semiconductor region 220 is P-type doped.

[0077] like Figures 1 to 8 As shown, the isolation structure 300 may surround the periphery of the first semiconductor region 210 and the second semiconductor region 220. The isolation structure 300 includes a deep trench isolation structure 300a. The deep trench isolation structure 300a includes a first trench 310 extending from the surface of the substrate 100 into the substrate 100, and an insulating material and a semiconductor material filled in the first trench 310. Optionally, the semiconductor material filled in the first trench has a band gap of 1.12 eV to 1.65 eV, and may specifically be polycrystalline silicon.

[0078] Furthermore, the isolation structure 300 can be closed around the periphery of the first semiconductor region 210 and the second semiconductor region 220 to form a complete isolation ring, thereby preventing the conduction of photons and carriers between adjacent photoelectric conversion units 200 and reducing optical and electrical crosstalk. The closed ring formed by the isolation structure 300 can be circular, square, or other polygonal, depending on the geometric arrangement and design requirements of the photoelectric conversion units 200.

[0079] In some embodiments, the isolation structure 300 includes a deep trench isolation structure 300 a , which includes a first trench 310 extending from a surface of the substrate 100 into the substrate 100 and an insulating material and polysilicon filled in the first trench 310 .

[0080] The first trench 310 can be formed by a deep trench isolation process, and its depth can be 3μm-9μm, but is not limited thereto. The first trench 310 can be formed by etching the front side of the substrate 100 in one go, or it can be formed by etching in stages from the front and back sides of the substrate 100 respectively. Among them, the staged etching can first etch a groove of a certain depth on the front side of the substrate 100. The depth of the front etching can be adjusted according to the process requirements, and is usually a portion of the total depth (for example, 1 / 2 or 1 / 3). Afterwards, the back side is thinned and etched. Specifically, the substrate 100 can be turned over and the back side is thinned so that the thickness of the substrate 100 meets the design requirements. The remaining depth is then etched on the back side until it is connected with the groove etched on the front side. Back side etching requires precise control of the etching depth to avoid over-etching.

[0081] The first trench 310 is filled with insulating material and semiconductor material. Insulating material, such as silicon dioxide ( ), which can effectively prevent the conduction of current between the photoelectric conversion units 200, thereby significantly reducing electrical crosstalk. In the deep trench isolation process, It can be accurately filled into the trench through techniques such as chemical vapor deposition (CVD) to form a high-quality isolation layer.

[0082] The semiconductor material can be polycrystalline silicon, and its inclusion further enhances the optical isolation performance of the deep trench isolation structure 300a. Polycrystalline silicon has a certain light absorption capacity, effectively absorbing photons released by the PN junction avalanche region, reducing the propagation and reflection of photons between the photoelectric conversion units 200, thereby significantly reducing optical crosstalk. This is particularly important for back-illuminated (BSI) photoelectric converters, as BSI structures generally have higher photon detection efficiency but are also more susceptible to optical crosstalk.

[0083] like Figure 1 and Figure 2 As shown, in the first trench 310 , insulating material can be used to form a first isolation layer 311 , and semiconductor material can be used to form a second isolation layer 312 . The first isolation layer 311 is wrapped around the periphery of the second isolation layer 312 , and the first isolation layer 311 is formed on the sidewall of the first trench 310 .

[0084] This structural design exploits the physical properties of different materials to achieve more efficient optical isolation. Although polycrystalline silicon (pSi) and silicon (Si) have similar refractive indices, and from an optical reflection perspective, the SiOx-pSi interface is not significantly different from a pure SiOx interface, it exhibits unique advantages in terms of optical absorption.

[0085] Specifically, the bandgap of silicon dioxide (SiOx) is approximately 9.0 electron volts (eV). This high bandgap makes SiOx less absorptive of visible and near-infrared light. In contrast, the bandgap of semiconductor material polysilicon is typically between 1.12eV and 1.65eV. This lower bandgap enables polysilicon to effectively absorb photons released from the PN junction avalanche region, especially photons with wavelengths below 750nm or 1100nm. These photons are often a source of noise generated during device operation, and their propagation and reflection can cause optical crosstalk, thereby reducing device performance. In this embodiment, by embedding polysilicon in SiOx, the Si-SiOx-pSi interface formed can effectively absorb these noise photons, reducing their propagation between the photoelectric conversion units 200, thereby significantly reducing optical crosstalk.

[0086] This structure in this embodiment can be integrated with the existing CMOS manufacturing process without the need for additional high-cost equipment investment, and has good process compatibility and scalability.

[0087] In some embodiments of the present disclosure, two adjacent photoelectric conversion units 200 may share the same first trench 310. Figure 1 and Figure 4 As shown. At this time, there is a deep isolation groove between two adjacent photoelectric conversion units 200, forming a single-layer isolation. Of course, two adjacent photoelectric conversion units 200 can also use different first grooves 310, that is, each photoelectric conversion unit 200 has its own independent corresponding first groove 310, as shown in FIG. Figure 2 and Figure 5 At this time, there are two deep isolation trenches between two adjacent photoelectric conversion units 200, forming a double-layer isolation.

[0088] When different first trenches 310 are used between two adjacent photoelectric conversion units 200, the shapes of the different first trenches 310 can be the same or different. Alternatively, the first trenches 310 can have a variety of shapes. For example, the sidewalls of the first trenches 310 can be straight, zigzag, or wavy, but are not limited to these. Any pattern that can be exposed by the mask within the process window is acceptable. The zigzag or wavy design of the sidewalls of the first trenches 310 causes photons to reflect multiple times on the sidewalls of the deep trenches, thereby increasing the propagation path length and the number of reflections. Compared to traditional straight trenches, the zigzag or wavy structure significantly enhances photon scattering and absorption, reducing the likelihood of photons directly propagating to adjacent photoelectric conversion units 200. Furthermore, when photons reflect within the first trenches 310, the polysilicon filling the trenches absorbs these photons. As the number of reflections increases or the reflection path lengthens, the polysilicon's absorption efficiency increases, further reducing optical crosstalk.

[0089] Furthermore, when two adjacent photoelectric conversion units 200 use different first trenches 310, the insulating material (e.g., SiOx) and polysilicon filling the two trenches form a multilayer reflective layer of Si-SiOx-Si-SiOx-Si. When light enters the SiOx from the silicon (Si) substrate 100, due to the difference in refractive index, some of the light is reflected at the Si-SiOx interface. This reflection effect occurs at each interface, gradually weakening the light as it propagates. This effectively blocks the propagation of light, further effectively reducing optical crosstalk. Similarly, when light enters the polysilicon from the SiOx, it is also reflected at the SiOx-pSi interface. This multiple reflection effect further reduces the effective propagation path of light. As a result, light experiences multiple reflections and partial absorption as it propagates between different material interfaces, significantly reducing the propagation intensity of the light and lowering optical crosstalk.

[0090] Optionally, the first trenches 310 of two adjacent photoelectric conversion units 200 may intersect or not intersect. For example, when the first trenches 310 of two adjacent photoelectric conversion units 200 do not intersect, the following may be formed: Figure 5 When the first trenches 310 of two adjacent photoelectric conversion units 200 intersect, a structure as shown in FIG. Figure 7 The structure shown.

[0091] Specifically, in Figure 5 In the illustrated embodiment, the first trenches 310 of different photoelectric conversion units 200 are independent of each other and can form separate closed loops.

[0092] exist Figure 7 In the illustrated embodiment, the first trenches 310 corresponding to two adjacent photoelectric conversion units 200 intersect, that is, the orthographic projections of the first trenches 310 of the two adjacent photoelectric conversion units 200 within the plane of the substrate 100 intersect. Furthermore, the sidewalls of the first trenches 310 are zigzag or wavy, that is, the orthographic projections of the first trenches 310 within the plane of the substrate 100 are zigzag or wavy. In this case, the intersection of the projections of the first trenches 310 corresponding to the two adjacent photoelectric conversion units 200 can form a grid-like pattern. Specifically, in the width direction of the deep trench (perpendicular to the extension direction of the deep trench), in two adjacent photoelectric conversion units 200, the raised portion of the first trench 310 corresponding to one photoelectric conversion unit 200 opposes the recessed portion of the first trench 310 corresponding to the other photoelectric conversion unit 200. In this type of embodiment, the intersection design of the first trenches 310 of two adjacent photoelectric conversion units 200 can effectively reduce the propagation intensity of photons between the two adjacent photoelectric conversion units 200 and reduce optical crosstalk without increasing the space occupied by the isolation structure 300.

[0093] like Figure 3 and Figure 6 As shown, in some embodiments of the present disclosure, the deep trench isolation structure 300a further includes a second trench 320 extending from the surface of the substrate 100 into the substrate 100 and an insulating material and polysilicon filled in the second trench 320. The structure and formation process of the second trench 320 can refer to the first trench 310 described above and will not be described in detail here. In the second trench 320, the insulating material can form a third isolation layer 321, and the polysilicon can form a fourth isolation layer 322. The third isolation layer 321 is coated around the periphery of the fourth isolation layer 322, and the third isolation layer 321 is formed on the sidewalls of the second trench 320.

[0094] The shapes and positions of the second groove 320 and the first groove 310 can be set according to product requirements, process requirements, etc. In some embodiments of the present disclosure, the second groove 320 is arranged around the periphery of the first groove 310, or the second groove 320 intersects the first groove 310.

[0095] like Figure 6 As shown, in one embodiment, the second trench 320 is arranged around the periphery of the first trench 310, that is, the orthographic projection of the second trench 320 on the plane where the substrate 100 is located surrounds the periphery of the orthographic projection of the first trench 310 on the plane where the substrate 100 is located. In this embodiment, the second trench 320 and the first trench 310 are combined to form a multi-layer protection for the photoelectric conversion unit 200, which can further reduce the optical crosstalk between the photoelectric conversion units 200. Figure 8 As shown, in another embodiment, the second groove 320 intersects with the first groove 310. The present disclosure does not limit the intersection position and size.

[0096] In some embodiments of the present disclosure, two adjacent photoelectric conversion units 200 may share the same second trench 320. Figure 3 and Figure 6 As shown. In this case, multiple deep isolation trenches can be provided between two adjacent photoelectric conversion units 200 to form multi-layer isolation. Of course, two adjacent photoelectric conversion units 200 can also use different second trenches 320, that is, each photoelectric conversion unit 200 has its own independent corresponding second trench 320.

[0097] Optionally, the shapes, positions and sharing relationships of the first trench 310 and the second trench 320 between two adjacent photoelectric conversion units 200 can be various. For example, the two photoelectric conversion units 200 can share the same second trench 320 but use different first trenches 310. Figure 6 or Figure 8 shown.

[0098] exist Figure 6In the illustrated embodiment, the first trenches 310 corresponding to the individual photoelectric conversion units 200 do not intersect, forming independent closed loops. The sidewalls of the first trenches 310 are linear. The second trenches 320 are arranged around the periphery of the first trenches 310. The second trenches 320 between the photoelectric conversion units 200 are interconnected to form a grid structure.

[0099] exist Figure 8 In the illustrated embodiment, the first grooves 310 corresponding to the respective individual photoelectric conversion units 200 intersect, and the sidewalls of the first grooves 310 are zigzag-shaped. In two adjacent photoelectric conversion units 200, the raised portion of the first groove 310 corresponding to one photoelectric conversion unit 200 is opposite to the recessed portion of the first groove 310 corresponding to the other photoelectric conversion unit 200. The second groove 320 intersects with the first groove 310, such as the second groove 320 is located at the intersection of the first grooves 310 corresponding to the two adjacent photoelectric conversion units 200. The sidewalls of the second groove 320 are straight. This embodiment can further increase the number of reflections and paths of photons within the grooves, effectively reducing the propagation intensity of photons between the two adjacent photoelectric conversion units 200, and reducing optical crosstalk.

[0100] like Figure 9 and Figure 10 As shown, in some embodiments of the present disclosure, the isolation structure 300 further includes a shallow trench isolation structure 300b, which includes a third trench 330 extending from the surface of the substrate 100 into the substrate 100 and a metal material filled in the third trench 330. The depth of the third trench 330 is less than the depth of the first trench 310, and the orthographic projections of the third trench 330 and the first trench 310 on the plane of the substrate 100 do not overlap.

[0101] The third trench 330 can be formed using a shallow trench isolation process. In semiconductor manufacturing, the shallow trench isolation structure 300b is compatible with the metal electrode manufacturing process, eliminating the need for new equipment. The metal material filled within the third trench 330 can be, but is not limited to, tungsten (W). In this embodiment, the metal material effectively blocks photon crosstalk between the photoelectric conversion units 200, and the shallow trench isolation structure 300b is compatible with existing semiconductor processes. Compared to filling deep trenches with metal, the present disclosure eliminates the need for new equipment and can significantly reduce production costs. Furthermore, the combination of deep and shallow trench structures can significantly reduce optical crosstalk.

[0102] Optionally, the depth of the third trench 330 is greater than the depth of a PN junction formed by the contact between the first semiconductor region 210 and the second semiconductor region 220. For example, the depth of the third trench 330 may be 0.5 μm-1 μm.

[0103] In photoelectric converters such as single-photon avalanche diodes (SPADs), the PN junction is a key region for the avalanche effect and a primary source of photon noise. A significant amount of photon noise is released from this region, blocking the primary photon transmission path. Therefore, the depth of the third trench 330 is greater than that of the PN junction. The metal filled within this trench significantly reduces optical crosstalk along the primary photon transmission path.

[0104] Specifically, in the thickness direction of the substrate 100 , the first semiconductor region 210 is located above the second semiconductor region 220 , and the first semiconductor region 210 is located on the front side of the substrate 100 .

[0105] In the present disclosure, the arrangement of the deep trench isolation structure 300a and the shallow trench isolation structure 300b is not limited, as long as it can meet the product requirements and process requirements and achieve the anti-crosstalk effect. Similarly, two adjacent photoelectric conversion units can use the same third trench 330, or they can use different third trenches 330. Figure 9 As shown, in one embodiment, the deep trench isolation structure 300a includes the above-mentioned first trench 310, and two adjacent photoelectric conversion units use different first trenches 310 and the same third trench 330, which is disposed between the two adjacent first trenches 310. Figure 10 As shown, in another embodiment, the deep trench isolation structure 300a includes a first trench 310 , and two adjacent photoelectric conversion units use the same first trench 310 and different third trenches 330 . The first trench 310 is located between the two third trenches 330 .

[0106] In actual products, the size of the isolation structure 300 between the photoelectric conversion units 200 will affect the photoelectric converter's detection efficiency (PDE) to a certain extent. For example, in a photoelectric conversion unit 200 with a size of 10μm, the isolation structure 300 may need to occupy a space close to 2μm. Although this larger isolation area effectively reduces the crosstalk between the photoelectric conversion units 200, it also leads to a significant reduction in the fill factor (FF) of the device. The fill factor refers to the proportion of the effective photosensitive area (i.e., the absorption area, AA) in the photoelectric conversion unit 200 to the area of ​​the entire photoelectric conversion unit 200. A lower fill factor means that the photosensitive area is relatively small, which affects the device's photon detection efficiency (PDE). To solve this problem, the present disclosure further provides the following solutions:

[0107] like Figure 11 and Figure 12As shown, in some embodiments of the present disclosure, substrate 100 has a concentration gradient region. This concentration gradient region is formed by adjusting the doping concentration within substrate 100. The concentration gradient region is used to guide carriers into the avalanche region formed by the PN junction under high reverse bias. The provision of the concentration gradient region can optimize the transport path of carriers (electrons or holes), allowing more carriers to enter the avalanche region, ensuring the collection efficiency of photogenerated carriers and guaranteeing the detection efficiency of the device. Furthermore, when the device collection efficiency is improved, the area of ​​the PN junction in the AA region can be reduced to a certain extent, slightly relaxing the design and reducing the fringe electric field, while ensuring device reliability and detection efficiency.

[0108] The setting of the gradient concentration region may be set according to the type of the substrate 100 , the doping concentration and type of the first semiconductor region 210 and the second semiconductor region 220 , and the like.

[0109] In one embodiment, substrate 100 is a P-type substrate, achieved by doping the silicon substrate 100 with trivalent ions (such as boron), resulting in a high hole concentration and a low electron concentration. A concentration gradient region can be formed by adjusting the concentration of the doped ions, with the doping concentration gradient varying from low to high from the PN junction to the periphery of substrate 100. In this case, according to minority carrier diffusion theory, minority carriers can diffuse into the avalanche region, ensuring the collection and detection efficiency of photogenerated electrons.

[0110] Alternatively, as Figure 11 As shown, the substrate 100 may form a concentration gradient in the vertical direction (thickness direction of the substrate 100). For example, the first semiconductor region 210 and the second semiconductor region 220 are located on the top of the substrate 100. In the thickness direction of the substrate 100, the doping concentration at the bottom of the substrate 100 is higher, while the doping concentration near the PN junction in the top region is lower. In addition, as shown in FIG. Figure 12 As shown, the substrate 100 may also form a concentration gradient in the lateral direction (within the plane where the substrate 100 is located). For example, within the plane where the substrate 100 is located, the concentration of the region of the substrate 100 close to the PN junction is lower, while the concentration of the region away from the PN junction is higher. Furthermore, the substrate 100 may form a concentration gradient in both the vertical and lateral directions, so that carriers can circle around the photoelectric conversion unit 200 and move closer to the avalanche region, forming a collection efficiency close to 100%. This collection efficiency is also affected by the concentration difference and the gradient change rate. The specific gradient can be set according to actual conditions. The concentration gradient region can be formed by multiple ion implantations, or by high-temperature annealing after ion implantation, using a diffusion mechanism. This disclosure does not limit this.

[0111] like Figures 13 to 16As shown, in some other embodiments of the present disclosure, the photoelectric conversion unit 200 further includes a third semiconductor region 230. The third semiconductor region 230 is configured to guide carriers into the avalanche region formed by the PN junction under high reverse bias. In such embodiments, the third semiconductor region 230 can also optimize the transport path of carriers (electrons or holes), allowing more carriers to enter the avalanche region, thereby ensuring efficient collection of photogenerated carriers and ensuring device detection efficiency.

[0112] The third semiconductor region 230 may be located below the PN junction in the thickness direction of the substrate 100. The third semiconductor region 230 may be formed by ion implantation, and its doping type and doping concentration may be set according to the density of the substrate 100, process conditions, and the like.

[0113] For example, in one embodiment, the second semiconductor region 220 is located below the first semiconductor region 210, and the third semiconductor region 230 is located below the second semiconductor region 220. The third semiconductor region 230 has the same doping type as the first semiconductor region 210, and the doping concentration of the third semiconductor region 230 is lower than the doping concentration of the first semiconductor region 210. Specifically, the substrate 100 has a P-type doping type, the first semiconductor region 210 has an N-type doping type, the second semiconductor region 220 has a P-type doping type, and the third semiconductor region 230 has an N-type doping type. The first semiconductor region 210 is heavily doped, the second semiconductor region 220 is heavily doped, and the doping concentration of the third semiconductor region 230 is lower than the doping concentration of the first semiconductor region 210.

[0114] In this embodiment, the third semiconductor region 230 may be in contact with the second semiconductor region 220. The implanted third semiconductor region 230 can alter the potential of a local region, creating a potential gradient. This allows photogenerated carriers near this region, such as minority electrons, to utilize the weak electric field lines formed by the second semiconductor region 220 (P+) and the third semiconductor region 230 (N), allowing them to more easily drift into the avalanche region of the PN junction formed by the first semiconductor region 210 and the second semiconductor region 220, further enhancing its carrier collection capability.

[0115] In another embodiment, the second semiconductor region 220 is located below the first semiconductor region 210, and the third semiconductor region 230 is located below the second semiconductor region 220. The third semiconductor region 230 has the same doping type as the second semiconductor region 220 and the substrate 100, and the doping concentration of the third semiconductor region 230 is lower than the doping concentration of the second semiconductor region 220 but higher than the doping concentration of the substrate 100. Specifically, the substrate 100 has a P-type doping type, the first semiconductor region 210 has an N-type doping type, the second semiconductor region 220 has a P-type doping type, and the third semiconductor region 230 has a P-type doping type. The first semiconductor region 210 is heavily doped, and the second semiconductor region 220 is heavily doped. The doping concentration of the third semiconductor region 230 is between that of the substrate 100 and the second semiconductor region 220.

[0116] In this embodiment, the injection of the third semiconductor region 230 can change the potential gradient in the local area to optimize the transmission path of photogenerated carriers, allowing more minority carriers (such as electrons) to enter the avalanche region of the PN junction, thereby ensuring the carrier collection capability.

[0117] The specific position and concentration of the third semiconductor region 230 can be set according to actual conditions. For example, the third semiconductor region 230 can be in contact with the second semiconductor region 220, or can be separated from the second semiconductor region 220 by a certain distance, which is not limited in this disclosure. Further, optionally, a first through hole can be provided in the third semiconductor region 230, and the first through hole is arranged opposite to the PN junction formed by the first semiconductor region 210 and the second semiconductor region 220 in the thickness direction of the substrate 100. In addition, the first semiconductor region 210 can also be provided with no through hole. In this case, the orthographic projection of the PN junction formed by the first semiconductor region 210 and the second semiconductor region 220 on the plane of the substrate 100 is located within the orthographic projection of the third semiconductor region 230 on the plane of the substrate 100, but the present invention is not limited thereto.

[0118] When the third semiconductor region 230 is provided with a first through-hole, the size of the first through-hole can be set based on the size of the PN junction, carrier collection requirements, and injection concentration. The first through-hole is disposed directly opposite the PN junction, which helps guide more photogenerated carriers (such as minority carrier electrons) through the first through-hole into the avalanche region of the PN junction, thereby achieving a carrier collection efficiency close to 100%.

[0119] like Figure 17As shown, in some other embodiments of the present disclosure, the first semiconductor region 210 is located above the second semiconductor region 220 in the thickness direction of the substrate 100. The photoelectric conversion unit 200 also includes a first electrode T1, a second electrode T2, and a third electrode T3. The first electrode T1 is connected to the first semiconductor region 210, and the second electrode T2 and the third electrode T3 are both connected to the substrate 100. The first electrode T1 and the second electrode T2 are used to apply a reverse bias voltage to form an avalanche region at the PN junction. The third electrode T3 is located on the side of the second electrode T2 away from the first electrode T1. The third electrode T3 is used to apply a voltage to guide carriers into the avalanche region formed by the PN junction under high reverse bias.

[0120] The voltage applied by the third electrode T3 can be set based on the doping type and concentration of the substrate 100, the first semiconductor region 210, and the second semiconductor region 220. In one embodiment, the substrate 100 is a P-type substrate, the first semiconductor region 210 is heavily N-type doped (N+), and the second semiconductor region 220 is heavily P-type doped (P+). The voltage applied by the first electrode T1 is higher than the voltage applied by the second electrode T2, and the voltage applied by the second electrode T2 is higher than the voltage applied by the third electrode T3. In this embodiment, the voltage of the third electrode T3 is lower than the voltage of the second electrode T2. Due to this lower voltage, the majority carrier holes among the photogenerated carriers are further attracted to the sidewalls of the deep trench isolation structure 300a, forming a hole concentration gradient near the sidewalls. This concentration gradient further generates a potential difference, forming a local electric field near the deep trench isolation structure 300a. This electric field guides the minority carrier electrons among the photogenerated carriers into the central PN junction region, thereby improving electron collection efficiency.

[0121] Optionally, when the deep trench isolation structure 300 a further includes a second trench 320 , the third electrode T3 is connected to the surface of the substrate 100 between the first trench 310 and the second trench 320 .

[0122] The present disclosure further provides a sensing device, comprising the photoelectric converter in any of the above embodiments, wherein the sensing device obtains relevant information by sensing the photoelectric converter to receive an optical signal.

[0123] The sensing device may include a transmitting module and a receiving module, and the transmitting module is used to transmit sensing light pulses to a preset detection space to detect external objects in the detection space. At least part of the sensing light pulses will be returned from the external object and received by the receiving module, and the depth information of the external object can be determined by measuring the flight time of the sensing light pulses in space. The receiving module may include the above-mentioned photoelectric converter, which is capable of generating an electrical signal when irradiated by a light pulse to determine the flight time of the light pulse in space, thereby determining one or more of the proximity information, depth information, or distance information of the external object. Among them, the depth information is used, for example, in 3D modeling, face recognition, autonomous driving, SLAM and other fields, and this application does not limit this.

[0124] The present disclosure also provides an electronic device, comprising the above-mentioned sensing device, the electronic device being configured to execute corresponding functions according to relevant information acquired by sensing electrical signals by the sensing device.

[0125] The corresponding functions include but are not limited to unlocking after identifying the user's identity, payment, launching preset applications, obstacle avoidance, and using deep learning technology to judge the user's emotions and health status after recognizing the user's facial expressions.

[0126] The electronic devices include, but are not limited to, suitable electronic products such as consumer electronics, home electronics, smart mobile tools, and financial terminals. Consumer electronics include, but are not limited to, mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include, but are not limited to, smart door locks, televisions, refrigerators, and wearable devices. Smart mobile tools include, but are not limited to, cars, robots, and unmanned delivery vehicles. Financial terminals include, but are not limited to, ATMs and self-service terminals.

[0127] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A photoelectric converter, characterized in that: include: substrate; A plurality of photoelectric conversion units are formed in the substrate, the photoelectric conversion units comprising a first semiconductor region and a second semiconductor region, wherein a contact interface between the first semiconductor region and the second semiconductor region forms a PN junction; An isolation structure is provided between two adjacent photoelectric conversion units and is used to reduce crosstalk between the two adjacent photoelectric conversion units. The isolation structure includes a deep trench isolation structure, and the deep trench isolation structure includes a first trench extending from the surface of the substrate to the substrate and an insulating material and a semiconductor material filled in the first trench. A first isolation layer and a second isolation layer are provided in the first trench. The first isolation layer is coated on the periphery of the second isolation layer, and the first isolation layer is formed on the sidewall of the first trench. The first isolation layer includes an insulating material, and the second isolation layer includes a semiconductor material.

2. The photoelectric converter according to claim 1, wherein The band gap width of the semiconductor material filled in the first trench is 1.12 eV-1.65 eV.

3. The photoelectric converter according to claim 1, wherein The semiconductor material filled in the first trench includes polysilicon.

4. The photoelectric converter according to claim 1, wherein The isolation structure is provided at the periphery of the first semiconductor region and the second semiconductor region; The deep trench isolation structure further includes a second trench extending from the substrate surface into the substrate and an insulating material and a semiconductor material filled in the second trench; Wherein, the second groove is arranged around the periphery of the first groove, or the second groove intersects with the first groove.

5. The photoelectric converter according to claim 4, wherein: The semiconductor material filled in the second trench includes polysilicon.

6. The photoelectric converter according to claim 4, wherein: The orthographic projection of the first groove and / or the second groove on the plane where the substrate is located is a sawtooth shape or a wave shape.

7. The photoelectric converter according to claim 1, wherein The isolation structure further includes a shallow trench isolation structure, wherein the shallow trench isolation structure includes a third trench extending from the substrate surface into the substrate and a metal material filled in the third trench; The depth of the third groove is smaller than the depth of the first groove, and the orthographic projections of the third groove and the first groove on the plane where the substrate is located do not overlap.

8. The photoelectric converter according to claim 7, wherein: The depth of the third trench is greater than the depth of a PN junction formed by contact between the first semiconductor region and the second semiconductor region.

9. The photoelectric converter according to any one of claims 1 to 8, characterized in that: The substrate has a concentration gradient region formed by adjusting the doping concentration in the substrate. The concentration gradient region is used to guide carriers into an avalanche region formed by the PN junction under a high reverse bias voltage.

10. The photoelectric converter according to claim 9, wherein: The substrate is a P-type substrate, and the doping concentration of the concentration gradient region forms a gradient distribution from low concentration to high concentration from the PN junction to the periphery of the substrate.

11. The photoelectric converter according to any one of claims 1 to 8, characterized in that: The photoelectric conversion unit further includes a third semiconductor region, and the third semiconductor region is used to guide carriers into an avalanche region formed by the PN junction under a high reverse bias voltage.

12. The photoelectric converter according to claim 11, wherein In the thickness direction of the substrate, the third semiconductor region is located below the PN junction, and the second semiconductor region is located below the first semiconductor region; The third semiconductor region has the same doping type as the first semiconductor region, and the doping concentration of the third semiconductor region is lower than the doping concentration of the first semiconductor region; or The third semiconductor region has the same doping type as the second semiconductor region and the substrate, and the doping concentration of the third semiconductor region is lower than the doping concentration of the second semiconductor region and higher than the doping concentration of the substrate.

13. The photoelectric converter according to any one of claims 1 to 8, characterized in that: In the thickness direction of the substrate, the second semiconductor region is located below the first semiconductor region; The photoelectric conversion unit further includes: a first electrode connected to the first semiconductor region; A second electrode and a third electrode, both connected to the substrate; Wherein, the first electrode and the second electrode are used to apply a reverse bias voltage to form an avalanche region at the PN junction; The third electrode is located on a side of the second electrode away from the first electrode, and is used to apply a voltage to guide carriers into an avalanche region formed by the PN junction under a high reverse bias voltage.

14. The photoelectric converter according to claim 13, wherein: When the deep trench isolation structure further includes a second trench, the third electrode is connected to the surface of the substrate between the first trench and the second trench.

15. A sensing device, characterized in that: The photoelectric converter comprises the photoelectric converter according to any one of claims 1 to 14, wherein the sensing device obtains relevant information by sensing the optical signal received by the photoelectric converter.

16. An electronic device, characterized in that: The electronic device comprises the sensing device as claimed in claim 15, and is used to perform corresponding functions according to the relevant information obtained by sensing the electrical signal by the sensing device.

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