Quantum chip and quantum computer
By using a quantum chip structure composed of multiple sub-chips and connecting quantum bits with signal lines and conductive columns, the problem of high-precision processing in quantum chips is solved, and the chip quality and computing stability are improved.
Patent Information
- Application Number
- CN202422638827.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-10-30
AI Technical Summary
When integrating more quantum bits into a quantum chip, the processing technology is difficult to achieve high precision, which affects the quality of the chip.
A quantum chip structure composed of multiple sub-chips is adopted. The electrical connection of quantum bits is achieved by setting a second signal line, a first conductive column and a second conductive column on the interposer wafer, and the quantum bits of adjacent sub-chips are connected using strip lines and couplers to improve processing accuracy and quality.
It improves the processing accuracy and quality of quantum chips, reduces the cost and resource waste caused by quality defects, and enhances computing stability and reliability.
Smart Images
Figure CN223362656U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of quantum computers, in particular to a quantum chip and a quantum computer. Background Art
[0002] Quantum computing is a new computing model that uses the laws of quantum mechanics to control basic information units for calculations. While the basic information unit of classical computing is the classical bit, the basic information unit of quantum computing is the qubit. A classical bit can only exist in one state, either 0 or 1, but based on the quantum mechanical principle of superposition, a qubit can exist in a superposition of multiple possible states. As a result, quantum computing far outperforms classical computing in terms of computational efficiency.
[0003] As the core component of a quantum computer, the performance of the quantum chip determines its overall performance. To achieve better performance, a larger number of qubits must be integrated into the chip. However, when manufacturing a quantum chip, the more qubits are integrated onto a single chip, the more difficult it is to achieve high precision in the processing, thus affecting the chip's quality.
[0004] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Utility Model Content
[0005] The purpose of the present utility model is to provide a quantum chip and a quantum computer. The quantum chip is formed by effectively connecting multiple sub-chips, which can effectively improve the processing accuracy of a single sub-chip and ensure the quality of the quantum chip.
[0006] In order to achieve the above purpose, the present invention provides the following technical solutions:
[0007] The first aspect of the present invention provides a quantum chip, comprising:
[0008] a stripline integrating a plurality of first signal lines;
[0009] A plurality of sub-chips, each of the sub-chips comprising a qubit wafer integrated with quantum bits and an interposer wafer integrated with control lines;
[0010] The interposer wafer is provided with a second signal line, a first conductive column, and a second conductive column; two ends of the first conductive column are electrically connected to the qubit and one end of the second signal line; one end of the second conductive column is electrically connected to the other end of the second signal line;
[0011] The stripline is provided between any two adjacent sub-chips, and both ends of each first signal line in the same stripline are electrically connected to the other end of one of the second conductive pillars in the two adjacent sub-chips, so as to realize the electrical connection between the two quantum bits on the two sub-chips;
[0012] A first coupler is provided on the first signal line.
[0013] The quantum chip as described above, further, the interposer wafer is a multi-layer structure, the first conductive pillar and the second conductive pillar are arranged on the surface of the interposer wafer, and the second signal line is arranged in an inner layer of the interposer wafer;
[0014] The first conductive column is electrically connected to one end of the second signal line through a first conductive hole;
[0015] One end of the second conductive pillar is electrically connected to the other end of the second signal line through a second conductive hole.
[0016] In the quantum chip as described above, further, the control line and the second signal line are located on different layers of the interposer wafer.
[0017] In the quantum chip as described above, further, the strip line includes a dielectric layer, and a plurality of first signal lines are arranged at intervals in the dielectric layer; a first notch is provided at both ends of the strip line, and the first signal line is exposed at the first notch to electrically connect the first signal line to the second conductive column.
[0018] The quantum chip as described above, further, the outer wall of the dielectric layer is provided with a metal shielding layer.
[0019] The quantum chip as described above, further, the qubits on the same qubit wafer are arranged in an array and any two adjacent qubits are coupled via a second coupler;
[0020] A group of quantum bits at the edges of the quantum bit wafers close to each other in any two adjacent sub-chips are electrically connected to the first conductive pillars on the corresponding interposer wafers in a one-to-one correspondence.
[0021] The quantum chip as described above, further, the first coupler and the second coupler both include capacitors.
[0022] The quantum chip as described above, further, the first conductive pillar and the second conductive pillar both comprise indium pillars;
[0023] And / or, both the first conductive via and the second conductive via include through silicon vias.
[0024] The quantum chip as described above, further, multiple sub-chips are arranged in an array.
[0025] A second aspect of the present invention provides a quantum computer, comprising the above-mentioned quantum chip and a quantum computing measurement and control system, wherein the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.
[0026] The beneficial effects of the present utility model are:
[0027] The quantum chip of the present application is composed of multiple sub-chips. When the quantum chip needs to integrate n quantum bits, the n quantum bits can be distributed to multiple sub-chips for separate processing. Then the number of quantum bits on a single sub-chip must be less than n, which can effectively improve the processing accuracy. At the same time, by setting a second signal line, a first conductive column and a second conductive column on the interposer wafer of the sub-chip, since the two ends of the first conductive column are electrically connected to the quantum bit and one end of the second signal line and one end of the second conductive column is electrically connected to the other end of the second signal line, the quantum bit and the second conductive column are electrically connected. Since the two ends of each first signal line in the same strip line are respectively electrically connected to a second conductive column in two adjacent sub-chips and a first coupler is provided on the first signal line, the quantum bits in the two adjacent sub-chips are effectively connected, thereby improving the quality of the quantum chip.
[0028] In addition, when a sub-chip has quality defects, it only needs to be replaced with a sub-chip of qualified quality, which will significantly improve the problems of high cost and waste of resources caused by quality defects.
[0029] The quantum computer provided by the present invention includes the above-mentioned quantum chip and thus has the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 Schematic diagram of the structure of the quantum chip provided in the embodiment of the utility model Figure 1 ;
[0031] Figure 2 Schematic diagram of the structure of connecting any two sub-chips in the quantum chip provided by the embodiment of the utility model Figure 1 ;
[0032] Figure 3 Schematic diagram of the structure of the quantum chip provided in the embodiment of the utility model Figure 2 ;
[0033] Figure 4 Schematic diagram of the structure of connecting any two sub-chips in the quantum chip provided by the embodiment of the utility model Figure 2 ;
[0034] In the accompanying drawings: 10, strip line; 11, first signal line; 12, dielectric layer; 13, metal shielding layer; 20, sub-chip; 21, qubit chip; 23, interposer chip; 231, second signal line; 232, first conductive column; 233, second conductive column; 234, first conductive hole; 235, second conductive hole. DETAILED DESCRIPTION
[0035] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain this application, and cannot be interpreted as limiting this application.
[0036] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.
[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this utility model, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0038] Figure 1 Schematic diagram of the structure of the quantum chip provided in the embodiment of the utility model Figure 1 ; Figure 2 Schematic diagram of the structure of connecting any two sub-chips 20 in the quantum chip provided by the embodiment of the utility model Figure 1 ;like Figure 1 and Figure 2 As shown: This embodiment of the application discloses a quantum chip, including:
[0039] The strip line 10 is integrated with a plurality of first signal lines 11 .
[0040] A plurality of sub-chips 20 , each of which includes a qubit wafer 21 integrated with quantum bits and an interposer wafer 23 integrated with control lines.
[0041] The interposer chip 23 is provided with a second signal line 231, a first conductive column 232 and a second conductive column 233; the two ends of the first conductive column 232 are electrically connected to the quantum bit and one end of the second signal line 231; one end of the second conductive column 233 is electrically connected to the other end of the second signal line 231.
[0042] The strip line 10 is provided between any two adjacent sub-chips 20, and the two ends of each first signal line 11 in the same strip line 10 are electrically connected to the other end of one of the second conductive columns 233 in the two adjacent sub-chips 20, so as to realize the electrical connection between the two quantum bits on the two sub-chips 20.
[0043] A first coupler is provided on the first signal line 11 .
[0044] The quantum chip of the present application is composed of multiple sub-chips 20. When the quantum chip needs to integrate n quantum bits, the n quantum bits can be distributed to multiple sub-chips 20 for separate processing. Then the number of quantum bits on a single sub-chip 20 must be less than n, which can effectively improve the processing accuracy. At the same time, by setting a second signal line 231, a first conductive column 232 and a second conductive column 233 on the interposer wafer 23 of the sub-chip 20, since the two ends of the first conductive column 232 are electrically connected to the quantum bit and one end of the second signal line 231 and one end of the second conductive column 233 is electrically connected to the other end of the second signal line 231, the quantum bit and the second conductive column 233 are electrically connected. Since the two ends of each first signal line 11 in the same strip line 10 are respectively electrically connected to one second conductive column 233 in the two adjacent sub-chips 20 and a first coupler is provided on the first signal line 11, the quantum bits in the two adjacent sub-chips 20 are effectively connected, thereby improving the quality of the quantum chip.
[0045] In addition, when a sub-chip 20 has a quality defect, it only needs to be replaced with a sub-chip 20 of qualified quality, which can significantly improve the problems of high cost and waste of resources caused by the quality defect.
[0046] In this embodiment, the number of sub-chips 20 is not specifically limited, and can be 2, 3, 4, or even more. Figure 1 As shown, the quantum chip includes four sub-chips 20; Figure 3 Schematic diagram of the structure of the quantum chip provided in the embodiment of the utility model Figure 2 ;like Figure 3 As shown, the quantum chip includes five sub-chips 20.
[0047] In this embodiment, the second signal line 231 can be disposed on the surface of the interposer wafer 23 or within it. To improve the quality of the quantum chip, in some implementations of this embodiment, the interposer wafer 23 has a multilayer structure, with the first conductive pillars 232 and the second conductive pillars 233 disposed on the surface of the interposer wafer 23, and the second signal line 231 disposed within the inner layer of the interposer wafer 23. The first conductive pillar 232 is electrically connected to one end of the second signal line 231 via a first conductive via 234; and one end of the second conductive pillar 233 is electrically connected to the other end of the second signal line 231 via a second conductive via 235.
[0048] By arranging the second signal line 231 inside the interposer wafer 23, it is prevented from being interfered with by external signals, and the quality of the electrical connection between adjacent sub-chips 20 is ensured, thereby improving the quality of the quantum chip.
[0049] To further improve the quality of the quantum chip, in some implementations of this embodiment, the control line and the second signal line 231 are located on different layers of the interposer wafer 23. By arranging the control line and the second signal line 231 on different layers of the interposer wafer 23, mutual interference between the control line and the second signal line 231 can be avoided, improving the electrical connection quality between adjacent sub-chips 20, thereby improving the quality of the quantum chip.
[0050] In this embodiment, the quality of the quantum chip can also be improved by improving the quality of the stripline 10. In some implementations of this embodiment, the stripline 10 includes a dielectric layer 12, and multiple first signal lines 11 are arranged at intervals in the dielectric layer 12; both ends of the stripline 10 are provided with a first notch, and the first signal line 11 is exposed at the first notch to electrically connect the first signal line 11 to the second conductive column 233.
[0051] By spacing multiple first signal lines 11 in the dielectric layer 12, mutual interference between the multiple first signal lines 11 is avoided, improving the quality of the stripline 10. The first notch facilitates electrical connection between the first signal lines 11 and the second conductive pillars 233. Furthermore, a metal shielding layer 13 is provided on the outer wall of the dielectric layer 12. This metal shielding layer 13 reduces external signal interference, ensures the quality of the signal transmitted by the first signal lines 11 in the stripline 10, and improves the stability and reliability of the electrical connection, thereby enhancing the quality of the quantum chip.
[0052] In quantum computing, the interactions between quantum bits and the topological structure of the connections are crucial to reducing computational errors and improving computational efficiency and stability.
[0053] In order to further improve the quality of the quantum chip to improve computing efficiency and stability, in some implementations of this embodiment, the quantum bits on the same quantum bit chip 21 are arranged in an array and any two adjacent quantum bits are coupled through a second coupler; a group of quantum bits at the end edges of the quantum bit chips 21 close to each other in any two adjacent sub-chips 20 are electrically connected one-to-one to the first conductive pillars 232 on the corresponding interposer chip 23 to achieve a one-to-one coupling of a group of quantum bits near the end edges of the two sub-chips 20.
[0054] Through the above layout, the topological map of each quantum bit in the quantum chip is the same, which can ensure that the interactions between quantum bits are consistent, which helps to reduce computing errors, improve the stability and reliability of quantum computing, and thus improve the quality of the quantum chip.
[0055] In this embodiment, the first coupler can be provided on the first signal line 11, which not only facilitates arrangement but also can further improve the quality of the quantum chip.
[0056] In this embodiment, in addition to the one-to-one coupling of a group of quantum bits near the end edges in adjacent sub-chips 20, the quantum bits in adjacent sub-chips 20 can also be coupled one-to-one. For example, Figure 4 Schematic diagram of the structure of connecting any two sub-chips 20 in the quantum chip provided by the embodiment of the utility model Figure 2 ;like Figure 4 As shown:
[0057] The surface of the interposer wafer 23 of the sub-chip 20 is provided with three groups of first conductive pillars 232 and three groups of second conductive pillars 233, and the interior of the interposer wafer 23 is provided with three groups of second signal lines 231 of different heights, three groups of first conductive pillars 232 and three groups of second conductive pillars 233; the three groups of first conductive pillars 232 are electrically connected to one end of the three groups of second signal lines 231 through three groups of first conductive holes 234; and one end of the three groups of second conductive pillars 233 is electrically connected to one end of the three groups of second signal lines 231 through three groups of second conductive holes 235.
[0058] The ends of the interposer wafers 23 in each sub-chip 20 that are close to each other are stepped. Each step is used to arrange a group of second conductive pillars 233 . There are three steps, and a total of three groups of second conductive pillars 233 are arranged.
[0059] The stripline 10 connecting adjacent sub-chips 20 includes three signal layers, each of which is provided with a plurality of first signal lines 11 ; stepped notches are provided at both ends of the stripline 10 to expose the first signal lines 11 in each signal layer.
[0060] The three groups of quantum bits on the quantum bit chip 21 are electrically connected to the three groups of first conductive pillars 232 in a one-to-one correspondence, and the three groups of second conductive pillars 233 are electrically connected to the first signal lines 11 on the three signal layers in the strip line 10 in a one-to-one correspondence. A first coupler is provided on each first signal line 11, thereby realizing one-to-one coupling of quantum bits in adjacent sub-chips 20.
[0061] Continue as Figure 4 As shown, dielectric layers 12 are provided on the upper and lower sides of each signal layer of the strip line 10, and a metal shielding layer 13 is provided on the side of the dielectric layer 12 away from the signal layer. This not only avoids mutual interference between signals transmitted on the first signal line 11 between different signal layers, but also avoids interference from external signals, thereby improving the quality of the quantum chip.
[0062] In this embodiment, the type of the first coupler is not specifically limited. In order to further improve the quality of the quantum chip, the first coupler includes a capacitor.
[0063] In this embodiment, the type of the second coupler is not specifically limited. In order to further improve the quality of the quantum chip, the second coupler includes a capacitor.
[0064] In this embodiment, the material of the first conductive column 232 is not specifically limited. In order to further improve the quality of the quantum chip, the first conductive column 232 includes an indium column. Indium is a metal with high electrical conductivity, which can ensure reliable electrical connection between the quantum bit and the second signal line 231, thereby improving the electrical connection performance between the sub-chips 20 to improve the quality of the quantum chip.
[0065] In this embodiment, the material of the second conductive pillar 233 is not specifically limited. In order to further improve the quality of the quantum chip, the second conductive pillar 233 includes an indium pillar. Indium is a metal with high electrical conductivity, which can ensure reliable electrical connection between the first signal line 11 and the second signal line 231, thereby improving the electrical connection performance between the sub-chips 20 and improving the quality of the quantum chip.
[0066] In order to further improve the quality of the quantum chip, in some implementations of this embodiment, the first conductive via 234 and the second conductive via 235 both include through-silicon vias.
[0067] In this embodiment, the arrangement of the plurality of sub-chips 20 is not specifically limited. In order to improve the integration of the quantum chip, in some implementations of this embodiment, the plurality of sub-chips 20 are arranged in an array. For example, Figure 1 As shown in FIG: the number of sub-chips 20 in the quantum chip is 4, and the 4 sub-chips 20 are arranged in a rectangular array. In a specific implementation, the spacing between two adjacent sub-chips 20 can be the same or different. For example, Figure 3As shown: the number of sub-chips 20 in the quantum chip is 5, among which one sub-chip 20 is located at the center position, and the remaining four sub-chips 20 are arranged in a circular array around the center position. In a specific implementation, the distances between the four sub-chips 20 and the center position can be the same or different.
[0068] Based on the same application concept, an embodiment of the present application also proposes a quantum computer, including the above-mentioned quantum chip and a quantum computing measurement and control system, wherein the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.
[0069] The quantum computer of the present application includes the above-mentioned quantum chip, and therefore has the same beneficial effects as the above-mentioned quantum chip, which will not be described in detail here.
[0070] Throughout this specification, references to terms such as "some embodiments" or "examples" indicate that the specific features, structures, materials, or characteristics described in conjunction with such embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, those skilled in the art may combine and reconcile the different embodiments or examples described in this specification.
[0071] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other variation to the technical solution and technical content disclosed herein shall be deemed to fall within the scope of the present invention and remain within the scope of protection of the present invention.
Claims
1. A quantum chip, characterized in that: include: a stripline integrating a plurality of first signal lines; A plurality of sub-chips, each of the sub-chips comprising a qubit wafer integrated with quantum bits and an interposer wafer integrated with control lines; The interposer wafer is provided with a second signal line, a first conductive column, and a second conductive column; two ends of the first conductive column are electrically connected to the quantum bit and one end of the second signal line; one end of the second conductive column is electrically connected to the other end of the second signal line; The stripline is provided between any two adjacent sub-chips, and both ends of each first signal line in the same stripline are electrically connected to the other end of one of the second conductive pillars in the two adjacent sub-chips, so as to realize the electrical connection between the two quantum bits on the two sub-chips; A first coupler is provided on the first signal line.
2. The quantum chip according to claim 1, characterized in that The interposer wafer is a multi-layer structure, the first conductive pillar and the second conductive pillar are arranged on the surface of the interposer wafer, and the second signal line is arranged on the inner layer of the interposer wafer; The first conductive column is electrically connected to one end of the second signal line through a first conductive hole; One end of the second conductive pillar is electrically connected to the other end of the second signal line through a second conductive hole.
3. The quantum chip according to claim 1, characterized in that The control line and the second signal line are located on different layers of the interposer wafer.
4. The quantum chip according to claim 1, characterized in that The stripline includes a dielectric layer, and a plurality of first signal lines are arranged at intervals in the dielectric layer; both ends of the stripline are provided with first notches, and the first signal lines are exposed at the first notches so as to electrically connect the first signal lines to the second conductive pillars.
5. The quantum chip according to claim 4, characterized in that The outer wall of the dielectric layer is provided with a metal shielding layer.
6. The quantum chip according to claim 1, characterized in that The qubits on the same qubit chip are arranged in an array and any two adjacent qubits are coupled via a second coupler; A group of quantum bits at the edges of the quantum bit wafers close to each other in any two adjacent sub-chips are electrically connected to the first conductive pillars on the corresponding interposer wafers in a one-to-one correspondence.
7. The quantum chip according to claim 6, characterized in that The first coupler and the second coupler each include a capacitor.
8. The quantum chip according to claim 2, characterized in that The first conductive pillar and the second conductive pillar both comprise indium pillars; And / or, both the first conductive via and the second conductive via include through silicon vias.
9. The quantum chip according to claim 1, characterized in that The plurality of sub-chips are arranged in an array.
10. A quantum computer, characterized in that: The method comprises a quantum chip as described in any one of claims 1 to 9 and a quantum computing measurement and control system, wherein the quantum chip performs quantum computing tasks based on the measurement and control signals provided by the quantum computing measurement and control system.