Storage chip packaging structure

Abstract

The utility model relates to a memory chip packaging structure. The structure comprises a bonding wire; storing the bare core; the lead frame comprises a base island and outer pins, the storage bare core is installed in the base island, the outer pins are located on the same side, close to the storage bare core, of the lead frame, and lead bonding is achieved between the outer pins and the Pad of the storage bare core through bonding wires. Since the outer pins are located at the same side, close to the storage bare core, of the lead frame, that is, the outer pins of the lead frame are led out from the same side closest to the Flash, compared with a QFN packaging structure in which the outer pins are led out from the periphery, the length of the bonding wire can be shortened, direct connection of the bonding wire is realized, the difficulty of the bonding wire is reduced, and the yield of the bonding wire is improved.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a memory chip packaging structure. Background Art

[0002] NAND Flash (abbreviated as Flash, the same below) is a storage chip used for data storage. It is the mainstream storage medium in the industry. For example, Flash in USB flash drives, SD cards, and SSDs all plays the role of data storage.

[0003] To protect the bare-die Flash, it needs to be packaged. Simply put, packaging involves using polymer or ceramic materials to protect the chip, lead frame, leads, and other components, and shaping them into a specific shape to create a user-usable integrated circuit product or module.

[0004] There are various types of packages, and common types include QFN (quad flat no-lead package), BGA (ball grid array package), TSOP (thin small outline package), etc. Figure 1 The figure shows Flash100 in the QFN package type. In this package type, pins 110 are drawn out from all sides, making it easier to locate the PCB pads when mounting the Flash. In addition, this package uses a single-layer substrate, which has a low package cost. QFN package is one of the mainstream package types for Flash.

[0005] However, the Flash using QFN package type has defects. Since the Pad 210 of the bare core Flash 200 is located on the same side (such as Figure 2 As shown in the figure, the Flash pins of the QFN package type need to be led out from all sides, which will undoubtedly increase the length of the bonding wire between the pad and the pins outside the lead frame, making the bonding wire more difficult and affecting the bonding wire yield. Utility Model Content

[0006] In order to solve or partially solve the problems existing in the related art, the present application provides a memory chip packaging structure, in which the Flash pins under the package can be led out from a single side, and direct bonding wires are realized internally, reducing the difficulty of bonding wires.

[0007] A first aspect of the present application provides a memory chip packaging structure, comprising:

[0008] Bonding wires;

[0009] Storage bare core;

[0010] A lead frame, wherein the lead frame includes a base island and external pins, the storage bare core is installed in the base island, the external pins are located on the same side of the lead frame close to the storage bare core, and the external pins are wire-bonded to the pad of the storage bare core through the bonding wires.

[0011] Furthermore, in one preferred embodiment, the external pin includes a signal external pin and a power external pin, the signal external pin is located on a bottom edge of the lead frame, and the power external pin is located on the lead frame between the storage bare core and the signal external pin.

[0012] Furthermore, in one preferred embodiment, the power external pin extends from one end of the lead frame to the other end of the lead frame.

[0013] Furthermore, in one preferred embodiment, it further comprises a protective adhesive layer, which wraps the bonding wires, the storage bare core and the lead frame.

[0014] Furthermore, in one preferred embodiment, the protective adhesive layer covers the middle portion of the power external pins, so that the ends of the power external pins are exposed.

[0015] Furthermore, in one preferred embodiment, the protective adhesive layer covers portions of the power supply external pins, so that the power supply external pins are exposed at intervals.

[0016] Furthermore, in one preferred embodiment, the protective adhesive layer does not cover one side surface of the base island, and the one side surface of the base island serves as an external pin of the lead frame.

[0017] Furthermore, in one preferred embodiment, the protective adhesive layer does not cover an edge portion of one side surface of the base island, and the edge portion of one side surface of the base island serves as an external pin of the lead frame.

[0018] Furthermore, in one preferred embodiment, the protective adhesive layer does not cover a central portion of one side surface of the base island, and the central portion of one side surface of the base island serves as an external pin of the lead frame.

[0019] Furthermore, in one preferred embodiment, the protective adhesive layer is provided with an indicator portion, and the indicator portion is located at one of the corners of the protective adhesive layer.

[0020] The technical solution of the present application includes: bonding wires; a memory die; and a lead frame. The lead frame includes a base island and external pins. The memory die is mounted in the base island, and the external pins are located on the same side of the lead frame as the memory die. The external pins are wire-bonded to the pad of the memory die via bonding wires. Because the external pins are located on the same side of the lead frame as the memory die, that is, the external pins of the lead frame are drawn from the same side closest to the Flash memory, compared to a QFN package structure with external pins extending from all four sides, the present application can shorten the length of the bonding wires and achieve direct wire bonding, reducing the difficulty of wire bonding and improving the wire bonding yield.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present application will become more apparent by describing in more detail exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0023] Figure 1 It is a schematic diagram of the structure of the QFN package type Flash in the prior art;

[0024] Figure 2 It is a structural diagram of the bare core Flash of the prior art;

[0025] Figure 3 1 is a schematic structural diagram of a memory chip packaging structure according to the first embodiment of the present application (before packaging);

[0026] Figure 4 1 is a schematic structural diagram of a memory chip packaging structure according to a second embodiment of the present application (before packaging);

[0027] Figure 5 1 is a schematic structural diagram of a memory chip packaging structure according to a third embodiment of the present application (after packaging);

[0028] Figure 6 1 is a schematic structural diagram of a memory chip packaging structure according to a fourth embodiment of the present application (after packaging);

[0029] Figure 7 1 is a schematic structural diagram of a memory chip packaging structure according to a fifth embodiment of the present application (after packaging);

[0030] Figure 8 1 is a structural diagram of a memory chip packaging structure according to a sixth embodiment of the present application (after packaging);

[0031] Figure 9This is a structural schematic diagram of the memory chip packaging structure shown in this application from another perspective (after packaging). DETAILED DESCRIPTION

[0032] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although the accompanying drawings illustrate embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0033] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0034] In the description of this application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0035] Unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," and the like should be interpreted broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0036] In the related art, since the Pads of the bare core Flash are all located on the same side (such as Figure 2 As shown in the figure, the Flash pins of the QFN package type need to be led out from all sides, which will undoubtedly increase the length of the bonding wire between the pad and the pins outside the lead frame, making the bonding wire more difficult and affecting the bonding wire yield.

[0037] Therefore, in order to solve the above technical problems, the present application provides a memory chip packaging structure, in which the Flash pins under the package can be led out from one side, and direct bonding wires are realized internally, reducing the difficulty of bonding wires.

[0038] The technical solution of this application is described in detail below with reference to the accompanying drawings.

[0039] Figure 3 FIG2 is a schematic structural diagram of a memory chip packaging structure in one embodiment of the present application.

[0040] See also Figure 3 A memory chip packaging structure 300 includes: a bonding wire 310, a memory bare core 320 and a lead frame 330.

[0041] It should be noted that the bonding wire 310 is the core component for realizing the electrical connection between the storage bare core 320 and the lead frame 330. In this embodiment, the bonding wire 310 is made of a metal material such as gold. The bonding wire 310 made of gold has good electrical conductivity and can improve the connection stability between the storage bare core 320 and the lead frame 330. The storage bare core 320 is Flash. As the name suggests, the bare core is an unpackaged memory chip. The storage bare core 320 is provided with a number of Pads 321. Pads 321 are the pins of the storage bare core 320. External devices or equipment can realize electrical connection with the storage bare core 320 through the Pads, thereby completing data interaction with the storage bare core 320. For most Flash on the market, the Pad positions of the Flash are all located on the same side (such as Figure 2 This is due to the design architecture and manufacturing process of Flash.

[0042] The lead frame 330 is the basic structural component of the memory chip package structure 300. It mainly provides physical support for the memory die 320 and also serves to connect the internal and external circuits and conduct heat. In this embodiment, the lead frame 330 includes a base island 331 and external pins 332. The memory die 320 is mounted in the base island 331. The external pins 332 are located on the same side of the lead frame 330 as the memory die 320. The external pins 332 are wire-bonded to the pads 321 of the memory die 320 via bonding wires 310. With the above structure, since the external pins 332 are located on the same side of the lead frame 330 as the memory die 320, that is, the external pins 332 of the lead frame 320 are led out from the same side closest to the Flash memory, compared to the QFN package structure in which the external pins 332 are led out from all sides, the present application can shorten the length of the bonding wires 310 and achieve direct bonding, reducing the bonding difficulty and improving the bonding yield. The "straight-through" mentioned here means that the bonding wire distance between the Flash Pad 321 and the external pin 332 is the shortest, which can effectively reduce the cost of the bonding wire 310. That is, the packaging structure of this embodiment not only improves the bonding wire yield, but also has obvious advantages in packaging cost.

[0043] It should be emphasized that this application is a brand-new packaging structure for the QFN package type of Flash. The full English name of the QFN package is QuadFlatNo-LeadsPackage, and the full Chinese name is Square Flat No-Lead Package, where "square" represents that the external pins of the package are led out from all sides. The packaging structure of this application is abbreviated as SFN in English, and the full English name is SingleFlat No-Leads Package, and the full Chinese name is Single-sided Flat No-Lead Package, where "Single" represents that the external pins of the package of this application are led out from a single side. From the above comparison, it can be seen that the most essential difference between the packaging structure of this application and the QFN packaging structure in the prior art is.

[0044] See also Figure 4 Furthermore, in one preferred embodiment, the external pin 332 includes a signal external pin 332a and a power external pin 332b, the signal external pin 332a is located at a bottom edge of the lead frame 330, and the power external pin 332b is located at a position on the lead frame 330 between the storage bare core 320 and the signal external pin 332a.

[0045] It should be noted that the external pins 332 are primarily classified into two types: signal pins 332a and power pins 332b. Signal pins 332a are used to transmit signals such as commands, addresses, and data, thereby controlling the operation of the memory die 320. Common Flash signal pins 332a include ALE, CLE, CMD, DAT, CE, and R / B. The functional definitions of these signal pins 332a vary depending on the Flash memory and are not specifically defined in this application. There are multiple signal pins 332a. Power pins 332b provide voltage. Common Flash power pins 332b include VCCQ and VCC. VCCQ provides core power to the Flash memory, while VCC provides input power to the Flash memory. These two types of power are the most common, and Flash memory must have at least one power pin 332b.

[0046] See also Figure 4 Furthermore, in one preferred embodiment, the power external pin 332 b extends from one end of the lead frame 330 to the other end of the lead frame 330 .

[0047] It should be noted that, since the distribution position of the power pad (power pad is the pad that transmits voltage signal) of the storage core 320 in the same storage core 320 is random, for example, the 2nd, 6th, 10th and 20th pads of the storage core 320 are all power pads, and the rest are signal pads (signal pad is the pad that transmits command, address and data), the power pad span area of ​​the storage core 320 is long, and the power external pin 332b cannot be arranged according to the storage core 320. The design is based on the distribution position of the power pads, which is defined by the Flash manufacturer and cannot be customized by the Flash buyer or user. This will cause two important problems. First, when bonding the storage die 320, the length of the bonding wire 310 of the 20th pad of the storage die 320 will be much longer than the length of the bonding wire 310 of the 2nd pad. The longer the bonding wire 310, the higher the defective rate. Second, the problem of wire crossing is prone to occur. The more wires that cross, the higher the defective rate.

[0048] Therefore, in order to solve the above technical problems, in this embodiment, the length of the power external pin 322b is designed to extend from one end of the lead frame 330 to the other end, so that no matter where the power pad of the storage bare core 320 is located, the nearest power external pin 332b can be selected for bonding, that is, straight-through bonding is achieved, which greatly reduces the probability of bonding wires crossing and is of great help to the bonding yield.

[0049] See also Figure 9 Furthermore, in one preferred embodiment, a protective adhesive layer 340 is further included, and the protective adhesive layer 340 wraps the bonding wire 310 , the storage bare core 320 and the lead frame 330 .

[0050] It should be noted that the protective adhesive layer 340 protects the bonding wires 310 , the storage die 320 and the lead frame 330 , preventing impurities from entering the interior and affecting product stability and wire bonding yield.

[0051] See also Figure 5 Furthermore, in one preferred embodiment, the protective adhesive layer 340 covers the middle portion of the power external pin 332b, so that the end of the power external pin 332b is exposed.

[0052] It should be noted that since the power external pin 332b extends from one end to the other within the lead frame 330, after production, it is not necessary to expose a significant portion of the power external pin 332b. This facilitates the alignment of the memory chip with the PCB pads for placement. Therefore, in this embodiment, when the protective adhesive layer 340 is formed during the sealing stage, the power external pin 332b can be specially treated so that the protective adhesive layer 340 only covers the middle portion of the power external pin 332b, leaving the end of the power external pin 332b exposed. In this way, during placement, only the end of the power external pin 332b needs to be soldered to achieve an electrical connection.

[0053] See also Figure 6 Furthermore, in one preferred embodiment, the protective adhesive layer 340 covers portions of the power external pins 332b, so that the power external pins 332b are exposed at intervals.

[0054] It should be noted that, in addition to exposing the ends of the power external pins 332b, other methods can be used to specifically treat the power external pins 332b. In this embodiment, when the protective adhesive layer 340 is formed during the sealing stage, it covers several portions of the power external pins 332b, leaving the power external pins 332b exposed at intervals. Compared to exposing the ends, this method provides greater connection stability, but it increases the overall difficulty of patching. The protective adhesive layer 340 of the power external pins 332b can be specially treated according to actual needs.

[0055] See also Figure 6 Furthermore, in one preferred embodiment, the protective adhesive layer 340 does not cover one side of the base island 331 , and the one side of the base island 331 serves as an external pin of the lead frame 330 .

[0056] It should be noted that a ground pin is essential for any chip. In this embodiment, as in the prior art, the ground pin is provided on a side surface of the base island 331 of the lead frame 330. Due to the large area of ​​the base island 331, the ground pin is located there. This not only provides stable heat dissipation for the memory die 320, but also allows the ground pin to be designed sufficiently large, thereby improving the overall grounding stability of the memory die 320. Of course, in other embodiments, the ground pin can also be extended from the signal external pin 332a.

[0057] See also Figure 7 Furthermore, in one preferred embodiment, the protective adhesive layer 340 does not cover an edge portion of one side of the base island 331 , and the edge portion of one side of the base island 331 serves as an external pin of the lead frame 330 .

[0058] It should be noted that, in this embodiment, the protective adhesive layer 340 does not cover the edge portion of one side of the base island 331, which is equivalent to a special treatment of one side of the base island 331, so that the edge portion of one side of the base island 331 is exposed. The exposed edge portion serves as the external pin of the lead frame 330, which can facilitate the patch operation of the memory chip.

[0059] See also Figure 8 Furthermore, in one preferred embodiment, the protective adhesive layer 340 does not cover the central portion of one side of the base island 331 , and the central portion of one side of the base island 331 serves as an external pin of the lead frame 330 .

[0060] It should be noted that, in this embodiment, the protective adhesive layer 340 does not cover the central portion of one side surface of the base island 331, which is equivalent to a special treatment of one side surface of the base island 331, so that the central portion of one side surface of the base island 331 is exposed. The exposed central portion serves as the external pin of the lead frame 330, which can also facilitate the patch operation of the memory chip.

[0061] See also Figure 9 Furthermore, in one preferred embodiment, the protective rubber layer 340 is provided with an indicator portion 341 , and the indicator portion 341 is located at one of the corners of the protective rubber layer 340 .

[0062] It should be noted that the indicator portion 341 serves as a prompt, and is used to mark which external pin of the memory chip is the first pin.

[0063] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the description are not necessarily required for this application. In addition, it is understood that the steps in the method of the embodiment of the present application can be adjusted in sequence, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0064] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory chip packaging structure, characterized in that: include: Bonding wires; Storage bare core; A lead frame, wherein the lead frame includes a base island and external pins, the storage bare core is installed in the base island, the external pins are located on the same side of the lead frame close to the storage bare core, and the external pins are wire-bonded to the pad of the storage bare core through the bonding wires.

2. The memory chip packaging structure according to claim 1, wherein: The external pins include signal external pins and power external pins. The signal external pins are located on a bottom edge of the lead frame, and the power external pins are located on the lead frame between the storage bare core and the signal external pins.

3. The memory chip packaging structure according to claim 2, wherein: The power external pin extends from one end of the lead frame to the other end of the lead frame.

4. The memory chip packaging structure according to claim 3, wherein: It also includes a protective adhesive layer, which wraps the bonding wires, the storage bare core and the lead frame.

5. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer covers the middle portion of the power external pins, so that the ends of the power external pins are exposed.

6. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer covers several parts of the power supply external pins, so that the power supply external pins are exposed at intervals.

7. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer does not cover one side surface of the base island, and the one side surface of the base island serves as an external pin of the lead frame.

8. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer does not cover an edge portion of one side surface of the base island, and the edge portion of one side surface of the base island serves as an external pin of the lead frame.

9. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer does not cover a central portion of one side surface of the base island, and the central portion of one side surface of the base island serves as an outer pin of the lead frame.

10. The memory chip packaging structure according to claim 4, wherein: The protective adhesive layer is provided with an indicator portion, and the indicator portion is located at one of the corner positions of the protective adhesive layer.

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