Laser irradiation device

Abstract

The laser irradiation apparatus includes: an optical system including a light source emitting laser light; a pattern mask including a plurality of patterns on which the laser light emitted from the optical system is incident and through which the laser light passes; and a moving module that moves the pattern mask in a direction perpendicular to the substrate while irradiating the metal layer with the laser light to control a region in which the metal layer is irradiated with the laser light. The plurality of pad electrodes and the plurality of bump electrodes are electrically connected through the plurality of metal patterns.

Description

Technical Field

[0001] The disclosure herein relates to a laser irradiation apparatus and a method of manufacturing a display device using the same, and more particularly, to a laser irradiation apparatus having improved reliability and a method of manufacturing a display device using the same. Background Art

[0002] Electronic devices such as smartphones, tablet computers, laptop computers, car navigation systems, and smart TVs are being developed. These electronic devices are provided with display devices for providing information.

[0003] Various types of display devices are being developed to satisfy user experience / user interface ("UX / UI") of users. Display devices providing a wide display area and a relatively small non-display area are being developed.

[0004] Generally speaking, laser devices are used in the manufacturing of electrical and electronic devices, such as display devices. Specifically, laser devices can be used for drilling, cutting, cleaning, marking, scanning, crystallizing, and surface modification of workpieces. To this end, a technology is needed that can easily adjust the shape, size, and energy density of the laser beam generated by a laser device. Utility Model Content

[0005] The present disclosure provides a laser irradiation apparatus configured to reduce damage to a substrate during a patterning process and a method of manufacturing a display device using the laser irradiation apparatus.

[0006] Embodiments of the present disclosure provide a laser irradiation device for irradiating a metal layer with laser light to form a plurality of metal patterns spaced apart in a first direction. The metal layer overlaps a plurality of pad electrodes disposed on a substrate and bump electrodes, each disposed to correspond to the plurality of pad electrodes, and has a non-uniform thickness. The laser irradiation device includes: an optical system including a light source that emits laser light; a pattern mask including a plurality of patterns, the laser light emitted from the optical system being incident on the plurality of patterns and passing through the plurality of patterns; and a moving module that moves the pattern mask in a direction perpendicular to the substrate while irradiating the metal layer with laser light to control the area of ​​the metal layer in which the laser light is irradiated. The plurality of pad electrodes and the plurality of bump electrodes are electrically connected via the plurality of metal patterns.

[0007] In an embodiment, the plurality of patterns may be arranged in the first direction and may not overlap with the plurality of metal patterns.

[0008] In an embodiment, the plurality of patterns may be formed to be inclined at a predetermined angle with respect to the plurality of pad electrodes in a plan view.

[0009] In an embodiment, the plurality of patterns may include first and second sub-patterns spaced apart in a second direction crossing the first direction.

[0010] In an embodiment, the first sub-pattern and the second sub-pattern may be alternately arranged in the first direction in a plan view.

[0011] In an embodiment, a plurality of open areas may be defined between two adjacent metal patterns among the plurality of metal patterns.

[0012] In an embodiment, the plurality of patterns may overlap with the plurality of open areas in a plan view.

[0013] In embodiments, a pattern mask may be disposed between the optical system and the substrate.

[0014] In an embodiment, the pattern mask may be disposed in parallel with the substrate.

[0015] In an embodiment, the laser light emitted from the light source may have a wavelength of about 200 nanometers (nm) to about 400 nm.

[0016] In an embodiment, the laser light emitted from the optical system may include a laser beam.

[0017] In an embodiment, the laser irradiation apparatus may further include an optical lens between the substrate and the pattern mask.

[0018] In an embodiment, the optical lens may include a chromatic aberration lens.

[0019] In an embodiment of the present disclosure, a method for manufacturing a display device includes: providing a plurality of pad electrodes and a plurality of bump electrodes, wherein the plurality of pad electrodes are provided on a base layer and arranged in a first direction, and the plurality of bump electrodes are provided on the plurality of pad electrodes and overlap each of the plurality of pad electrodes in a plan view; providing a metal layer having a non-uniform thickness on the plurality of pad electrodes and the plurality of bump electrodes; irradiating the metal layer with laser light using a laser irradiation device including a pattern mask, the pattern mask including a plurality of patterns; and forming a plurality of metal patterns that overlap the plurality of pad electrodes and the plurality of bump electrodes and are spaced apart in the first direction. The plurality of pad electrodes and the plurality of bump electrodes are electrically connected via the plurality of metal patterns.

[0020] In an embodiment, irradiating the metal layer with the laser may include patterning the metal layer overlapping a region between two adjacent pad electrodes among the plurality of pad electrodes in a plan view.

[0021] In an embodiment, the patterning of the metal layer may include irradiating the metal layer overlapping a region between two adjacent pad electrodes among the plurality of pad electrodes in a plan view with a patterned laser through a pattern mask.

[0022] In an embodiment, patterning the metal layer may include moving the pattern mask in a direction away from the base layer by a moving module.

[0023] In an embodiment, while the pattern mask moves, an irradiation area of ​​the laser light patterned by passing through the pattern mask may gradually increase, and a thickness of the metal layer may gradually decrease.

[0024] In an embodiment, a plurality of open regions may be defined between two adjacent metal patterns among the plurality of metal patterns, and the plurality of open regions may overlap with the plurality of patterns in a plan view.

[0025] In an embodiment, the method may further include planarizing the metal layer using a laser irradiation apparatus including a planarization mask before forming the plurality of metal patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0027] Figure 1 is a perspective view of an embodiment of an electronic device according to the present disclosure;

[0028] Figure 2 is an exploded perspective view of an embodiment of an electronic device according to the present disclosure;

[0029] Figure 3 It is along Figure 2 A cross-sectional view of the display device taken along line II';

[0030] Figure 4 is a simplified cross-sectional view of an embodiment of a display module according to the present disclosure;

[0031] Figure 5 is a plan view of an embodiment of a display panel according to the present disclosure;

[0032] Figure 6 is a cross-sectional view of an embodiment of a display module according to the present disclosure;

[0033] Figure 7A is a view enlarging a portion of an embodiment of a display device according to the present disclosure;

[0034] Figure 7B It is along Figure 7A A cross-sectional view of the base layer taken along line II-II';

[0035] Figure 8is a perspective view of an embodiment of a laser irradiation device according to the present disclosure;

[0036] Figure 9 It shows Figure 8 a cross-sectional view of components of the optical system shown in ;

[0037] Figure 10A yes Figure 8 A plan view of the pattern mask shown in ;

[0038] Figure 10B and Figure 10C It shows Figure 8 A plan view of another embodiment of the pattern mask shown in FIG;

[0039] Figures 11A to 11C It shows Figure 8 A view of the irradiated target shown in ;

[0040] Figure 12A is a perspective view of an embodiment of a laser irradiation device according to the present disclosure;

[0041] Figure 12B yes Figure 12A A plan view of the opening mask shown in ;

[0042] Figure 12C It is along Figure 12A a cross-sectional view taken along line V-V'; and

[0043] Figures 13A to 15B is a view illustrating an embodiment of a process of forming a metal pattern using a laser irradiation apparatus according to the present disclosure. DETAILED DESCRIPTION

[0044] The present disclosure can be modified into many alternative forms, and thus illustrative embodiments will be illustrated in the drawings and described in detail. However, it should be understood that it is not intended to limit the present disclosure to the particular forms disclosed, but is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure.

[0045] It will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to" or "coupled to" another element, it can be directly disposed on, directly connected to or directly coupled to the other element, or intervening elements may be disposed therebetween.

[0046] The same reference numerals refer to the same elements. In addition, in the drawings, the thickness, ratio and size of elements are exaggerated for the effective description of the technical contents.

[0047] The term "and / or" includes all combinations of one or more that the relevant configurations can define.

[0048] Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the teachings of the present disclosure. Singular forms are intended to also include plural forms, unless the context clearly indicates otherwise.

[0049] In addition, terms such as "below," "lower," "above," and "upper" are used to describe the relationship of the configurations shown in the drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0050] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0052] It will also be understood that when used in this specification, the terms “comprises” or “comprising” specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of an embodiment of an electronic device according to the present disclosure. Figure 2 is an exploded perspective view of an embodiment of an electronic device according to the present disclosure. Figure 3 It is along Figure 2 1-1' is a cross-sectional view of the display device taken along line II'.

[0055] refer to Figure 1The electronic device ED in the embodiment of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0056] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may be an area where an image IM is displayed, and the non-display area NDA may be an area where the image IM is not displayed. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the shapes of the display area DA and the non-display area NDA may be modified.

[0057] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The front and rear surfaces of each member are distinguished from each other with respect to the third direction DR3. In addition, as used herein, "in a plan view" can be defined as a state in which the display device DD is viewed from the third direction DR3.

[0058] In an embodiment of the present disclosure, the electronic device ED may be a foldable electronic device that is foldable about a folding axis. The folding axis may be parallel to the first direction DR1 or the second direction DR2, and the folding region may be defined within a portion of the display area DA. The electronic device ED may be folded inwardly so that portions of the display area DA face each other, or may be folded outwardly so that portions of the display area DA face away from each other.

[0059] like Figure 2 As shown in FIG, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM and a housing HM. Figure 2 The electronic device ED is briefly shown, and may further include a mechanical structure (eg, a hinge) designed to control the operation (eg, folding or rolling) of the display device DD.

[0060] The display device DD generates an image IM and detects external input. The display device DD includes a window WM, an upper member UM, a display module DM, a lower member LM, a flexible circuit board FCB, and a driver chip DIC. The upper member UM comprises a member disposed above the display module DM, and the lower member LM comprises a member disposed below the display module DM.

[0061] The window WM provides a front surface of the electronic device ED and includes a transmissive area TA and a bezel area BZA. Figure 1The display area DA and non-display area NDA of the display surface DS shown in FIG are defined by a transmissive area TA through which an image IM passes, and a bezel area BZA covering a structure / member disposed below the window WM.

[0062] The display module DM includes Figure 1 , and the display area DA and the non-display area NDA shown in FIG. As used herein, the phrase “area / portion corresponding to an area / portion” indicates that they overlap and are not limited to the same area.

[0063] The pad area PA is provided on one side of the non-display area DM-NDA. The pad area PA is an area electrically bonded (or electrically connected) to the flexible circuit board FCB, which will be described later. In the illustrated embodiment, the pad area PA is defined on the rear surface of the display module DM.

[0064] The display module DM has a substantially quadrilateral shape. The term "substantially quadrilateral shape" herein encompasses mathematically defined quadrilateral shapes as well as quadrilateral-like shapes that can be perceived by a user as quadrilaterals. In embodiments, for example, the substantially quadrilateral shape may include a quadrilateral shape having rounded corners. Furthermore, the substantially quadrilateral shape need not be limited to straight edges of the display module DM, and the edges may include curved areas.

[0065] The upper member UM may include a protective film or an optical film. The optical film may include a polarizer and a retarder to reduce reflection of external light. The lower member LM may include a protective film to protect the display module DM, a support member to support the display module DM, and a digitizer. A detailed description of the upper member UM and the lower member LM will be provided below.

[0066] The flexible circuit board FCB is disposed below the display module DM. The flexible circuit board FCB may be bonded to the rear surface of the display module DM. The flexible circuit board FCB connects the display module DM and the main circuit board MCB (refer to FIG. Figure 3 ) electrical connection. The flexible circuit board FCB includes at least one insulating layer and at least one conductive layer. The conductive layer may include multiple signal lines.

[0067] The driving chip DIC may be disposed (eg, mounted) on the flexible circuit board FCB. The driving chip DIC may include a driving circuit for driving pixels of the display module DM, such as a data driving circuit. Figure 2 A structure is shown in which the driver chip DIC is disposed (eg, mounted) on the flexible circuit board FCB, but the present disclosure is not limited thereto. In an embodiment, for example, the driver chip DIC may be disposed (eg, mounted) on the display module DM or the main circuit board MCB.

[0068] The electronic module EM may include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, and an external interface module. The electronic module EM may include a main circuit board MCB, and the modules may be disposed (e.g., mounted) on the main circuit board MCB or may be electrically connected to the main circuit board MCB via a flexible circuit board FCB. The electronic module EM is electrically connected to a power supply module PSM.

[0069] Although not shown separately, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives optical signals. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may capture external images through a partial area of ​​the display module DM.

[0070] Figure 2 The housing HM shown in FIG is coupled to the display device DD (particularly the window WM) to accommodate other modules. The housing HM is shown as having a single main body shape, but is not limited thereto. The housing HM may include multiple parts (e.g., side edge parts and a bottom part) coupled to each other.

[0071] refer to Figure 3 The window WM may include a base substrate BS and a frame pattern BM disposed on the lower surface of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin-film glass substrate, a protective film disposed on the thin-film glass substrate, and an adhesive layer bonding the thin-film glass substrate and the protective film.

[0072] The frame pattern BM is a color light blocking film and can be formed, for example, by a coating method. The frame pattern BM may include a base material and a dye or pigment mixed with the base material. Figure 1 The non-display area NDA shown in Figure 2 . The frame pattern BM may be provided on the lower surface of the base substrate BS. When the base substrate BS has a multi-layer structure, the frame pattern BM may be provided between interfaces defined by the multiple layers. In an embodiment, for example, the frame pattern BM may be provided between the thin film glass substrate and the protective film. Although not shown separately, the window WM may further include at least one of a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer on the upper surface of the base substrate BS.

[0073] The upper member UM may include an upper film. The upper film may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, cellulose triacetate, polymethyl methacrylate, or polyethylene terephthalate.

[0074] The upper film can absorb external shocks applied to the front surface of the display device DD. In an embodiment of the present disclosure, the display module DM may include a color filter as an anti-reflection member instead of a polarizing film. Including a polarizing film as an anti-reflection member may reduce the frontal impact strength of the display device DD. Therefore, the upper film can compensate for the reduced impact strength due to the application of the color filter.

[0075] Upper component UM and border area BZA (reference Figure 2 ) and the transmissive area TA (reference Figure 2 ) overlap. The upper member UM may overlap only a portion of the frame area BZA. A portion of the frame pattern BM may be exposed from the upper member UM. In an embodiment of the present disclosure, the upper member UM may not be provided. In an embodiment of the present disclosure, the upper member UM may be replaced with an optical film including a polarizer and a retarder.

[0076] Although not shown, an adhesive layer bonding the upper member UM and the window WM may be further included between the upper member UM and the window WM. The adhesive layer may be a pressure-sensitive adhesive film ("PSA") or an optically clear adhesive ("OCA").

[0077] The display module DM is disposed below the upper member UM. The display module DM overlaps the bezel area BZA and the transmissive area TA. The display module DM may cover the entire upper member UM in the bezel area BZA. In a plan view, the side surfaces of the display module DM may be aligned with the side surfaces of the upper member UM, and the corners of the display module DM may be aligned with the corners of the upper member UM.

[0078] The pad area PA of the display module DM may overlap with the upper member UM in the bezel area BZA. The portion of the display module DM corresponding to the pad area PA may be bonded to the lower surface of the upper member UM via an adhesive layer. The pad area PA overlaps with the upper member UM, and the portion of the display module DM overlapping with the pad area PA is bonded to the upper member UM. Therefore, when the flexible circuit board FCB is bonded to the pad area PA, the upper member UM can adequately support the pad area PA.

[0079] The lower member LM may include a lower film PF and a cover panel CP. In an embodiment of the present disclosure, the lower member LM may further include a support plate and a digitizer.

[0080] The lower film PF may expose the pad area PA of the display module DM. The lower film PF may have an area size smaller than that of the display module DM. In an embodiment, for example, the lower film PF may overlap only with the display area DM-DA of the display module DM. An opening area PF-OP corresponding to the non-display area DM-NDA may be defined in the lower film PF. In an optional embodiment, the lower film PF may have a size substantially corresponding to that of the display module DM. In this case, an opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0081] The lower film PF may expose the pad area PA. The lower film PF may have an area smaller than that of the display module DM. In an embodiment, for example, the lower film PF may overlap only with the display area DA. The lower film PF may have an area substantially the same as that of the display module DM. An opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0082] The cover panel CP may be disposed below the lower film PF. The cover panel CP may increase resistance to compression forces caused by external pressure. Thus, the cover panel CP may be used to prevent deformation of the display module DM. The cover panel CP may include a flexible plastic material such as polyimide or polyethylene terephthalate. In addition, the cover panel CP may be a colored film with a relatively low light transmittance. The cover panel CP may absorb light incident from the outside. In an embodiment, for example, the cover panel CP may be a black synthetic resin film. When the display device DD is observed from the upper side of the window WM, components disposed below the cover panel CP may not be observed by the user.

[0083] Although not shown, a support plate may also be provided below the cover panel CP. The support plate may include a metal material having relatively high strength. The support plate may include a fiber-reinforced composite material. The support plate may include reinforcing fibers disposed inside the matrix portion. The reinforcing fibers may be carbon fibers or glass fibers. The matrix portion may include a polymer resin. The matrix portion may include a thermoplastic resin. In an embodiment, for example, the matrix portion may include a polyamide-based resin or a polypropylene-based resin. In an embodiment, for example, the fiber-reinforced composite material may be a carbon fiber reinforced plastic ("CFRP") or a glass fiber reinforced plastic ("GFRP").

[0084] The main circuit board MCB can be arranged on the lower surface of the flexible circuit board FCB. The flexible circuit board FCB may include an insulating film and conductive wires arranged (e.g., mounted) on the insulating film. The main circuit board MCB may include signal lines and electronic components, which are not shown in the figure. The electronic components can be connected to the signal lines and thus can be electrically connected to the display module DM. The electronic components generate various electrical signals, such as signals for generating images or signals for sensing external inputs, or perform processing on the sensed signals. A single main circuit board MCB or three or more main circuit boards MCB can be provided corresponding to each electrical signal for generation and processing, but are not limited to a specific embodiment.

[0085] Although not shown, the main circuit board MCB may include a driver chip DIC (refer to FIG. Figure 2 ).

[0086] refer to Figure 2 and Figure 3 The flexible circuit board FCB is bonded to the rear surface of the display module DM (rear surface bonding). The non-display area DM-NDA of the display module DM is not bent, thus preventing defects caused by bending of the non-display area DM-NDA of the display module DM. Furthermore, the area of ​​the bezel area BZA of the window WM, which covers the non-display area DM-NDA of the display module DM, can be reduced.

[0087] Figure 4 is a simplified cross-sectional view of an embodiment of a display module according to the present disclosure.

[0088] refer to Figure 4 The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-ED, and an encapsulation layer TFE.

[0089] The circuit layer DP-CL is disposed on the upper surface of the base layer BL. The base layer BL may be a flexible substrate that is bendable, foldable, rollable, etc. The base layer BL may be a glass substrate, a metal substrate, or a polymer substrate. However, the present disclosure is not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. The base layer BL has a shape substantially the same as that of the display panel DP.

[0090] The base layer BL may have a multilayer structure. In an embodiment, for example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed therebetween. The first synthetic resin layer and the second synthetic resin layer may each include a polyimide-based resin, and are not particularly limited.

[0091] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include multiple insulating layers, multiple semiconductor patterns, multiple conductive patterns, signal lines, and the like. The circuit layer DP-CL may include pixel driver circuits. Hereinafter, unless otherwise specified, when components A and B are disposed in the same layer, they are interpreted as being formed by the same process and having the same material or the same stacking structure. Conductive patterns or semiconductor patterns disposed in the same layer may be interpreted as described above.

[0092] The display element layer DP-ED may be disposed on the circuit layer DP-CL. The display element layer DP-ED may include a light-emitting element. In an embodiment, the light-emitting element may include, for example, an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro light-emitting diode ("LED"), or a nano-LED.

[0093] The encapsulation layer TFE may be provided on the display element layer DP-ED. The encapsulation layer TFE may be used to protect the display element layer DP-ED, which serves as a light-emitting element, from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may include at least one inorganic encapsulation layer. The encapsulation layer TFE may include a stacked structure of a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer.

[0094] The input sensing layer (ISL) may be directly disposed on the display panel DP. The input sensing layer (ISL) may detect user input using, for example, an electromagnetic induction method or a capacitive method. The display panel DP and the input sensing layer (ISL) may be formed using a roll-to-roll process. Terms such as "directly disposed" as used herein may indicate that no third component is disposed between the input sensing layer (ISL) and the display panel DP. In embodiments, for example, a separate adhesive layer may not be disposed between the input sensing layer (ISL) and the display panel DP.

[0095] Figure 5 is a plan view of an embodiment of a display panel according to the present disclosure. Figure 6 is a cross-sectional view of an embodiment of a display module according to the present disclosure. Specifically, Figure 5 It is a plan view of the display panel DP viewed from a third direction DR3.

[0096] like Figure 5 As shown in FIG, the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The plurality of pixels PX are arranged in the display area DM-DA. Each of the pixels PX includes a light emitting element and a pixel drive circuit connected thereto. The scan drive circuit SDC, the plurality of signal lines SGL, and the pixel drive circuit may be included in Figure 4 The circuit layer DP-CL is shown in FIG.

[0097] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit generates multiple scan signals and sequentially outputs the multiple scan signals to the multiple scan lines GL, which will be described later. The scan drive circuit SDC may also include a light emitting drive circuit separate from the gate drive circuit. The light emitting drive circuit may output scan signals to another group of scan lines.

[0098] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit, for example, a low temperature polysilicon (“LTPS”) process or a low temperature polycrystalline oxide (“LTPO”) process.

[0099] The plurality of signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each scan line GL is connected to a corresponding pixel PX among the plurality of pixels PX, and each data line DL is connected to a corresponding pixel PX among the plurality of pixels PX. The power lines PL are connected to the plurality of pixels PX. The data lines DL provide data signals to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit SDC.

[0100] A plurality of power lines PL may be provided. In an embodiment, for example, the power lines PL may include a first power line receiving a first power voltage and a second power line receiving a second power voltage at a higher level than the first power voltage. The first power voltage is supplied to the pixel PX via the first power line, and the second power voltage is supplied to the pixel PX via the second power line. Figure 5 One control signal line CSL is shown in the embodiment, but a plurality of control signal lines CSL may be provided.

[0101] The scan lines GL, data lines DL, and power lines PL may overlap the display area DM-DA and the non-display area DM-NDA, and the control signal lines CSL may overlap the non-display area DM-NDA. The ends of the plurality of signal lines SGL may be aligned on one side of the non-display area DM-NDA. Each of the plurality of signal lines SGL may have a single main body shape, but may include a plurality of portions disposed in different layers. The different portions separated by an insulating layer may be connected via contact holes passing through the insulating layer. In an embodiment, for example, the data line DL may include a first portion disposed in the display area DM-DA and a second portion disposed in the non-display area DM-NDA and disposed in a different layer from the first portion. The first portion and the second portion may include different materials and may have different stacking structures.

[0102] The plurality of signal lines SGL may be electrically connected to the pad area PA. Figure 3In an embodiment, for example, a plurality of signal lines SGL may be provided in the pad area PA and connected to pad electrodes PD spaced apart in the first direction DR1 through connection electrodes or the like. The pad electrodes PD may be provided on the rear surface of the display panel DP and connected to a flexible circuit board FCB (refer to FIG. Figure 2 ).

[0103] Figure 6 shows the display module DM and Figure 5 The cross section corresponding to the pixel PX.

[0104] The pixel driving circuit PC driving the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit PC may include a plurality of transistors S-TFT and O-TFT and a capacitor Cst. The plurality of transistors S-TFT and O-TFT may include silicon transistors S-TFT and oxide transistors O-TFT. Figure 6 A silicon transistor S-TFT and an oxide transistor O-TFT are shown. Figure 6 The pixel driving circuit PC is just one of the embodiments, and the components of the pixel driving circuit PC are not necessarily limited thereto. The pixel driving circuit PC may include only one type of transistor of a silicon transistor S-TFT and an oxide transistor O-TFT.

[0105] refer to Figure 6 , the base layer BL is shown as a single layer. The base layer BL may include a synthetic resin such as polyimide. The synthetic resin layer may be applied to a working substrate (or carrier substrate) to form the base layer BL. When the display module DM is completed through subsequent processes, the working substrate may be removed.

[0106] refer to Figure 6 The barrier layer BRL may be disposed on the base layer BL. The barrier layer BRL prevents the introduction of foreign matter from the outside. The barrier layer BRL may include at least one inorganic layer. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in plurality, and the silicon oxide layers and silicon nitride layers may be alternately stacked.

[0107] The barrier layer BRL may include a lower barrier layer BRL1 and an upper barrier layer BRL2. The first shielding electrode BML1 may be disposed between the lower barrier layer BRL1 and the upper barrier layer BRL2. The first shielding electrode BML1 may be disposed to correspond to the silicon transistor S-TFT. The first shielding electrode BML1 may include a metal such as molybdenum.

[0108] The first shielding electrode BML1 can receive a bias voltage. The first shielding electrode BML1 can also receive a first power supply voltage. The first shielding electrode BML1 can block the potential caused by polarization from affecting the silicon transistor (S-TFT). The first shielding electrode BML1 can also block external light from reaching the silicon transistor (S-TFT). In an embodiment of the present disclosure, the first shielding electrode BML1 can be a floating electrode isolated from other electrodes or wiring.

[0109] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BL into the first semiconductor pattern SC1 disposed above the buffer layer BFL. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0110] The first semiconductor pattern SC1 may be disposed on the buffer layer BFL. The first semiconductor pattern SC1 may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon, polysilicon, etc. In an embodiment, for example, the first semiconductor pattern SC1 may include low-temperature polysilicon.

[0111] The first semiconductor pattern SC1 can have different electrical characteristics depending on whether it is doped or undoped. The first semiconductor pattern SC1 may include a first region with relatively high conductivity and a second region with relatively low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region or may be doped at a lower concentration than the first region. In the illustrated embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0112] The first region has a greater conductivity than the second region and can be basically used as an electrode or a signal line. The second region can basically correspond to the channel region (or active region) of the transistor. That is, a portion of the first semiconductor pattern SC1 can be the channel region of the transistor, another portion can be the source region or the drain region of the transistor, and the remaining portion can be a connection electrode or a connection signal line.

[0113] A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed of the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend from the channel region AC1 in opposite directions in a cross section.

[0114] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. The first insulating layer 10 of the circuit layer DP-CL and the inorganic layer described later may have a single-layer structure or a multi-layer structure and may include at least one of the aforementioned materials, but the present disclosure is not limited thereto.

[0115] The gate GT1 of the silicon transistor S-TFT is disposed on the first insulating layer 10. The gate GT1 may be part of a metal pattern. The gate GT1 overlaps with the channel region AC1. The gate GT1 may be a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the storage capacitor Cst is disposed on the first insulating layer 10. Figure 6 Unlike what is shown in FIG, the first electrode CE10 may have a single body shape with the gate electrode GT1.

[0116] The second insulating layer 20 may be provided on the first insulating layer 10 and may cover the gate electrode GT1. In an embodiment of the present disclosure, an upper electrode overlapping the gate electrode GT1 may be further provided on the second insulating layer 20. A second electrode CE20 overlapping the first electrode CE10 may be provided on the second insulating layer 20. The upper electrode may have a single body shape with the second electrode CE20 in a plan view.

[0117] The second shielding electrode BML2 is disposed on the second insulating layer 20. The second shielding electrode BML2 may be disposed to correspond to the oxide transistor O-TFT. In an embodiment of the present disclosure, the second shielding electrode BML2 may not be provided. In an embodiment of the present disclosure, the first shielding electrode BML1 may extend to the bottom of the oxide transistor O-TFT, thereby replacing the second shielding electrode BML2.

[0118] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a metal oxide semiconductor such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), indium gallium zinc oxide ("IGZO"), zinc oxide (ZnO x ), transparent conductive oxides ("TCO") such as indium oxide (In2O3).

[0119] The metal oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 divided according to whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter referred to as the reduced region) has a greater conductivity than the region where the transparent conductive oxide is not reduced (hereinafter referred to as the non-reduced region). The reduced region essentially serves as the source / drain region of the transistor or a signal line. The non-reduced region essentially corresponds to the semiconductor region (or channel region) of the transistor. That is, a portion of the second semiconductor pattern SC2 may be the semiconductor region of the transistor, another portion may be the source region SE2 / drain region DE2 of the transistor, and the remaining region may be a signal transmission region.

[0120] The fourth insulating layer 40 may be disposed on the third insulating layer 30. Figure 6 As shown in , the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In an embodiment of the present disclosure, the fourth insulating layer 40 may be an insulating pattern overlapping the gate GT2 of the oxide transistor O-TFT and exposed by the source region SE2 and the drain region DE2 of the oxide transistor O-TFT.

[0121] The gate electrode GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate electrode GT2 of the oxide transistor O-TFT may be a portion of the metal pattern. The gate electrode GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0122] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate electrode GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer.

[0123] A first connection pattern CNP1 and a second connection pattern CNP2 may be disposed on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 are formed by the same process and may have the same material and the same stacking structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 passing through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship between the first connection pattern CNP1 and the second connection pattern CNP2 for the silicon transistor S-TFT and the oxide transistor O-TFT is not necessarily limited thereto.

[0124] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. A third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 via a third pixel contact hole PCH3 passing through the sixth insulating layer 60. A data line DL may be disposed on the sixth insulating layer 60. A seventh insulating layer 70 is disposed on the sixth insulating layer 60 and may cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL are formed by the same process and therefore may have the same material and the same stacking structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0125] The first shield electrode BML1, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo), an alloy containing or consisting of molybdenum, titanium (Ti), or an alloy containing or consisting of titanium, which has satisfactory heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum, which has relatively high electrical conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer structure in which titanium / aluminum / titanium are stacked.

[0126] The light-emitting element LD may include an anode AE ​​(or first electrode), an emission layer EL, and a cathode CE (or second electrode). The anode AE ​​of the light-emitting element LD may be disposed on the seventh insulating layer 70. The anode AE ​​may be a transmissive electrode, a semi-transmissive semi-reflective electrode, or a reflective electrode. The anode AE ​​may include a stacked structure in which ITO / Ag / ITO are stacked in this order. The positions of the anode AE ​​and the cathode CE may be interchangeable.

[0127] A pixel-defining layer (PDL) may be disposed on the seventh insulating layer 70. The pixel-defining layer (PDL) may be an organic layer. The pixel-defining layer (PDL) may have light-absorbing properties, and for example, the pixel-defining layer (PDL) may be black. The pixel-defining layer (PDL) may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel-defining layer (PDL) may correspond to a light-blocking pattern having light-blocking properties.

[0128] The pixel defining film PDL may cover a portion of the anode AE. In an embodiment, for example, an opening PDL-OP exposing a portion of the anode AE ​​may be defined in the pixel defining film PDL. The light emitting area LA may be defined to correspond to the opening PDL-OP. In an embodiment of the present disclosure, a hole control layer may be provided between the anode AE ​​and the emission layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be provided between the emission layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0129] The encapsulation layer TFE may cover the light emitting element LD. The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the present disclosure is not limited thereto, and the encapsulation layer TFE may also include a plurality of inorganic layers and organic layers.

[0130] The first encapsulation insulating layer IL1 may be an inorganic layer. The first encapsulation insulating layer IL1 may prevent external moisture or oxygen from penetrating into the light emitting element LD. In an embodiment, for example, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or any combination thereof. The first encapsulation insulating layer IL1 may be formed by a chemical vapor deposition process.

[0131] The second encapsulation insulating layer IL2 may be an organic layer. The second encapsulation insulating layer IL2 may be disposed on the first encapsulation insulating layer IL1 and may contact the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 may provide a flat surface on the first encapsulation insulating layer IL1. Curvature formed on the upper surface of the first encapsulation insulating layer IL1 or particles on the first encapsulation insulating layer IL1 may be covered by the second encapsulation insulating layer IL2 to prevent the surface state of the upper surface of the first encapsulation insulating layer IL1 from affecting components formed on the second encapsulation insulating layer IL2. In addition, the second encapsulation insulating layer IL2 may relieve stress between contacting layers. The second encapsulation insulating layer IL2 may be formed by a solution process such as spin coating, slit coating, or inkjet process.

[0132] The third encapsulation insulating layer IL3 is provided on and covers the second encapsulation insulating layer IL2. The third encapsulation insulating layer IL3 can be stably formed on a relatively flat surface rather than being provided on the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 seals moisture released from the second encapsulation insulating layer IL2 and prevents moisture from flowing to the outside.

[0133] The third encapsulation insulating layer IL3 may be optically transparent. In an embodiment, for example, the third encapsulation insulating layer IL3 may have a visible light transmittance of about 90% or more. The third encapsulation insulating layer IL3 may have a relatively higher light transmittance than the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO x ) or silicon oxynitride (SiON). The third encapsulation insulating layer IL3 may be formed by a chemical vapor deposition process. Each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include a plurality of layers and is not limited to a specific embodiment.

[0134] The input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In the illustrated embodiment, the input sensing layer ISL may include a first sensing insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 6 The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 are schematically shown.

[0135] The first sensing insulating layer IS-IL1 may be directly disposed on the display panel DP. The first sensing insulating layer IS-IL1 may be an inorganic layer including at least any one of silicon nitride, silicon oxynitride, and silicon oxide. The first conductive layer ICL1 and the second conductive layer ICL2 may each have a single-layer structure or may have a multi-layer structure stacked along the third direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 may include conductive lines defining electrodes in a grid form. The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may be connected through contact holes passing through the second insulating layer IS-IL2, or may not be connected. The connection relationship between the conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may be determined according to the type of sensor formed as the input sensing layer ISL.

[0136] The first conductive layer ICL1 and the second conductive layer ICL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or any alloy thereof. The transparent conductive layer may include, for example, indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO x ) or indium zinc tin oxide ("IZTO"). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) ("PEDOT"), metal nanowires, graphene, etc.

[0137] The first conductive layer ICL1 and the second conductive layer ICL2 having a multilayer structure may include metal layers. The metal layers may have, for example, a three-layer structure of titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be disposed between the first conductive layer ICL1 and the second conductive layer ICL2. The third insulating layer IS-IL3 may cover the second conductive layer ICL2. In embodiments of the present disclosure, the third insulating layer IS-IL3 may not be provided. The second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include inorganic layers or organic layers.

[0138] Figure 7A is a view enlarging a portion of an embodiment of a display device according to the present disclosure. Figure 7B It is along Figure 7A Hereinafter, descriptions overlapping with those previously described will not be provided.

[0139] refer to Figure 7A and Figure 7B , a base opening B-OP may be defined in the base layer BL. A pad electrode PD may be provided in the base opening B-OP. Although not shown, the pad electrode PD may be electrically connected to a connection electrode provided on the base layer BL through a contact hole. The pad electrode PD may be electrically connected to the connection electrode through the connection electrode. Figure 6 The data line DL shown in FIG. The pad electrode PD may be exposed to the outside through the base opening B-OP. The pad electrode PD may be connected to the non-display area DM-NDA (refer to FIG. Figure 2 In an embodiment, for example, the pad electrode PD may be provided at Figure 2 In the pad area PA shown in .

[0140] refer to Figure 7A The pad electrodes PD may extend in the second direction DR2 and be arranged along the first direction DR1. The distances d1 between the centers of adjacent pad electrodes PD arranged along the first direction DR1 may be equal to each other. In an embodiment, for example, the distance d1 between the pad electrodes PD arranged along the first direction DR1 may be about 10 μm to about 20 μm.

[0141] The flexible circuit board (FCB) may include a base film (BF) and a bump electrode (BMP) disposed on the base film (BF) and partially exposed from an edge (BE) of the base film (BF). The bump electrode (BMP) may overlap with the pad electrode (PD) in a plan view. The bump electrode (BMP) may contact and be electrically connected to the pad electrode (PD). A plurality of bump electrodes (BMP) may be provided. The plurality of bump electrodes (BMP) may be formed corresponding to the pad electrodes (PD). One bump electrode (BMP) may correspond to one pad electrode (PD). The plurality of bump electrodes (BMP) may extend in a second direction (DR2) and be arranged along the first direction (DR1).

[0142] The bump electrode BMP may be electrically connected to the pad electrode PD. Specifically, the display device DD may further include a metal pattern MP electrically connecting the bump electrode BMP and the pad electrode PD. The metal pattern MP contacts the pad electrode PD and the bump electrode BMP exposed from the edge BE of the base film BF to electrically connect the pad electrode PD and the bump electrode BMP.

[0143] Multiple metal patterns MP may be provided to correspond to the multiple pad electrodes PD. Each of the multiple metal patterns MP may be a pattern in which a metal ink is cured. The metal patterns MP may include solder paste. The metal patterns MP may be formed from a metal ink including or consisting of silver or copper. The metal pattern MP may be provided on each pad electrode PD. The metal patterns MP may be formed by curing and then patterning the metal ink. The metal patterns MP may be formed at a relatively low temperature and may electrically connect and simultaneously bond the pad electrodes PD and the bump electrodes BMP at a relatively high temperature without requiring a pressurization process.

[0144] Although not shown, an adhesive layer may be further provided between the pad electrode PD and the bump electrode BMP and between the base film BF and the base layer BL. In an embodiment, the adhesive layer may include an insulating material. In this case, the pad electrode PD and the bump electrode BMP may be electrically connected only through the metal pattern MP.

[0145] Figure 8 is a perspective view of an embodiment of a laser irradiation device according to the present disclosure. Figure 9 It shows Figure 8 A cross-sectional view of components of the optical system shown in . Figure 10A yes Figure 8 A plan view of the pattern mask shown in FIG. Figure 10B and Figure 10C It shows Figure 8 A plan view of another embodiment of a pattern mask is shown in FIG. Figures 11A to 11C It shows Figure 8 View of the irradiation target shown in . Figures 8 to 11C, the laser irradiation device LID in the embodiment of the present disclosure will be described. The irradiation target ISB can be Figure 7B Some components of the display device DD shown in correspondence.

[0146] refer to Figure 8 , the laser irradiation device LID in an embodiment of the present disclosure may include an optical system OD, a pattern mask PM, and an optical lens OL, wherein the optical system OD emits strong light (e.g., laser L), the pattern mask PM includes a plurality of patterns, the laser L emitted from the optical system OD is incident on the plurality of patterns, and the laser L passes through the plurality of patterns. The irradiation target ISB may be irradiated with the laser L by the laser irradiation device LID according to the present disclosure. In an embodiment, for example, a metal layer MTL provided on a substrate SB may be irradiated with the laser L by the laser irradiation device LID in an embodiment of the present disclosure. The optical system OD may be placed on an upper portion of the laser irradiation device LID, and the pattern mask PM may be placed below the optical system OD. The optical lens OL may be disposed between the pattern mask PM and the irradiation target ISB.

[0147] refer to Figure 8 and Figure 9 , the optical system OD placed on the upper portion of the laser irradiation device LID may include a light source LS, a first lens LZ1, an attenuator AT, a reflecting mirror MR, and a second lens LZ2.

[0148] Laser light L may be emitted from a light source LS. Laser light L may be directed toward a first lens LZ1 disposed adjacent to the light source LS. In an embodiment of the present disclosure, laser light L may have a wavelength of approximately 200 nanometers (nm) to approximately 400 nm. In an embodiment, for example, laser light L may have a wavelength of approximately 248 nm to approximately 266 nm. However, the present disclosure is not limited thereto.

[0149] The first lens LZ1 can receive laser light L from the light source LS. The first lens LZ1 can adjust the size of the laser light L emitted from the light source LS. In other words, the first lens LZ1 can control the diameter or energy density of the laser light L. The first lens LZ1 can be a convex lens. The laser light L passing through the first lens LZ1 can be converged by the first lens LZ1. However, the present disclosure is not limited thereto, and the first lens LZ1 can be composed of two or more lenses.

[0150] The attenuator AT may be provided on the path of the laser light L passing through the first lens LZ1. That is, the laser light L focused by the first lens LZ1 may be provided to the attenuator AT. The attenuator AT may change the amplitude of the laser light L provided to the attenuator AT. However, the attenuator AT only reduces the amplitude of the laser light L and does not change the signal waveform of the laser light L. In other words, the attenuator AT may reduce the signal level of the laser light L.

[0151] The reflecting mirror MR can be set on the path of the laser L passing through the attenuator AT. The reflecting mirror MR can adjust the irradiation direction of the laser L so that the laser L is emitted to Figure 8 In an embodiment, for example, the reflecting mirror MR may change the irradiation direction of the laser light L from the second direction DR2 to the third direction DR3.

[0152] The second lens LZ2 can receive the laser light L passing through the reflective mirror MR. The second lens LZ2 can adjust the size of the laser light L emitted to the second lens LZ2 in the same manner as the first lens LZ1. That is, the second lens LZ2 can control the diameter or energy density of the laser light L. The second lens LZ2 can be a convex lens. The laser light L passing through the second lens LZ2 can be converged by the second lens LZ2. However, the present disclosure is not limited thereto, and the second lens LZ2 may include a plurality of lenses. By adjusting the focal length, the second lens LZ2 can be adjusted to have uniform energy in the area in which the laser light L is emitted. The laser light L passing through the second lens LZ2 can be emitted to Figure 8 The pattern mask PM shown in .

[0153] refer to Figure 8 and Figure 10A , the pattern mask PM may be disposed below the optical system OD. The pattern mask PM may be disposed between the optical system OD and the irradiation target ISB, and may be disposed parallel to the substrate SB of the irradiation target ISB. Specifically, the pattern mask PM may include a plane extending in a first direction DR1 and a second direction DR2. The pattern mask PM may receive the laser L emitted from the optical system OD. In an embodiment of the present disclosure, the laser L emitted from the optical system OD and incident on the pattern mask PM may include a laser line beam. However, the present disclosure is not limited thereto, and the laser L may include a laser area beam. In addition, Figure 9 The laser light L emitted by the light source LS shown in FIG. 1 may itself comprise a laser beam.

[0154] The pattern mask PM may be damaged by the laser light L emitted to the pattern mask PM, and therefore, may have an ablation threshold having a predetermined size or larger. In an embodiment, for example, the pattern mask PM may have an ablation threshold of about 100 mJ / cm2. 2 ) or greater ablation threshold.

[0155] The pattern mask PM may include a plurality of patterns PT. The plurality of patterns PT may be arranged to overlap the metal layer MTL in a plan view. The plurality of patterns PT may extend in the second direction DR2 and be arranged in the first direction DR1. The plurality of patterns PT may each have the same size, and the distance between adjacent patterns PT may also be the same.

[0156] The plurality of patterns PT may not overlap with the plurality of pads PDa in a plan view. The plurality of patterns PT may be used to pattern the metal layer MTL by patterning the laser light L emitted to the pattern mask PM. Patterned laser light L corresponding to the shapes of the plurality of patterns PT may be emitted to the metal layer MTL. That is, the metal layer MTL that overlaps with the region that does not overlap with the plurality of pads PDa may be irradiated with the laser light L to pattern the metal layer MTL. Therefore, the distance between the plurality of patterns PT in the first direction DR1 may be equal to the distance between the plurality of pads PDa in the first direction DR1.

[0157] Figure 10B It shows Figure 8 FIG. 2 is a view of another embodiment of a pattern mask PM shown in FIG.

[0158] refer to Figure 10B , the pattern mask PMa may include a plurality of patterns PTa. In a plan view, when compared with the plurality of pads PDa, the plurality of patterns PTa may be formed to be inclined at a predetermined angle relative to the second direction DR2. As shown in the figure, among the plurality of patterns PTa, the pattern PTa disposed in the center may have the same Figure 10A The shape of the pattern PT shown in , and with respect to the pattern PTa disposed in the center, the pattern PTa may be formed to be inclined in a direction toward the pattern PTa disposed in the center.

[0159] refer to Figure 10C The pattern mask PMb may include a plurality of patterns PTb. The plurality of patterns PTb may include first sub-patterns SPT1 and second sub-patterns SPT2 spaced apart in the second direction DR2. The first sub-patterns SPT1 and the second sub-patterns SPT2 may each be arranged in the first direction DR1. When viewed in the second direction DR2, the first sub-patterns SPT1 and the second sub-patterns SPT2 may be alternately arranged in the first direction DR1. Specifically, one of the second sub-patterns SPT2 may be disposed between two adjacent first sub-patterns SPT1, and one of the first sub-patterns SPT1 may be disposed between two adjacent second sub-patterns SPT2.

[0160] Return Reference Figure 8 , further comprising a moving module MM for moving the pattern mask PM in a third direction DR3. While irradiating the irradiation target ISB with the laser light L, the moving module MM can move the pattern mask PM in the third direction DR3. Therefore, as the pattern mask PM moves in the third direction DR3, the area of ​​the laser light L patterned by passing through the pattern mask PM (also referred to as the irradiation area) can gradually increase. In other words, the moving module MM can control the area of ​​the laser light L emitted to the metal layer MTL by moving the pattern mask PM in the third direction DR3.

[0161] An optical lens OL may be further disposed between the pattern mask PM and the irradiation target ISB. The optical lens OL may converge the laser light L passing through the pattern mask PM. In other words, the optical lens OL may include a convex lens. In embodiments of the present disclosure, the optical lens OL may include a chromatic aberration lens. In embodiments, for example, the optical lens OL may be a lens assembly for preventing chromatic aberration. Thus, the laser light L passing through the optical lens OL can be uniformly emitted to the irradiation target ISB.

[0162] Figure 11A It is a stereogram of the irradiation target ISB. Figure 11B It is along Figure 11A 1 is a cross-sectional view of the irradiation target ISB taken along line III-III'. Figure 11C It is along Figure 11A sectional view of the irradiation target ISB taken along line IV-IV'.

[0163] refer to Figure 8 and Figure 11A The irradiation target ISB may include a substrate SB, a plurality of pads PDa provided on the substrate SB, a flexible circuit board FCBa, and a metal layer MTL provided on the plurality of pads PDa and the flexible circuit board FCBa. The flexible circuit board FCBa may include a base film BFa and a bump electrode BMPa. Figure 11A The substrate SB, the plurality of pads PDa and the flexible circuit board FCBa shown in FIG can be Figure 7B The base layer BL, the plurality of pad electrodes PD, and the flexible circuit board FCB shown in FIG correspond to each other. Therefore, an overlapping description will not be provided.

[0164] refer to Figures 11A to 11C The metal layer MTL may be provided on the plurality of pads PDa and the bump electrodes BMPa. The metal layer MTL may be integrated with the plurality of pads PDa and the bump electrodes BMPa. The laser irradiation device LID in the embodiment of the present disclosure (refer to Figure 8 ) aims to irradiate the metal layer MTL provided in the region not overlapping with the plurality of pads PDa and the bump electrode BMPa with laser, so that the metal layer MTL is formed to be provided only in the region overlapping with the plurality of pads PDa and the bump electrode BMPa.

[0165] refer to Figure 11B , an adhesive layer may be provided. The adhesive layer AL may be provided between the substrate SB and the base film BFa. The substrate SB and the base film BFa may be bonded by the adhesive layer AL. In an embodiment of the present disclosure, the adhesive layer AL may include a non-conductive material. In an embodiment, for example, the adhesive layer AL may be provided between the substrate SB and the base film BFa in the form of a non-conductive film.

[0166] refer to Figure 11C The metal layer MTL may overlap with the plurality of pads PDa and the bump electrode BMPa in a plan view to be disposed on the plurality of pads PDa and the bump electrode BMPa. The metal layer MTL may be electrically connected. The metal layer MTL is formed to overlap only with the plurality of pads PDa and the bump electrode BMPa in a plan view, and thus, the plurality of pads PDa and the bump electrode BMPa may be electrically connected.

[0167] refer to Figure 8 and Figures 11A to 11C , the laser L passing through the optical lens OL can be emitted to the metal layer MTL that does not overlap with the multiple pads PDa and the bump electrode BMPa. When the laser L is used to pattern the metal layer MTL including the non-uniform thickness, the substrate SB can also be patterned by the laser L and may be damaged as a result. The laser irradiation device LID in the embodiment of the present disclosure controls the area in which the laser L is emitted to the metal layer MTL having the non-uniform thickness by moving the moving module MM of the pattern mask PM in the third direction DR3, and thus the metal layer MTL can be patterned without damaging the substrate SB. Using the laser irradiation device LID in the embodiment of the present disclosure (refer to Figure 8 ) Process for forming the metal pattern MP ( Figure 15A ) will be described later.

[0168] Figure 12A is a perspective view of an embodiment of a laser irradiation device according to the present disclosure. Figure 12B yes Figure 12A A plan view of the opening mask shown in . Figure 12C It is along Figure 12A A cross-sectional view taken along line V-V' of FIG. No overlapping content with the previous description will be provided.

[0169] refer to Figure 12A and Figure 12B , the laser irradiation device LIDa in the embodiment of the present disclosure may include an opening mask OPM. Figure 8 Unlike the pattern mask PM shown in the figure, the open mask OPM may include an opening hole OH instead of the pattern PT. The laser light L emitted from the laser irradiation device LIDa in the embodiment of the present disclosure may be emitted to the open mask OPM including the opening hole OH. The laser light L emitted to the open mask OPM may be emitted from the open mask OPM corresponding to the shape of the opening hole OH. The laser light L emitted from the open mask OPM may pass through the optical lens OL and be emitted to the metal layer MTLa.

[0170] The irradiation target ISBa may include a substrate SB, a plurality of pads PDa provided on the substrate SB, a flexible circuit board FCBa, and a metal layer MTLa provided on the plurality of pads PDa and the flexible circuit board FCBa. The flexible circuit board FCBa may include a base film BFa and bump electrodes BMPa. The irradiation target ISBa may be irradiated with laser light L using a laser irradiation device LIDa according to the present disclosure. In an embodiment, for example, the metal layer MTLa provided on the substrate SB may be irradiated with laser light L using the laser irradiation device LIDa according to an embodiment of the present disclosure.

[0171] When the metal layer MTLa having a non-uniform thickness is patterned, the substrate SB is also patterned after the patterning, which may cause damage to the substrate SB. The laser irradiation device LIDa in the embodiment of the present disclosure controls the region where the laser L is emitted to the metal layer MTLa having a non-uniform thickness by moving the moving module MM of the opening mask OPM in the third direction DR3, and thus the upper surface of the metal layer MTLa can be etched flat without damaging the substrate SB. That is, the opening mask (also referred to as the planarization mask) OPM can be used in forming a plurality of metal patterns MP (refer to FIG. Figure 7B ) The metal layer MTLa is planarized before patterning. Therefore, even when the metal layer MTLa is patterned using a laser scanning method, damage to the substrate SB may not be caused.

[0172] Figures 13A to 15B is a view illustrating an embodiment of a process of forming a metal pattern using a laser irradiation apparatus according to the present disclosure. Hereinafter, contents overlapping with those described previously will not be given.

[0173] Figure 13A is a perspective view of an embodiment of a laser irradiation device LID according to the present disclosure. Figure 13B It is along Figure 13A 4 is a cross-sectional view of the irradiation target ISB taken along line VI-VI'.

[0174] refer to Figure 13A and Figure 13B , laser light L emitted from the optical system OD may be incident on the pattern mask PM including the plurality of patterns PT. The patterned laser light L corresponding to the shapes of the plurality of patterns PT may be emitted to the metal layer MTLb. The laser light L is emitted to the metal layer MTLb, and thus, the metal layer MTLb may be etched corresponding to the region in which the laser light L is emitted. That is, as Figure 13B As shown in , a portion of the metal layer MTLb may be etched corresponding to a width w1 of the laser light L passing through the pattern mask PM. Figure 13A and Figure 13B1 and 2. When the optical system OD and the pattern mask PM form the first distance ds1, the width w1 of the laser light L passing through the pattern mask PM may be substantially the same as the width of the plurality of patterns PT.

[0175] Figure 14A is a perspective view of an embodiment of a laser irradiation device LID according to the present disclosure. Figure 14B It is along Figure 14A 1 is a cross-sectional view of the irradiation target ISB taken along line VII-VII'.

[0176] refer to Figure 14A and Figure 14B , patterned laser light L corresponding to the shape of the plurality of patterns PT may be emitted to the metal layer MTLc. Figure 14B As shown in FIG, a portion of the metal layer MTLc may be etched corresponding to the width w2 of the laser light L passing through the pattern mask PM. Figure 13A and Figure 13B compared to, Figure 14A and Figure 14B 1 is a view showing a state in which the pattern mask PM has been moved in the third direction DR3 by the moving module MM. The pattern mask PM is moved in the third direction DR3 by the moving module MM, and therefore, the width w2 of the laser light L passing through the pattern mask PM may be different from the width w2 of the laser light L passing through the pattern mask PM. Figure 13A and Figure 13B The width w1 of the laser light L passing through the pattern mask PM shown in FIG is different. Specifically, Figure 14B The width w2 of the laser light L passing through the pattern mask PM shown in FIG is greater than Figure 13B The width w1 of the laser light L passing through the pattern mask PM is shown in FIG. In addition, the pattern mask PM moves in the third direction DR3, and therefore, the second distance ds2 between the optical system OD and the pattern mask PM is less than Figure 13B A first distance ds1 between the optical system OD and the pattern mask PM is shown in FIG.

[0177] Figure 14B The width w2 of the laser light L passing through the pattern mask PM shown in FIG is formed to be larger than Figure 13B The width w1 of the laser light L passing through the pattern mask PM is shown in FIG, and therefore, the etching width and depth of the metal layer MTLc can be larger. That is, the etching width and depth of the metal layer MTLc can be greater than Figure 13B The etching width and depth of the metal layer MTLb are shown in FIG.

[0178] Figure 15A is a perspective view of an embodiment of a laser irradiation device LID according to the present disclosure. Figure 15B It is along Figure 15A1 is a cross-sectional view of the irradiation target ISB taken along line VIII-VIII'.

[0179] refer to Figure 15A and Figure 15B , the metal pattern MPa can be obtained by Figure 14A and Figure 14B Specifically, the metal layer MTLc may be irradiated with a patterned laser L corresponding to the shape of the plurality of patterns PT to form a metal pattern MPa. The metal pattern MPa may be formed with Figure 7B The metal pattern MP shown in corresponds to .

[0180] like Figure 15B As shown in FIG, the metal pattern MPa can be formed corresponding to the width w3 of the laser light L passing through the pattern mask PM. Figure 14A and Figure 14B compared to, Figure 15A and Figure 15B 1 is a view showing a state in which the pattern mask PM has been moved in the third direction DR3 by the moving module MM. The pattern mask PM is moved in the third direction DR3 by the moving module MM, and therefore, the width w3 of the laser light L passing through the pattern mask PM may be different from the width w3 of the laser light L passing through the pattern mask PM. Figure 14A and Figure 14B The width w2 of the laser light L passing through the pattern mask PM shown in FIG is different. Specifically, Figure 15B The width w3 of the laser light L passing through the pattern mask PM shown in FIG is greater than Figure 14B The width w2 of the laser light L passing through the pattern mask PM is shown in FIG. In addition, the pattern mask PM moves in the third direction DR3, and therefore, the third distance ds3 between the optical system OD and the pattern mask PM is less than Figure 14B A second distance ds2 between the optical system OD and the pattern mask PM is shown in .

[0181] refer to Figures 13A to 15B The pattern mask PM is moved in the third direction DR3 by the moving module MM, and thus the area in which the laser light L is emitted into the metal layer can be gradually increased. Ultimately, the substrate SB is not damaged by the laser light L emitted into the metal layer having a non-uniform thickness, and the metal pattern MPa defining the opening area M-OP can be formed.

[0182] When a metal layer having a non-uniform thickness is patterned with a laser, the laser may cause damage to the substrate disposed below the metal layer. The laser irradiation device in the embodiment of the present disclosure may include a pattern mask and a moving module for moving the pattern mask in the thickness direction of the substrate, wherein the pattern mask includes a plurality of patterns. When the laser is emitted, the area of ​​the metal layer having a non-uniform thickness irradiated with the laser can be controlled as the pattern mask moves in the above-mentioned direction. Therefore, a plurality of spaced-apart metal patterns can be formed by patterning the metal layer without damaging the substrate disposed below the metal layer.

[0183] Although the present disclosure has been described with reference to preferred embodiments thereof, it will be understood that the present disclosure should not be limited to these preferred embodiments but may be variously changed and modified by those skilled in the art without departing from the spirit and scope of the present disclosure.

[0184] Therefore, the technical scope of the present disclosure is not limited to the detailed description in the specification, but should be determined only with reference to the claims.

Claims

1. A laser irradiation device for irradiating a metal layer with laser light to form a plurality of metal patterns spaced apart in a first direction, the metal layer overlapping a plurality of pad electrodes provided on a substrate and a plurality of bump electrodes, each provided to correspond to the plurality of pad electrodes, and having a non-uniform thickness, the laser irradiation device comprising: an optical system comprising a light source for emitting said laser light; a pattern mask including a plurality of patterns on which the laser light emitted from the optical system is incident and through which the laser light passes; as well as a moving module that moves the pattern mask in a direction perpendicular to the substrate while irradiating the metal layer with the laser to control a region in which the metal layer is irradiated with the laser, The plurality of pad electrodes and the plurality of bump electrodes are electrically connected through the plurality of metal patterns.

2. The laser irradiation device according to claim 1, wherein The plurality of patterns are arranged in the first direction and do not overlap with the plurality of metal patterns.

3. The laser irradiation device according to claim 2, characterized in that The plurality of patterns are formed to be inclined at a predetermined angle with respect to the plurality of pad electrodes in a plan view.

4. The laser irradiation device according to claim 2, wherein The plurality of patterns include first and second sub-patterns spaced apart in a second direction crossing the first direction.

5. The laser irradiation device according to claim 4, characterized in that The first sub-patterns and the second sub-patterns are alternately arranged in the first direction in a plan view.

6. The laser irradiation device according to claim 1, wherein A plurality of opening areas are defined between two adjacent metal patterns among the plurality of metal patterns.

7. The laser irradiation device according to claim 6, characterized in that The plurality of patterns overlap with the plurality of opening areas in a plan view.

8. The laser irradiation device according to claim 1, wherein The pattern mask is disposed between the optical system and the substrate.

9. The laser irradiation device according to claim 8, characterized in that The pattern mask is arranged parallel to the substrate.

10. The laser irradiation device according to claim 1, wherein The laser light emitted from the light source has a wavelength of 200 nm to 400 nm.

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