High-heat-dissipation staggered chip stacking packaging structure
By introducing a heat dissipation cover and liquid cooling channels into the staggered chip stacking packaging structure, combined with the TGV/TSV structure of the glass or silicon substrate, the heat dissipation problem of the packaging structure is solved, and efficient heat conduction and packaging stability are achieved.
Patent Information
- Application Number
- CN202422760501.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2034-11-12
AI Technical Summary
The existing staggered chip stacking packaging structure has the problem of heat dissipation difficulties, especially in highly integrated 3D packaging, where the heat dissipation efficiency is low and it is difficult to meet the demand for efficient heat dissipation.
A heat dissipation cover and heat dissipation substrate are combined to form a liquid cooling channel. Through the heat dissipation cover and the coolant circulation, combined with the TGV/TSV structure in the glass or silicon carrier, rapid heat conduction and heat dissipation are achieved, replacing traditional organic carriers.
The heat dissipation efficiency of the chip stacking structure is significantly improved, the stability of the packaging structure and efficient heat dissipation are ensured, and the packaging cost is reduced.
Smart Images
Figure CN223378163U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductor packaging, and in particular relates to a high-heat-dissipating staggered chip stacking packaging structure. Background Art
[0002] With the continuous advancement of semiconductor technology, chip packaging technology is also making continuous progress. Currently, 2D packaging and 3D packaging are the two mainstream packaging technologies. These two packaging technologies have their own characteristics and challenges in terms of heat dissipation paths and thermal design.
[0003] Compared with 2D packaging, 3D packaging stacks multiple chips together to achieve higher integration and smaller size, but it also brings more complex heat dissipation problems.
[0004] 2D and 3D packaging each have their own unique characteristics and challenges in terms of heat dissipation paths and thermal design. The heat dissipation path for 2D packaging is relatively straightforward, primarily transferring heat upward to the package housing through thermally conductive materials. However, 3D chip stacking structures present a more complex heat dissipation challenge, requiring heat conduction through multiple stacked chips. Given the unique characteristics of 3D packaging, special attention must be paid to optimizing heat dissipation performance by reducing the thermal resistance of the chip itself and utilizing highly conductive paths.
[0005] Currently, to increase DRAM capacity, memory packaging mostly uses HBM (High Bandwidth Memory) 3D packaging. HBM utilizes a direct TSV stacking method. Through-silicon via (TSV) technology is the core HBM process, accounting for nearly 30% of the total cost, the largest portion of HBM packaging costs. The TSV process is prohibitively expensive to control yield and, coupled with the complexity of the packaging process, yield control is difficult. The overall cost of HBM is very high, currently limiting its application to AI GPU packaging, making it difficult to expand its application.
[0006] As a result, a staggered chip stacking packaging structure has emerged on the market. This packaging structure generally includes an organic substrate structure that supports and electrically connects the chips on both sides, and memory chips stacked on both sides of the organic substrate. This staggered stacking packaging structure also faces the problem of heat dissipation difficulties.
[0007] Therefore, there is an urgent need for a staggered chip stacking packaging structure that improves heat dissipation performance. Utility Model Content
[0008] The purpose of the present utility model is to provide a high-heat dissipation staggered chip stacking packaging structure, which forms a complete liquid cooling channel through the structure of the heat dissipation cover and the heat dissipation substrate, and can efficiently dissipate the heat generated inside the staggered stacking structure of such storage chips, thereby improving the heat dissipation efficiency and meeting the heat dissipation requirements.
[0009] To achieve the above objectives, the present invention provides a high heat dissipation staggered chip stacking packaging structure, which includes:
[0010] A package body, an upper stacked chipset and a lower stacked chipset symmetrically arranged in the package body, wherein the upper stacked chipset and the lower stacked chipset are both formed by staggered stacking of multiple chips;
[0011] A heat dissipation cover is provided above the packaging body, wherein one end of the heat dissipation cover is provided with a coolant inlet and the other end is provided with a coolant outlet;
[0012] a heat dissipation substrate disposed between the upper and lower chipsets within the package, the heat dissipation substrate being provided with vertical electrical interconnection through-holes and at least one horizontal microfluidic channel, the upper and lower chipsets being connected via the electrical interconnection through-holes; one end of the microfluidic channel being an inlet and the other end being an outlet;
[0013] The inlet of the microchannel is connected to the coolant inlet, and the outlet is connected to the coolant outlet.
[0014] Preferably, the inlet of the microchannel is connected to the coolant inlet through a first diverter component, and the outlet is connected to the coolant outlet through a second diverter component.
[0015] Preferably, the first diversion component includes a first connecting port, a first diversion groove and multiple first diversion ports, the first connecting port is connected to the coolant inlet, the upper end of the first diversion groove is connected to the first connecting port, and the lower end is connected to multiple first diversion ports; the first diversion ports are connected to the microchannel inlet one by one.
[0016] Preferably, the second diversion component includes a second connecting port, a second diversion groove and multiple second diversion ports, the second connecting port is connected to the coolant outlet, the upper end of the second diversion groove is connected to the second connecting port, and the lower end is connected to multiple second diversion ports, and the second diversion ports are connected to the microchannel outlet one by one.
[0017] Preferably, the first flow diversion component and the second flow diversion component are arranged at the bottom of the heat dissipation cover.
[0018] Preferably, the heat dissipation cover is connected to the packaging body via a thermal interface material.
[0019] Preferably, the heat dissipation substrate is a silicon carrier or a glass substrate.
[0020] Compared with the prior art, the present invention has the following beneficial effects:
[0021] On the one hand, the present invention can dissipate heat through the heat dissipation cover. On the other hand, the organic carrier in the middle of the existing staggered chip stacking packaging structure is replaced with a glass carrier or a silicon carrier. Vertical TGVs (TSVs are set inside the silicon carrier) and planar liquid-cooling microchannels are set inside the glass carrier. The ports of the liquid-cooling microchannels are connected to the coolant inlet and outlet on the heat dissipation cover through a diversion component, and the chips on both sides of the organic carrier are interconnected through the TGV / TSV. This combined structure can quickly conduct the heat generated inside the multi-chip stacking structure to the glass carrier / silicon carrier and the heat dissipation cover, and then be carried out through the coolant circulation, greatly improving the heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a schematic diagram of the packaging structure in the present utility model;
[0023] Figure 2 for Figure 1 Schematic diagram of the structure of the heat dissipation substrate;
[0024] Figure 3 for Figure 2 Structural diagram from another perspective;
[0025] Figure 4 for Figure 1 Schematic diagram of the structure of the heat dissipation cover;
[0026] Figure 5 for Figure 4 Schematic diagram of the structure from another perspective.
[0027] Figure numbers: package body-1, upper stacked chipset-2, lower stacked chipset-3, heat dissipation cover-4, heat dissipation substrate-5, electrical interconnection through hole-501, microchannel-502, inlet-5021, outlet-5022, thermal interface material-6, first shunt component-7, second shunt component-8, first connection port-701, first shunt groove-702, first shunt port-703, second connection port-801, second shunt groove-802, second shunt port-803, conductive bump-9, coolant inlet-10, coolant outlet-11. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present application will be described clearly and completely below with reference to the accompanying drawings.
[0029] like Figure 1 As shown, the present application discloses a high heat dissipation staggered chip stacking packaging structure, which includes:
[0030] The package body 1 has an upper chip group 2 and a lower chip group 3 symmetrically arranged in the package body 1. The upper chip group 2 and the lower chip group 3 are both formed by staggered stacking of multiple chips. The bottom of the package body 1 is connected to a conductive bump 9 for connecting to an external circuit.
[0031] The heat dissipation cover 4 is disposed above the package body 1 and is connected to the package body 1 via a thermal interface material 6. The heat dissipation cover 4 has a coolant inlet 10 at one end and a coolant outlet 11 at the other end; the coolant inlet 10 is connected to an external coolant addition system.
[0032] The structure of the heat dissipation substrate 5 is as follows Figure 2 and Figure 3 As shown, a heat dissipation substrate 5 is provided between the upper chipset 2 and the lower chipset 3 within the package 1, and is provided with a vertical electrical interconnection through-hole 501 and at least one horizontal microchannel 502. The upper chipset 2 and the lower chipset 3 are connected via the electrical interconnection through-hole 501. The microchannel 502 has an inlet 5021 at one end and an outlet 5022 at the other end. The inlet 5021 of the microchannel 502 is connected to the coolant inlet 10, and the outlet 5022 is connected to the coolant outlet 11.
[0033] The heat dissipation substrate 5 is a silicon carrier or a glass substrate. The technology of opening holes on a silicon carrier or a glass substrate is prior art and will not be described in detail here. The organic carrier in the middle of the existing staggered chip stacking packaging structure is replaced with a glass carrier or a silicon carrier, and a vertical TGV (TSV is set inside the silicon carrier) and a planar liquid cooling microchannel 502 are set inside the glass carrier. The port of the liquid cooling microchannel 502 is connected to the coolant inlet 10 and the outlet 5022 on the heat dissipation cover 4 through a diversion component, and the chips on both sides of the organic carrier are interconnected through TGV / TSV; this combined structure can quickly conduct the heat generated inside the multi-chip stacking structure to the glass carrier / silicon carrier and the heat dissipation cover 4, and then be taken out through the circulation of the coolant, which greatly improves the heat dissipation efficiency.
[0034] Specifically, the coolant inlet 10 and coolant outlet 11 are disposed at both ends of the heat dissipation cover 4. The inlet 5021 of the microchannel 502 is connected to the coolant inlet 10 via the first flow diversion component 7, while the outlet 5022 is connected to the coolant outlet 11 via the second flow diversion component 8, thereby forming the entire liquid-cooled microchannel 502. This structure increases the area over which the coolant flows through the package 1 and also collaborates with the heat dissipation cover 4 to dissipate heat from the package 1, increasing heat dissipation efficiency and ensuring operational stability of the package 1.
[0035] There are many structures that can connect the inlet 5021 of the microchannel 502 to the coolant inlet 10. In the present invention, the first diversion component 7 and the second diversion component 8 are innovatively arranged at the bottom of the heat dissipation cover 4, such as Figure 4 and Figure 5As shown, the specific structure is:
[0036] The first flow diversion assembly 7 includes a first connection port 701, a first diversion groove 702, and multiple first diversion ports 703. The first connection port 701 is connected to the coolant inlet 10. The upper end of the first diversion groove 702 is connected to the first connection port 701, and the lower end is connected to the multiple first diversion ports 703. The first diversion ports 703 are connected to the microchannel inlet 5021 in a one-to-one correspondence. A sealing sheet (not shown) is provided between the first connection port 701 and the coolant inlet 10 to ensure the sealing performance of the entire packaging structure and prevent coolant leakage.
[0037] The second flow diversion assembly 8 includes a second connection port 801, a second diversion groove 802, and multiple second diversion ports 803. The second connection port 801 is connected to the coolant outlet 11. The upper end of the second diversion groove 802 is connected to the second connection port 801, and the lower end is connected to the multiple second diversion ports 803. The second diversion ports 803 are connected to the microchannel outlet 5022 in a one-to-one correspondence. A sealing sheet (not shown) is also provided between the second connection port 801 and the coolant outlet 11 to ensure the sealing performance of the entire packaging structure and prevent coolant leakage.
[0038] In the present invention, vertical electrical interconnection through-holes 501 and multiple horizontal microchannels 502 need to be pre-fabricated in the heat dissipation substrate 5. A coolant inlet 10 and a coolant outlet 11 need to be pre-fabricated at both ends of the heat dissipation cover 4. A first diversion assembly 7 and a second diversion assembly 8 are also pre-fabricated at the bottom of the heat dissipation cover 4. The first diversion port 703 and the second diversion port 803 can be arranged according to the height of the package body 1 so that after the heat dissipation cover 4 and the package body 1 are connected, the first diversion port 703 and the second diversion port 803 exactly match the microchannel inlet 5021 and outlet 5022, as shown in FIG. Alternatively, upward through-holes can be provided in the package body 1 at positions corresponding to the microchannel inlet 5021 and outlet 5022, and then connected to the first diversion port 703 and the second diversion port 803. Regardless of the structure, as long as the first diversion port 703 can be connected to the microchannel inlet 5021 and the second diversion port 803 can be connected to the microchannel outlet 5022, it will suffice.
[0039] When the staggered chip stacking packaging structure shown in the present invention is working, the heat generated by multiple chips can be conducted away through the heat dissipation cover 4 to achieve the heat dissipation function. On the other hand, the coolant can also flow from the coolant inlet 10 into the first diversion component 7 and the microchannel inlet 5021, and then flow through the microchannel 502, and then flow from the microchannel outlet 5022 to the second diversion component 8, and finally flow out from the coolant outlet 11, so as to quickly conduct the heat generated by the chip operation. The coolant flow channel arranged in the heat dissipation cover 4 can also conduct heat through the heat dissipation cover 4. Therefore, the packaging structure provided by the present invention greatly improves the heat dissipation efficiency.
[0040] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.
Claims
1. A high heat dissipation staggered chip stacking packaging structure, characterized in that: include: A package body, an upper stacked chipset and a lower stacked chipset symmetrically arranged in the package body, wherein the upper stacked chipset and the lower stacked chipset are both formed by staggered stacking of multiple chips; A heat dissipation cover is provided above the packaging body, wherein one end of the heat dissipation cover is provided with a coolant inlet and the other end is provided with a coolant outlet; a heat dissipation substrate disposed between the upper and lower chipsets within the package, the heat dissipation substrate being provided with vertical electrical interconnection through-holes and at least one horizontal microfluidic channel, the upper and lower chipsets being connected via the electrical interconnection through-holes; one end of the microfluidic channel being an inlet and the other end being an outlet; The inlet of the microchannel is connected to the coolant inlet, and the outlet is connected to the coolant outlet.
2. The high heat dissipation staggered chip stacking package structure according to claim 1, characterized in that: The inlet of the microchannel is connected to the coolant inlet through a first flow diversion component, and the outlet is connected to the coolant outlet through a second flow diversion component.
3. The high heat dissipation staggered chip stacking package structure according to claim 2, characterized in that: The first diversion component includes a first connecting port, a first diversion groove and multiple first diversion ports. The first connecting port is connected to the coolant inlet. The upper end of the first diversion groove is connected to the first connecting port, and the lower end is connected to multiple first diversion ports; the first diversion ports are connected to the microchannel inlet one by one.
4. A high heat dissipation staggered chip stacking packaging structure according to claim 2 or 3, characterized in that: The second diversion component includes a second connecting port, a second diversion groove and multiple second diversion ports. The second connecting port is connected to the coolant outlet. The upper end of the second diversion groove is connected to the second connecting port, and the lower end is connected to multiple second diversion ports. The second diversion ports are connected to the microchannel outlet one by one.
5. The high heat dissipation staggered chip stacking packaging structure according to claim 4, characterized in that: The first flow diversion component and the second flow diversion component are arranged at the bottom of the heat dissipation cover.
6. The high heat dissipation staggered chip stacking packaging structure according to claim 5, characterized in that: The heat dissipation cover is connected to the packaging body through a thermal interface material.
7. The high heat dissipation staggered chip stacking package structure according to claim 6, characterized in that: The heat dissipation substrate is a silicon carrier or a glass substrate.