Bus isolation circuit based on data transceiver

Abstract

The utility model discloses a bus isolation circuit based on a data transceiver. A GPMC bus 16-path data line pin in a CPU is connected with a latch bus data input pin, and a latch address output pin of the latch is connected with a left address line and a right address line of a DPRAM respectively; the front and rear eight I / O pins of the left part of the DPRAM are respectively connected with the A bus pin of the first data transceiver and the A bus pin of the second data transceiver, and the B bus pin of the first data transceiver and the B bus pin of the second data transceiver are respectively connected with the front and rear eight data line pins of the GPMC bus; the front and rear eight I / O pins of the right part of the DPRAM are respectively connected with the A bus pin of the third data transceiver and the A bus pin of the fourth data transceiver, and the B bus pin of the third data transceiver and the B bus pin of the fourth data transceiver are connected with the front and rear eight data line pins of the GPMC bus. According to the utility model, electrical isolation between input and output signals can be realized, interference signals and fault conduction are effectively blocked, and the stability and safety of bus data transmission are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of communications, and more particularly relates to a bus isolation circuit based on a data transceiver. Background Art

[0002] In existing communication systems, buses and peripherals are typically connected directly, lacking effective isolation. This connection makes bus signals susceptible to electromagnetic interference and data interference, resulting in poor communication quality and, at high communication rates, errors or even interruptions. Therefore, effectively preventing data and electromagnetic interference on the bus, improving the stability and reliability of communication systems, and ensuring the integrity and security of data during transmission remain pressing technical challenges. Utility Model Content

[0003] The purpose of the utility model is to overcome the deficiencies in the prior art and provide a bus isolation circuit based on a data transceiver, which can realize electrical isolation between input and output signals, thereby effectively blocking interference signals and fault conduction, and improving the stability and security of bus data transmission.

[0004] The purpose of this utility model is achieved through the following technical solutions.

[0005] The utility model is based on a bus isolation circuit of a data transceiver, comprising a CPU, wherein 16 data line pins of a GPMC bus in the CPU are connected to bus data input pins of a latch, and latch address output pins of the latch are respectively connected to address lines of a left portion of a DPRAM and an address line of a right portion of a DPRAM;

[0006] The first 8 I / O pins of the left portion of the DPRAM are connected to the A-bus pins of the first data transceiver, and the B-bus pins of the first data transceiver are connected to the first 8 data line pins of the GPMC bus in the CPU; the last 8 I / O pins of the left portion of the DPRAM are connected to the A-bus pins of the second data transceiver, and the B-bus pins of the second data transceiver are connected to the last 8 data line pins of the GPMC bus in the CPU;

[0007] The first 8 I / O pins of the right part of the DPRAM are connected to the A bus pins of the third data transceiver, and the B bus pins of the third data transceiver are connected to the first 8 data line pins of the GPMC bus in the CPU; the last 8 I / O pins of the right part of the DPRAM are connected to the A bus pins of the fourth data transceiver, and the B bus pins of the fourth data transceiver are connected to the last 8 data line pins of the GPMC bus in the CPU.

[0008] Furthermore, the latch is a D-type latch, the latch enable pin of the latch is connected to the output pin of the first inverter, and the input pin of the first inverter is connected to the address valid control enable pin of the GPMC bus in the CPU.

[0009] Furthermore, the A to B output enable pin of the first data transceiver and the A to B output enable pin of the second data transceiver are both connected to the output pin of the second inverter, the input pin of the second inverter is connected to the 4th chip select enable signal line pin of the GPMC bus in the CPU, and the 4th chip select enable signal line pin is also respectively connected to the B to A output enable pin of the first data transceiver, the B to A output enable pin of the second data transceiver, and the input pin of the third inverter.

[0010] Furthermore, the chip master mode or slave mode setting pin of the left part of the DPRAM is connected to a 3.3V power supply via resistor No. 1, the low byte select pin is connected to the low eight-bit read and write enable pins of the GPMC bus in the CPU, the high byte select pin is connected to the high eight-bit read and write enable pins of the GPMC bus in the CPU, the first left port chip work enable pin is connected to the fourth chip select enable signal line pin of the GPMC bus in the CPU, the second left port chip work enable pin is connected to the output pin of the third inverter, the signal flag enable pin is connected to the 3.3V power supply via resistor No. 2, the read / write enable pin is connected to the read and write general control enable pin of the GPMC bus in the CPU, the chip output enable pin is connected to the output enable pin of the GPMC bus in the CPU, the busy flag pin is connected to the 3.3V power supply via resistor No. 7, and the interrupt flag pin is connected to the 3.3V power supply via resistor No. 8.

[0011] Furthermore, the A to B output enable pin of the third data transceiver and the A to B output enable pin of the fourth data transceiver are both connected to the output pin of the fourth inverter, the input pin of the fourth inverter is connected to the 5th chip select enable signal line pin of the GPMC bus in the CPU, and the 5th chip select enable signal line pin is also respectively connected to the B to A output enable pin of the third data transceiver, the B to A output enable pin of the fourth data transceiver, and the input pin of the fifth inverter.

[0012] Furthermore, the low byte selection pin of the right part of the DPRAM is connected to the low eight-bit read and write enable pins of the GPMC bus in the CPU, the high byte selection pin is connected to the high eight-bit read and write enable pins of the GPMC bus in the CPU, the first Right Port chip work enable pin is connected to the 5th chip select enable signal line pin of the GPMC bus in the CPU, the second Right Port chip work enable pin is connected to the output pin of the fifth inverter, the signal flag enable pin is connected to the 3.3V power supply via resistor No. 10, the read / write enable pin is connected to the read and write general control enable pin of the GPMC bus in the CPU, the chip output enable pin is connected to the output enable pin of the GPMC bus in the CPU, the busy flag pin is connected to the 3.3V power supply via resistor No. 15, and the interrupt flag pin is connected to the 3.3V power supply via resistor No. 16.

[0013] Compared with the prior art, the beneficial effects brought about by the technical solution of the utility model are:

[0014] The present invention uses data transceiver No. 1 U3, data transceiver No. 2 U5, data transceiver No. 3 U10, and data transceiver No. 4 U12 to achieve bus data isolation. The control signal of the bus (the chip select signal of the GPMC bus in the present invention) and inverter No. 2 U2 and inverter No. 4 U9 ​​form a control logic to control whether the A bus and B bus of the data transceiver are connected. In fact, this bus isolation method is physical isolation. The communication between the peripherals and the bus uses different physical lines, avoiding direct connection, which can effectively prevent the bus from being interfered with by other peripherals when transmitting data. This method can also achieve electrical isolation between the various parts, which can avoid damage to sensitive electronic equipment caused by high voltage or high current on the bus, thereby effectively blocking signal interference and fault conduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the principle of the CPU part of the utility model.

[0016] Figure 2 This is a schematic diagram of the DPRAM Left Port principle in the present utility model.

[0017] Figure 3 This is a schematic diagram of the DPRAM Right Port principle in the present utility model.

[0018] Figure numerals: U1-CPU, U2-inverter No. 2, U3-data transceiver No. 1, U4A-DPRAM left part, U4B-DPRAM right part, U5-data transceiver No. 2, U6-inverter No. 1, U7-inverter No. 3, U8-latch, U9-inverter No. 4, U10-data transceiver No. 3, U11-inverter No. 5, U12-data transceiver No. 4. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings.

[0020] The utility model is based on a bus isolation circuit of a data transceiver, which mainly includes a CPU (U1), a DPRAM, a first data transceiver U3, a second data transceiver U5, a third data transceiver U10, a fourth data transceiver U12, a latch U8, a first inverter U6, a second inverter U2, a third inverter U7, a fourth inverter U9, a fifth inverter U11, etc.

[0021] like Figure 1 As shown, the 16 data line pins gpmc_d0 to gpmc_d15 of the GPMC bus in the CPU are respectively connected to the bus data input pins 1D1 to 1D8 and 2D1 to 2D8 of the latch U8. The 16 latch address output pins (1Q1 to 1Q8 and 2Q1 to 2Q8) of the latch U8 are respectively connected to the address lines A0L to A15L of the left DPRAM U4A and the address lines A0R to A15R of the right DPRAM U4B. Among them, the latch enable pins 1LE and 2LE of the latch U8 are both connected to the output pin "4" of the first inverter U6. The input pin "2" of the first inverter U6 is connected to the address valid control enable pin gpmc_nadv_ale of the GPMC bus in the CPU. The power pin "5" of the first inverter U6 is connected to the 3.3V power supply, and the ground pin "3" is connected to the ground GND. Pins "7", "18", "31" and "42" of the latch U8 are all connected to a 3.3V power supply, chip enable pins 10E# and 20E# are both grounded GND, and ground lines "4", "10", "15", "21", "28", "34", "39" and "45" are all grounded GND.

[0022] like Figure 2As shown, the first 8 I / O pins I / O0L to I / O7L of the DPRAM left part (i.e., DPRAM Left Port) U4A are connected to the A-bus pins A1 to A8 of the first data transceiver U3, and the B-bus pins B1 to B8 of the first data transceiver U3 are connected to the first 8 data line pins gpmc_d0 to gpmc_d7 of the GPMC bus in the CPU. The power pin VCC of the data transceiver No. 1 U3 is connected to a 5V power supply, the ground line is connected to the ground GND, the B to A output enable pin OEBA# is connected to the 4th chip select enable signal line pin gpmc_ncs3 of the GPMC bus in the CPU, the A to B output enable pin OEAB of the data transceiver No. 1 U3 is connected to the output pin "4" of the inverter No. 2 U2, the input pin "2" of the inverter No. 2 U2 is connected to the 4th chip select enable signal line pin gpmc_ncs3 of the GPMC bus in the CPU, the power pin "5" of the inverter No. 2 U2 is connected to a 3.3V power supply, and the ground pin "3" is connected to the ground GND.

[0023] The last eight I / O pins (I / O8L-I / O15L) of the left DPRAM portion (U4A) are connected to the A-bus pins (A1-A8) of the second data transceiver (U5). The B-bus pins (B1-B8) of the second data transceiver (U5) are connected to the last eight data line pins (gpmc_d8-gpmc_d15) of the GPMC bus in the CPU. The power pin (VCC) of the second data transceiver (U5) is connected to a 5V power supply, the ground line (GND) is connected to the ground, the B-to-A output enable pin (OEBA#) is connected to the fourth chip select enable signal line (gpmc_ncs3) of the GPMC bus in the CPU, and the A-to-B output enable pin (OEAB) of the second data transceiver (U5) is connected to the output pin (4) of the second inverter (U2).

[0024] The chip master or slave mode setting pin M / S of the left DPRAM U4A is connected to a 3.3V power supply via resistor R1. The low-byte select pin LBL of the left DPRAM U4A is connected to the lower eight-bit read / write enable pins gpmc_nbe0_cle of the GPMC bus in the CPU, and is also connected to the 3.3V power supply via resistor R3. The high-byte select pin UBL of the left DPRAM U4A is connected to the upper eight-bit read / write enable pin gpmc_nbe1 of the GPMC bus in the CPU, and is also connected to the 3.3V power supply via resistor R4. The first left port chip enable pin CE0L of the left DPRAM U4A is connected to the fourth chip select enable signal line gpmc_ncs3 of the CPU's GPMC bus. The second left port chip enable pin CE1L of the left DPRAM U4A is connected to the output pin "4" of the third inverter U7. The input pin "2" of the third inverter U7 is connected to the fourth chip select enable signal line gpmc_ncs3 of the CPU's GPMC bus. The power pin "5" of the second inverter U2 is connected to a 3.3V power supply, and the ground pin "3" is connected to ground GND. The signal flag enable pin SEML of the left DPRAM U4A is connected to the 3.3V power supply via the second resistor R2. The read / write enable pin R / WL of the left DPRAM U4A is connected to the read / write general control enable pin gpmc_nwe of the CPU's GPMC bus, which is also connected to the 3.3V power supply via the fifth resistor R5. The chip output enable pin OEL of the left DPRAM U4A is connected to the GPMC bus output enable pin gpmc_noe of the CPU, and this pin is also connected to a 3.3V power supply via resistor R6. The busy flag pin BUSYL of the left DPRAM U4A is connected to a 3.3V power supply via resistor R7, and the interrupt flag pin INTL is connected to a 3.3V power supply via resistor R8.

[0025] like Figure 3As shown, the first 8 I / O pins I / O0R to I / O7R of the DPRAM right part (i.e., DPRAM Right Port) U4B are connected to the A-bus pins A1 to A8 of the third data transceiver U10, and the B-bus pins B1 to B8 of the third data transceiver U10 are connected to the first 8 data line pins gpmc_d0 to gpmc_d7 of the GPMC bus in the CPU. The power pin VCC of the third data transceiver U10 is connected to a 5V power supply, the ground line is connected to the ground GND, the B to A output enable pin OEBA# is connected to the 5th chip select enable signal line pin gpmc_ncs4 of the GPMC bus in the CPU, the A to B output enable pin OEAB of the third data transceiver U10 is connected to the output pin "4" of the fourth inverter U9, the input pin "2" of the fourth inverter U9 is connected to the 5th chip select enable signal line pin gpmc_ncs4 of the GPMC bus in the CPU, the power pin "5" of the fourth inverter U9 is connected to a 3.3V power supply, and the ground pin "3" is connected to the ground GND.

[0026] The last eight I / O pins (I / O8R-I / O15R) of the right DPRAM portion (U4B) are connected to the A-bus pins (A1-A8) of the fourth data transceiver (U12). The B-bus pins (B1-B8) of the fourth data transceiver (U12) are connected to the last eight data line pins (gpmc_d8-gpmc_d15) of the GPMC bus in the CPU. The power pin (VCC) of the fourth data transceiver (U12) is connected to a 5V power supply, the ground line (GND) is connected to the ground, the B-to-A output enable pin (OEBA#) is connected to the fifth chip select enable signal line (gpmc_ncs4) of the GPMC bus in the CPU, and the A-to-B output enable pin (OEAB) of the fourth data transceiver (U12) is connected to the output pin (4) of the fourth inverter (U9).

[0027] The low-byte select pin LBR of the right DPRAM U4B is connected to the low-order eight-bit read / write enable pin gpmc_nbe0_cle of the GPMC bus in the CPU, and is also connected to a 3.3V power supply via resistor R11. The high-byte select pin UBR of the right DPRAM U4B is connected to the high-order eight-bit read / write enable pin gpmc_nbe1 of the GPMC bus in the CPU, and is also connected to a 3.3V power supply via resistor R12. The first Right Port chip enable pin CE0R of the right DPRAM U4B is connected to the fifth chip select enable signal line gpmc_ncs4 of the CPU's GPMC bus. The second Right Port chip enable pin CE1R of the right DPRAM U4B is connected to the output pin "4" of inverter U11 (5). The input pin "2" of inverter U11 is connected to the fifth chip select enable signal line gpmc_ncs4 of the CPU's GPMC bus. The power pin "5" of inverter U11 is connected to a 3.3V power supply, and the ground pin "3" is connected to ground GND. The signal flag enable pin SEMR of the right DPRAM U4B is connected to the 3.3V power supply via resistor R10 (10). The read / write enable pin R / WR of the right DPRAM U4B is connected to the CPU's GPMC bus's read / write general control enable pin gpmc_nwe, which is also connected to a 3.3V power supply via resistor R13. The chip output enable pin OER of the right DPRAM U4B is connected to the CPU's GPMC bus's output enable pin gpmc_noe, which is also connected to a 3.3V power supply via resistor R14. The busy flag pin BUSYR of the right DPRAM U4B is connected to the 3.3V power supply via resistor R15, and the interrupt flag pin INTR is connected to the 3.3V power supply via resistor R16.

[0028] In this invention, the CPU model can be AM3517AZER. Its GPMC (General Purpose Memory Controller) bus is a general-purpose memory interface unique to TI processors, supporting devices including SRAM, NOR flash, NAND flash, and ASIC devices. The GPMC bus of this CPU model supports connecting up to eight peripheral devices. When connecting a large number of peripherals, communication errors or even interruptions may occur due to problems such as long PCB wiring lengths, excessive branches, and external interference. To provide the CPU with a larger address space when accessing memory devices, the GPMC bus uses a multiplexing mode for address and data lines. The latch U8 is a D-type latch. The address valid control signal GPMC_NADV_ALE in the GPMC bus can control latch U8 to latch a valid address and pass it to the memory. The peripheral connected to the GPMC bus in this invention is DPRAM (U4, including U4A and U4B), and its model can be 70V28L15PFG. This memory is DPRAM (Dual-Port Static RAM). DPRAM is a dual-port random access memory with two independent ports. Each port has its own independent address bus and data bus, which enables two independent devices to read and write to DPRAM at the same time, that is, two devices can access the same memory unit of DPRAM at the same time. Similarly, two different chip selects of the GPMC bus can be used to connect the two ports of DPRAM respectively.

[0029] In the present invention, the models of the data transceiver No. 1 U3, the data transceiver No. 2 U5, the data transceiver No. 3 U10, and the data transceiver No. 4 U12 can all adopt SN74ALS623ADW, which can realize synchronous bidirectional communication between data buses, and the control function allows maximum timing flexibility, and allows data to be transmitted from the A bus to the B bus or from the B bus to the A bus, depending on the logic level input of its "output enable signal" (that is, the output enable pin OEAB of A to B and the output enable pin OEBA# of B to A). According to the user manual, when the output enable signal of the B-to-A output enable pin OEBA# is high and the output enable signal of the A-to-B output enable pin OEAB is low, the SN74ALS623ADW device is in an isolated state, and all its pins are in a high-impedance state, effectively isolating the bus data line. When the output enable signal of the B-to-A output enable pin OEBA# is low and the output enable signal of the A-to-B output enable pin OEAB is high, the SN74ALS623ADW device is in a bidirectional transmission state, and the GPMC bus and peripheral storage devices can communicate normally. Based on the characteristics of the SN74ALS623ADW, the chip select signal of the GPMC bus can be used as the output enable signal of the SN74ALS623ADW to implement ideal control logic. When reading or writing to a storage device, the GPMC bus first pulls the chip select signal of the corresponding storage device low. That is, when reading or writing to the storage device with chip select 4, the GPMC bus pulls the GPMC_NCS3 signal low. At the same time, inverters U2 and U9 (both of which can be SN74LVC1G14DCKR) are used to invert the GPMC_NCS3 signal to a high level and output it to the OEAB control signals of data transceivers U3 and U5. At this point, data transceivers U3 and U5 are in a bidirectional transmission state, and the GPMC bus can communicate normally with the chip-selected storage device. For other storage devices that are not chip-selected, their GPMC_NCSx (x = 0, 1, 2, ..., 7) signals are high. The GPMC_NCSx (x=0, 1, 2, ..., 7) signal is low, and the data transceiver is in an isolated state, thereby realizing GPMC bus data isolation.

[0030] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A bus isolation circuit based on a data transceiver, comprising a CPU (U1), characterized in that: 16 data line pins of the GPMC bus in the CPU (U1) are connected to the bus data input pins of the latch (U8), and the latch address output pins of the latch (U8) are respectively connected to the address lines of the left part (U4A) of the DPRAM and the address lines of the right part (U4B) of the DPRAM; The first 8 I / O pins of the left portion of the DPRAM (U4A) are connected to the A bus pins of the first data transceiver (U3), and the B bus pins of the first data transceiver (U3) are connected to the first 8 data line pins of the GPMC bus in the CPU (U1); the last 8 I / O pins of the left portion of the DPRAM (U4A) are connected to the A bus pins of the second data transceiver (U5), and the B bus pins of the second data transceiver (U5) are connected to the last 8 data line pins of the GPMC bus in the CPU (U1); The first 8 I / O pins of the right part (U4B) of the DPRAM are connected to the A bus pins of the third data transceiver (U10), and the B bus pins of the third data transceiver (U10) are connected to the first 8 data line pins of the GPMC bus in the CPU (U1); the last 8 I / O pins of the right part (U4B) of the DPRAM are connected to the A bus pins of the fourth data transceiver (U12), and the B bus pins of the fourth data transceiver (U12) are connected to the last 8 data line pins of the GPMC bus in the CPU (U1).

2. The bus isolation circuit based on data transceiver according to claim 1, characterized in that: The latch (U8) is a D-type latch, the latch enable pin of the latch (U8) is connected to the output pin of the first inverter (U6), and the input pin of the first inverter (U6) is connected to the address valid control enable pin of the GPMC bus in the CPU (U1).

3. The bus isolation circuit based on data transceiver according to claim 1, characterized in that: The A-to-B output enable pin of the first data transceiver (U3) and the A-to-B output enable pin of the second data transceiver (U5) are both connected to the output pin of the second inverter (U2); the input pin of the second inverter (U2) is connected to the fourth chip select enable signal line pin of the GPMC bus in the CPU (U1); and the fourth chip select enable signal line pin is also respectively connected to the B-to-A output enable pin of the first data transceiver (U3), the B-to-A output enable pin of the second data transceiver (U5), and the input pin of the third inverter (U7).

4. The bus isolation circuit based on a data transceiver according to claim 1, characterized in that: The chip master mode or slave mode setting pin of the left part (U4A) of the DPRAM is connected to a 3.3V power supply via a resistor (R1), the low byte selection pin is connected to the low eight-bit read and write enable pin of the GPMC bus in the CPU (U1), the high byte selection pin is connected to the high eight-bit read and write enable pin of the GPMC bus in the CPU (U1), the first Left Port chip work enable pin is connected to the 4th chip select enable signal line pin of the GPMC bus in the CPU (U1), and the second Left The port chip work enable pin is connected to the output pin of the third inverter (U7), the signal flag enable pin is connected to the 3.3V power supply through the second resistor (R2), the read / write enable pin is connected to the read and write general control enable pin of the GPMC bus in the CPU (U1), the chip output enable pin is connected to the output enable pin of the GPMC bus in the CPU (U1), the busy flag pin is connected to the 3.3V power supply through the seventh resistor (R7), and the interrupt flag pin is connected to the 3.3V power supply through the eighth resistor (R8).

5. The bus isolation circuit based on data transceiver according to claim 1, characterized in that: The A-to-B output enable pin of the third data transceiver (U10) and the A-to-B output enable pin of the fourth data transceiver (U12) are both connected to the output pin of the fourth inverter (U9); the input pin of the fourth inverter (U9) is connected to the fifth chip select enable signal line pin of the GPMC bus in the CPU (U1); and the fifth chip select enable signal line pin is further connected to the B-to-A output enable pin of the third data transceiver (U10), the B-to-A output enable pin of the fourth data transceiver (U12), and the input pin of the fifth inverter (U11).

6. The bus isolation circuit based on data transceiver according to claim 1, characterized in that: The low byte selection pin of the right part (U4B) of the DPRAM is connected to the low eight-bit read and write enable pins of the GPMC bus in the CPU (U1), the high byte selection pin is connected to the high eight-bit read and write enable pins of the GPMC bus in the CPU (U1), the first Right Port chip work enable pin is connected to the 5th chip select enable signal line pin of the GPMC bus in the CPU (U1), the second Right Port chip work enable pin is connected to the output pin of the fifth inverter (U11), the signal flag enable pin is connected to the 3.3V power supply via the tenth resistor (R10), the read / write enable pin is connected to the read and write general control enable pin of the GPMC bus in the CPU (U1), the chip output enable pin is connected to the output enable pin of the GPMC bus in the CPU (U1), the busy flag pin is connected to the 3.3V power supply via the fifteenth resistor (R15), and the interrupt flag pin is connected to the 3.3V power supply via the sixteenth resistor (R16).

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