Circuit board, circuit board assembly and electronic equipment

Abstract

The utility model discloses a circuit board, a circuit board assembly and electronic equipment. The circuit board comprises a circuit board body, the circuit board body comprises a plurality of wiring layers and a plurality of first insulating medium layers, the plurality of first insulating medium layers are stacked, and one wiring layer is arranged between any two adjacent first insulating medium layers; a first pad; in the two first insulating dielectric layers on the outermost side, the outer surface of at least one first insulating dielectric layer is provided with a first groove, the first bonding pad is arranged in the first groove, and the end face, deviating from the bottom of the first groove, of the first bonding pad is coplanar with the end face, deviating from the wiring layer, of the first insulating dielectric layer.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic devices, and specifically relates to a circuit board, a circuit board assembly, and an electronic device. Background Art

[0002] With the continuous innovation of new mobile phone technologies, mobile phone designs have become increasingly diverse. Foldable phones are also becoming increasingly popular, with more and more users turning to foldable screen phones. To enhance product competitiveness and attract consumer orders, mobile phone manufacturers are actively launching ultra-thin foldable models. To achieve the goal of achieving the millimeter-thin era of overall device thinning, various terminals are extremely reducing the thickness of printed circuit boards.

[0003] As printed circuit boards become thinner, their ability to withstand external forces decreases dramatically. External forces are transmitted layer by layer, concentrating on the PCB and generating localized high stress. This stress then propagates along the edges of the pads to the insulating dielectric layer of the PCB, causing cracks in the pads and malfunctioning of the phone. Utility Model Content

[0004] The present application aims to provide a circuit board, a circuit board assembly and an electronic device, which solve one of the problems in the related art that the printed circuit board's ability to resist external forces decreases due to thinning of the printed circuit board.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a circuit board, comprising: a circuit board body, the circuit board body comprising multiple routing layers and multiple first insulating dielectric layers, the multiple first insulating dielectric layers being stacked, and a routing layer being arranged between any two adjacent first insulating dielectric layers; a first solder pad; among the two outermost first insulating dielectric layers, at least one first insulating dielectric layer having an outer surface provided with a first groove, the first solder pad being arranged in the first groove, and the end face of the first solder pad facing away from the bottom of the first groove being coplanar with the end face of the first insulating dielectric layer facing away from the routing layer.

[0007] In a second aspect, an embodiment of the present application provides a circuit board assembly, comprising: a chip; and a circuit board as in the first aspect, wherein the chip is stacked on one side of the circuit board, the chip has a second solder pad, and the first solder pad and the second solder pad are connected by a soldering portion.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, including: a power supply; and the circuit board in the first aspect, wherein the circuit board is electrically connected to the power supply.

[0009] In an embodiment of the present application, the circuit board includes a circuit board body and a first solder pad.

[0010] The circuit board body includes a plurality of wiring layers and a plurality of first insulating medium layers. The plurality of wiring layers are stacked, the plurality of first insulating medium layers are stacked, and a wiring layer is arranged between any two adjacent first insulating medium layers.

[0011] Of the two outermost first insulating dielectric layers, at least one first insulating dielectric layer has a first groove on its outer surface. That is, one first insulating dielectric layer has a first groove on its outer surface. Alternatively, both first insulating dielectric layers have first grooves on their outer surfaces.

[0012] The first pad is disposed within the first groove, which serves to mount and secure the first pad. The end surface of the first pad facing away from the bottom of the first groove is coplanar with the end surface of the first insulating dielectric layer facing away from the routing layer. This further defines the mating structure between the first pad and the first insulating dielectric layer. It is understood that the first pad is electrically connected to the routing layer.

[0013] In related art, at least a portion of the pad protrudes beyond the side of the insulating dielectric layer facing away from the trace layer. After soldering, the solder wraps around the exposed side of the pad. Furthermore, due to the thickness of the solder resist, the solder is thicker overall. When external stress is transmitted to the pad, it shears at the junction between the bottom of the pad and the insulating dielectric layer. The insulating dielectric layer has a low stress resistance, which can cause cracks in the pad and lead to PCB failure.

[0014] In the present application, the first pad is embedded in the first groove, that is, the first pad is embedded in the first insulating medium layer, and only the end face of the first pad facing away from the bottom of the first groove is exposed to the outside air. When the circuit board is welded to other devices, the welding part (such as solder) is only surface-welded to the end face of the first pad facing away from the bottom of the first groove. In this way, when external stress is transmitted to the welding position of the first pad, the stress will be concentrated between the solder and the first pad, and the stress shear direction points to the center of the first pad. Since the stress resistance of the solder and the first pad is much greater than that of the first insulating medium layer, the stress resistance of the first pad is greatly increased, which can fundamentally improve the anti-cracking ability of the first pad, greatly reducing the risk of cracking of the circuit board due to stress, which is conducive to improving the service life of the circuit board.

[0015] At the same time, the first solder pad is embedded in the first insulating dielectric layer, which rationally utilizes the existing structure of the first insulating dielectric layer. While ensuring the effectiveness and feasibility of installing and fixing the first solder pad, it can also reduce the overall thickness of the circuit board body and the first solder pad after assembly, further reducing the thickness of the circuit board while ensuring the performance of the circuit board.

[0016] It is understandable that the first pad is embedded in the first insulating dielectric layer, and the first insulating dielectric layer located on the peripheral side of the first pad can act as a solder resist. In this way, the material input of the solder resist can be reduced, the processing steps of the circuit board can be simplified, and the production cost of the circuit board can be reduced. At the same time, this setting fundamentally avoids the height difference between the side of the first insulating dielectric layer facing away from the wiring layer and the first pad, thereby reducing the amount of tin applied during soldering. While reducing the height of the solder joint (approximately 30μm to 70μm), the amount of solder used is saved, and because the cross-sectional aspect ratio of the solder is reduced, the stress resistance of the soldering position is further increased.

[0017] Furthermore, because the first pads are embedded in the first insulating dielectric layer, which has much higher weather resistance, electromigration resistance, and penetration resistance than the surface solder resist, the spacing between surface traces can be further reduced, significantly improving the layout space utilization of the circuit board. This can achieve the goal of reducing the size of the circuit board and reduce the internal space occupied by the circuit board in the electronic device, providing structural support for increasing the installation space for batteries, cameras, etc. in the electronic device, which is conducive to improving the performance and market competitiveness of the electronic device.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 This is a partial structural diagram of a circuit board according to an embodiment of the present application;

[0021] Figure 2 This is a partial structural diagram of a circuit board assembly according to an embodiment of the present application;

[0022] Figure 3 This is a schematic structural diagram of the circuit board after the first processing step of the first embodiment of the present application;

[0023] Figure 4 This is a schematic structural diagram of the circuit board after the second processing step of the first embodiment of the present application;

[0024] Figure 5 is a schematic structural diagram of the circuit board after the third processing step of the first embodiment of the present application;

[0025] Figure 6 is a schematic structural diagram of the circuit board after the fourth processing step of the first embodiment of the present application;

[0026] Figure 7 is a schematic structural diagram of the circuit board after the fifth processing step of the first embodiment of the present application;

[0027] Figure 8 is a schematic structural diagram of the circuit board after the sixth processing step of the first embodiment of the present application;

[0028] Figure 9 is a schematic structural diagram of a circuit board after the first processing step according to the second embodiment of the present application;

[0029] Figure 10 is a schematic structural diagram of a circuit board after the second processing step according to the second embodiment of the present application;

[0030] Figure 11 This is a schematic structural diagram of the circuit board after the third processing step of the second embodiment of the present application.

[0031] Reference numerals:

[0032] Figures 1 to 11 The corresponding relationship between the reference numerals and component names is as follows:

[0033] 10 circuit board, 100 circuit board body, 110 routing layer, 120 first insulating dielectric layer, 122 first groove, 1222 bottom of the first groove, 1224 notch of the first groove, 124 second groove, 1242 notch of the second groove, 1244 bottom of the second groove, 130 first conductive layer, 140 carrier board, 150 first intermediate conductive layer, 160 circuit mask, 170 second intermediate conductive layer, 180 conductive hole, 190 intermediate insulating dielectric layer, 200 first soldering pad, 300 signal transmission part, 400 solder resist part, 50 circuit board assembly, 500 chip, 510 second insulating dielectric layer, 512 third groove, 5122 bottom of the third groove, 5124 notch of the third groove, 520 second soldering pad, 530 second conductive layer, 800 soldering part. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly refer to one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more. Furthermore, "and / or" in the specification and claims refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0036] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0038] The following is combined with Figures 1 to 11 The circuit board 10, circuit board assembly 50 and electronic device provided in the embodiments of the present application are described.

[0039] like Figure 1 As shown, the circuit board 10 according to some embodiments of the present application includes: a circuit board body 100, the circuit board body 100 includes multiple routing layers 110 and multiple first insulating dielectric layers 120, the multiple first insulating dielectric layers 120 are stacked, and a routing layer 110 is arranged between any two adjacent first insulating dielectric layers 120; a first solder pad 200; among the two outermost first insulating dielectric layers 120, the outer surface of at least one first insulating dielectric layer 120 is provided with a first groove 122, the first solder pad 200 is arranged in the first groove 122, and the end face of the first solder pad 200 facing away from the groove bottom 1222 of the first groove is coplanar with the end face of the first insulating dielectric layer 120 facing away from the routing layer 110.

[0040] In the embodiment of the present application, the circuit board 10 includes a circuit board body 100 and a first solder pad 200 .

[0041] The circuit board body 100 includes multiple wiring layers 110 and multiple first insulating dielectric layers 120. The multiple wiring layers 110 are stacked, and the multiple first insulating dielectric layers 120 are stacked. There is one wiring layer 110 between any two adjacent first insulating dielectric layers 120.

[0042] Of the two outermost first insulating dielectric layers 120, at least one first insulating dielectric layer 120 has a first groove 122 on its outer surface. That is, the outer surface of one first insulating dielectric layer 120 has a first groove 122. Alternatively, the outer surfaces of both first insulating dielectric layers 120 have a first groove 122.

[0043] The first pad 200 is disposed in the first groove 122, which serves to mount and secure the first pad 200. The end surface of the first pad 200 facing away from the groove bottom 1222 of the first groove is coplanar with the end surface of the first insulating dielectric layer 120 facing away from the routing layer 110. This further defines the mating structure between the first pad 200 and the first insulating dielectric layer 120. It is understood that the first pad 200 is electrically connected to the routing layer 110.

[0044] In related art, at least a portion of the pad protrudes from the side of the insulating dielectric layer facing away from the trace layer. After soldering, the solder wraps around the side of the pad exposed to the air. Due to the thickness of the solder, the overall thickness of the solder after soldering is relatively thick. When external stress is transmitted to the pad, the stress is sheared at the connection between the bottom of the pad and the insulating dielectric layer. The insulating dielectric layer has a low stress resistance, which can cause cracks in the pad and lead to malfunction of the printed circuit board.

[0045] In the present application, the first solder pad 200 is embedded in the first groove 122, that is, the first solder pad 200 is embedded in the first insulating dielectric layer 120, and only the end face of the first solder pad 200 that is away from the groove bottom 1222 of the first groove is exposed to the outside air. When the circuit board 10 is welded to other devices, the welding portion 800 (such as solder) is only surface-welded to the end face of the first solder pad 200 that is away from the groove bottom 1222 of the first groove. In this way, when external stress is transmitted to the welding position of the first solder pad 200, the stress will be concentrated between the solder and the first solder pad 200, and the stress shear direction is directed to the center of the first solder pad 200. Since the stress resistance of the solder and the first solder pad 200 is much greater than that of the first insulating dielectric layer 120, the stress resistance of the first solder pad 200 is greatly increased, which can fundamentally improve the anti-cracking ability of the first solder pad 200, greatly reducing the risk of cracking of the circuit board 10 due to stress, and improving the service life of the circuit board 10.

[0046] At the same time, the first solder pad 200 is embedded in the first insulating medium layer 120, which rationally utilizes the existing structure of the first insulating medium layer 120. While ensuring the effectiveness and feasibility of installing and fixing the first solder pad 200, it can also reduce the overall thickness of the circuit board body 100 and the first solder pad 200 after assembly, further reducing the thickness of the circuit board 10 while ensuring the performance of the circuit board 10.

[0047] It is understandable that the first solder pad 200 is embedded in the first insulating dielectric layer 120, and the first insulating dielectric layer 120 located on the side of the first solder pad 200 can play the role of the solder resist 400. In this way, the material input of the solder resist 400 can be reduced, the processing steps of the circuit board 10 can be simplified, and the production cost of the circuit board 10 can be reduced. At the same time, this setting fundamentally avoids the height difference between the side of the first insulating dielectric layer 120 facing away from the wiring layer 110 and the first solder pad 200, thereby reducing the amount of tin applied during soldering. While reducing the height of the solder joint (approximately 30μm to 70μm), the amount of solder used is saved, and because the cross-sectional aspect ratio of the solder is reduced, the stress resistance of the soldering position is further increased.

[0048] Furthermore, because the first solder pads 200 are embedded in the first insulating dielectric layer 120, and the first insulating dielectric layer 120 has much higher weather resistance, electromigration resistance, and penetration resistance than the surface solder resist, the spacing between surface traces can be further reduced, thereby significantly improving the layout space utilization of the circuit board 10. This can achieve the goal of reducing the volume of the circuit board 10 and reduce the internal space occupied by the circuit board 10 in the electronic device, providing structural support for increasing the installation space for batteries, cameras, etc. in the electronic device, thereby improving the performance and market competitiveness of the electronic device.

[0049] It is understood that the end surface of the first pad 200 facing away from the bottom 1222 of the first groove is coplanar with the end surface of the first insulating dielectric layer 120 facing away from the wiring layer 110. In other words, the end surface of the first pad 200 facing away from the bottom 1222 of the first groove and the end surface of the first insulating dielectric layer 120 facing away from the wiring layer 110 are located in the same plane.

[0050] In some embodiments, as Figure 1 As shown, the outer surface of the first solder pad 200 is arranged to fit the groove wall of the first groove 122; along the groove opening 1224 of the first groove to the groove bottom 1222 of the first groove, the cross-sectional area of ​​the first solder pad 200 gradually increases, and the cross-sectional area of ​​the first solder pad 200 is perpendicular to the stacking direction of multiple first insulating medium layers 120.

[0051] In this embodiment, the matching structure between the first pad 200 and the first insulating dielectric layer 120 is further defined.

[0052] The outer surface of the first solder pad 200 is arranged to fit the groove wall of the first groove 122 , that is, the shape of the first solder pad 200 is adapted to the shape of the first groove 122 .

[0053] like Figure 2 As shown, when external stress is transmitted to the soldering position of the first pad 200, the stress is concentrated between the solder and the first pad 200, and the stress shear direction points to the center of the first pad 200. Figure 2 The arrows in the figure indicate the direction of stress transmission.

[0054] By rationally designing the shapes of the first pad 200 and the first groove 122, the cross-sectional area of ​​the first pad 200 gradually increases from the notch 1224 of the first groove to the bottom 1222 of the first groove. The cross-sectional area of ​​the first pad 200 is perpendicular to the stacking direction of the multiple first insulating dielectric layers 120. This shape of the first pad 200 is opposite to the direction of shear stress. This leverage further enhances the strain resistance of the first pad 200, further reducing the risk of stress-induced cracking of the circuit board 10 and thereby increasing the service life of the circuit board 10.

[0055] Alternatively, as Figure 1 As shown, the longitudinal section of the first pad 200 is a trapezoid. From the notch 1224 of the first groove to the bottom 1222 of the first groove, the cross-section of the first pad 200 gradually increases. This cross-section can be understood as the cross section of the first pad 200.

[0056] In some embodiments, there are multiple first grooves 122 and multiple first pads 200 . Each first pad 200 is disposed in one first groove 122 , and multiple first grooves 122 are arranged at intervals.

[0057] In this embodiment, the number and matching structure of the first pads 200 and the first grooves 122 are further defined.

[0058] There are multiple first grooves 122 and multiple first pads 200 . The multiple first grooves 122 are arranged at intervals. Each first pad 200 is disposed in a first groove 122 . Each first pad 200 is electrically connected to the routing layer 110 through a conductive hole 180 .

[0059] It is understood that the portion of the first insulating dielectric layer 120 located between two adjacent first grooves 122 functions as a solder resist, thereby meeting the safety requirements of the circuit board 10. This configuration can reduce the material input for the solder resist portion 400, simplify the processing steps of the circuit board 10, and thus reduce the production cost of the circuit board 10.

[0060] In some embodiments, as Figure 1As shown, among the two outermost first insulating dielectric layers 120, at least one first insulating dielectric layer 120 is provided with a second groove 124 on the side facing away from the routing layer 110; the circuit board 10 also includes a signal transmission part 300, the signal transmission part 300 is provided in the second groove 124, and the end face of the signal transmission part 300 facing away from the groove bottom 1244 of the second groove is coplanar with the end face of the first insulating dielectric layer 120 facing away from the routing layer 110.

[0061] In this embodiment, the structure of the circuit board 10 is further defined.

[0062] Of the two outermost first insulating dielectric layers 120, at least one first insulating dielectric layer 120 has a second groove 124 on a side facing away from the routing layer 110. That is, one first insulating dielectric layer 120 has a second groove 124 on a side facing away from the routing layer 110. Alternatively, both first insulating dielectric layers 120 have a second groove 124 on a side facing away from the routing layer 110.

[0063] The circuit board 10 also includes a signal transmission unit 300 for transmitting signals. The signal transmission unit 300 is disposed in the second groove 124, which serves to mount and secure the signal transmission unit 300. The end surface of the signal transmission unit 300 facing away from the groove bottom 1244 of the second groove is coplanar with the end surface of the first insulating dielectric layer 120 facing away from the routing layer 110. It is understood that the signal transmission unit 300 is electrically connected to the routing layer 110.

[0064] In related art, at least a portion of the signal transmission unit protrudes from the side of the insulating dielectric layer facing away from the routing layer. The solder resist wraps around the side of the signal transmission unit exposed to air. Due to the thickness of the solder resist, the overall thickness after soldering is relatively thick. When external stress is transmitted to the signal transmission unit, the stress is sheared at the junction between the bottom of the signal transmission unit and the insulating dielectric layer. The insulating dielectric layer has a low stress resistance, which can cause cracks in the signal transmission unit, leading to PCB failure.

[0065] In the present application, the signal transmission part 300 is embedded in the second groove 124, that is, the signal transmission part 300 is embedded in the first insulating dielectric layer 120, and only the end face of the signal transmission part 300 that is away from the groove bottom 1244 of the second groove is exposed to the outside air. When the signal transmission part 300 is welded to the solder resist part 400, the solder resist part 400 is only surface-welded to the end face of the signal transmission part 300 that is away from the groove bottom 1244 of the second groove. In this way, when external stress is transmitted to the welding position of the signal transmission part 300, the stress shear direction points to the center of the signal transmission part 300. Since the stress resistance of the signal transmission part 300 is much greater than that of the first insulating dielectric layer 120, the stress resistance of the signal transmission part 300 is greatly increased, which can fundamentally improve the anti-cracking ability of the signal transmission part 300, greatly reducing the risk of cracking of the circuit board 10 due to stress, and improving the service life of the circuit board 10.

[0066] At the same time, the signal transmission part 300 is embedded in the first insulating medium layer 120, which rationally utilizes the existing structure of the first insulating medium layer 120. While ensuring the effectiveness and feasibility of installing and fixing the signal transmission part 300, it is also beneficial to thin the thickness of the solder mask part 400, thereby further thinning the thickness of the circuit board 10 while ensuring the performance of the circuit board 10.

[0067] It is understood that the end surface of the signal transmission portion 300 facing away from the groove bottom 1244 of the second groove is coplanar with the end surface of the first insulating dielectric layer 120 facing away from the wiring layer 110. In other words, the end surface of the signal transmission portion 300 facing away from the groove bottom 1244 of the second groove and the end surface of the first insulating dielectric layer 120 facing away from the wiring layer 110 are located in the same plane.

[0068] In some embodiments, as Figure 1 As shown, the outer surface of the signal transmission part 300 is arranged to fit the groove wall of the second groove 124; along the groove opening 1242 of the second groove to the groove bottom 1244 of the second groove, the cross-sectional area of ​​the signal transmission part 300 gradually increases, and the cross-sectional area of ​​the signal transmission part 300 is perpendicular to the stacking direction of the multiple first insulating medium layers 120.

[0069] In this embodiment, the matching structure between the signal transmission portion 300 and the first insulating dielectric layer 120 is further defined.

[0070] The outer surface of the signal transmission portion 300 is arranged to fit the groove wall of the second groove 124 , that is, the shape of the signal transmission portion 300 is adapted to the shape of the second groove 124 .

[0071] When external stress is transmitted to the soldering position of the signal transmission part 300 , the stress shearing direction is directed toward the center of the signal transmission part 300 .

[0072] By rationally designing the shapes of the signal transmission portion 300 and the second groove 124, the cross-sectional area of ​​the signal transmission portion 300 gradually increases from the notch 1242 of the second groove to the bottom 1244 of the second groove. The cross-sectional area of ​​the signal transmission portion 300 is perpendicular to the stacking direction of the multiple first insulating dielectric layers 120. This shape of the signal transmission portion 300 opposes the direction of shear stress. This leverage further enhances the strain resistance of the signal transmission portion 300, reduces the risk of stress-induced cracking in the circuit board 10, and improves the service life of the circuit board 10.

[0073] Alternatively, as Figure 1 As shown, the longitudinal section of the signal transmission part 300 is trapezoidal. From the notch 1242 of the second groove to the groove bottom 1244 of the second groove, the cross-section area of ​​the signal transmission part 300 gradually increases. This cross-section can be understood as the cross section of the signal transmission part 300.

[0074] In some embodiments, as Figure 1 As shown, the circuit board 10 further includes: a solder resist portion 400 , which is disposed on a side of the signal transmission portion 300 away from the wiring layer 110 .

[0075] In this embodiment, the structure of the circuit board 10 is further defined.

[0076] The circuit board 10 further includes a solder resist portion 400 . The solder resist portion 400 is disposed on a side of the signal transmission portion 300 facing away from the wiring layer 110 to ensure safety requirements of the circuit board 10 .

[0077] Since the end face of the signal transmission part 300 facing away from the bottom 1244 of the second groove is coplanar with the end face of the first insulating medium layer 120 facing away from the wiring layer 110, the thickness of the solder resist part 400 provided on the side of the signal transmission part 300 facing away from the wiring layer 110 is smaller than the solder resist part that needs to cover the top and side of the signal transmission part in the related art. In this way, the thickness of the circuit board 10 can be further reduced.

[0078] In some embodiments, there are multiple second grooves 124 and multiple signal transmission parts 300 . Each signal transmission part 300 is disposed in one second groove 124 . Multiple second grooves 124 are arranged at intervals, and the solder resist 400 covers multiple signal transmission parts 300 .

[0079] In this embodiment, the matching structure of the signal transmission portion 300 , the second groove 124 and the solder resist portion 400 is further defined.

[0080] There are multiple second grooves 124 and multiple signal transmission parts 300. The multiple second grooves 124 are arranged at intervals. Each signal transmission part 300 is provided in a second groove 124. Each signal transmission part 300 is electrically connected to the routing layer 110 through a conductive hole 180.

[0081] In addition, the solder resist portion 400 covers the plurality of signal transmission portions 300. Since the end surfaces of the plurality of signal transmission portions 300 facing away from the groove bottom 1244 of the second groove are coplanar with the end surface of the first insulating dielectric layer 120 facing away from the wiring layer 110, the solder resist portion 400 can be a flat layer structure. This not only ensures safety regulations but also helps to reduce the thickness of the solder resist portion 400, reducing the material input of the solder resist portion 400, thereby helping to reduce the production cost of the circuit board 10.

[0082] like Figure 2 As shown, according to some other embodiments of the present application, the circuit board assembly 50 includes: a chip 500; and a circuit board 10 as in any of the above embodiments, the chip 500 is stacked on one side of the circuit board 10, the chip 500 has a second solder pad 520, and the first solder pad 200 and the second solder pad 520 are connected by a welding portion 800.

[0083] The circuit board assembly 50 provided in the present application includes a chip 500 and a circuit board 10. Since the circuit board assembly 50 includes the circuit board 10 of any of the above embodiments, it has all the beneficial effects of the above circuit board 10, which will not be described one by one here.

[0084] It can be understood that the chip 500 has a second pad 520 , and the first pad 200 and the second pad 520 are connected via the soldering portion 800 to achieve electrical connection between the chip 500 and the circuit board 10 .

[0085] Alternatively, as Figure 2 As shown, the circuit board 10 further includes a first conductive layer 130 , and the chip 500 further includes a second conductive layer 530 .

[0086] In some embodiments, as Figure 2 As shown, the chip 500 includes: a second insulating dielectric layer 510, and a third groove 512 is provided on the side of the second insulating dielectric layer 510 facing the circuit board 10; a second solder pad 520 is provided in the third groove 512, and the end surface of the second solder pad 520 facing the circuit board 10 is coplanar with the end surface of the second insulating dielectric layer 510 facing the circuit board 10.

[0087] In this embodiment, the structure of the chip 500 is further defined.

[0088] The chip 500 includes a second insulating dielectric layer 510 and a second pad 520 .

[0089] A third groove 512 is defined on the side of the second insulating dielectric layer 510 facing the circuit board 10, and a second solder pad 520 is disposed within the third groove 512. The third groove 512 serves to mount and secure the second solder pad 520. The end surface of the second solder pad 520 facing the circuit board 10 is coplanar with the end surface of the second insulating dielectric layer 510 facing the circuit board 10.

[0090] The second solder pad 520 is embedded in the third groove 512, that is, the second solder pad 520 is embedded in the second insulating dielectric layer 510, and only the end surface of the second solder pad 520 that is away from the groove bottom 5122 of the third groove is exposed to the outside air. When the circuit board 10 is welded to the chip 500, the welding portion 800 (such as solder) is only surface-welded to the end surface of the second solder pad 520 that is away from the groove bottom 5122 of the third groove. In this way, when external stress is transmitted to the welding position of the second solder pad 520, the stress will be concentrated between the solder and the second solder pad 520, and the stress shear direction is directed to the center of the second solder pad 520. Since the stress resistance of the solder and the second solder pad 520 is much greater than that of the second insulating dielectric layer 510, the stress resistance of the second solder pad 520 is greatly increased, which can fundamentally improve the anti-cracking ability of the second solder pad 520, greatly reducing the risk of the chip 500 cracking due to stress.

[0091] This arrangement also fundamentally avoids the height difference between the second insulating dielectric layer 510 and the second solder pad 520, thereby reducing the amount of solder applied during soldering. While reducing the height of the solder joint, it also saves on solder usage. Furthermore, because the cross-sectional aspect ratio of the solder is reduced, the stress resistance of the soldering location is further increased.

[0092] It is understood that the end surface of the second pad 520 facing the circuit board 10 is coplanar with the end surface of the second insulating dielectric layer 510 facing the circuit board 10. In other words, the end surface of the second pad 520 facing the circuit board 10 and the end surface of the second insulating dielectric layer 510 facing the circuit board 10 are located in the same plane.

[0093] In some embodiments, as Figure 2 As shown, the outer surface of the second solder pad 520 is arranged to fit the wall of the third groove 512; along the groove opening 5124 of the third groove to the groove bottom 5122 of the third groove, the cross-sectional area of ​​the second solder pad 520 gradually increases, and the cross-sectional area of ​​the second solder pad 520 is perpendicular to the thickness direction of the chip 500.

[0094] In this embodiment, the matching structure between the second pad 520 and the second insulating dielectric layer 510 is further defined.

[0095] The outer surface of the second solder pad 520 is arranged to fit the groove wall of the third groove 512 , that is, the shape of the second solder pad 520 is adapted to the shape of the third groove 512 .

[0096] When external stress is transmitted to the soldering position of the second soldering pad 520 , the stress is concentrated between the soldering portion 800 and the second soldering pad 520 , and the stress shear direction points to the center of the second soldering pad 520 .

[0097] By rationally designing the shapes of the second pad 520 and the third groove 512, the cross-sectional area of ​​the second pad 520 gradually increases from the notch 5124 of the third groove to the bottom 5122 of the third groove. The cross-sectional area of ​​the second pad 520 is perpendicular to the thickness direction of the chip 500. In this way, the shape of the second pad 520 is opposite to the direction of shear stress. Under the action of leverage, the strain resistance of the second pad 520 is further improved, which can further reduce the risk of chip 500 cracking due to stress, thereby improving the service life of the chip 500.

[0098] According to some further embodiments of the present application, electronic devices include: a power supply; and a circuit board 10 as in any of the above embodiments, wherein the circuit board 10 is electrically connected to the power supply.

[0099] Since the electronic device provided in the present application includes the circuit board 10 of any of the above embodiments, it has all the beneficial effects of the above circuit board 10, which will not be described one by one here.

[0100] In some other embodiments, the electronic device includes the circuit board assembly 50 according to any of the above embodiments.

[0101] Optionally, the electronic device may be a mobile terminal such as a mobile phone, a wearable device, a tablet computer, a laptop computer, a mobile computer, an augmented reality device (also known as an AR (Augmented Reality) device), a virtual reality device (also known as a VR (Virtual Reality) device) and a handheld game console, etc.

[0102] The first solder pad 200 (e.g., a truncated cone-shaped solder pad) of the present application is embedded in the first insulating dielectric layer 120. The longitudinal cross-sections of the first solder pad 200 and the signal transmission portion 300 on the surface of the circuit board 10 are both trapezoidal. Only the end surface of the first solder pad 200 facing away from the bottom 1222 of the first groove is exposed to the outside air, and only the end surface of the signal transmission portion 300 facing away from the bottom 1244 of the second groove is exposed to the outside air.

[0103] The soldering portion 800 (e.g., solder) is only bonded to the top of the first pad 200, while the sides and bottom of the first pad 200 are completely embedded in the first insulating dielectric layer 120. When external stress is transmitted to the soldering position of the first pad 200, the stress is concentrated between the solder and the first pad 200, and the stress shear direction is toward the center of the first pad 200. The shape of the first pad 200 is opposite to the stress shear direction. This fundamentally improves the first pad 200's ability to resist pitting and cracking, greatly reducing the risk of stress-induced cracking in the circuit board 10, and thus helping to extend the service life of the circuit board 10.

[0104] The first solder pad 200 is embedded in the first insulating medium layer 120 , which not only ensures the effectiveness and feasibility of installing and fixing the first solder pad 200 , but also reduces the overall thickness of the assembled circuit board body 100 and the first solder pad 200 , and can reduce the thickness of the circuit board 10 by 50 μm.

[0105] The first solder pad 200 is embedded in the first insulating dielectric layer 120. The outermost end surface of the first insulating dielectric layer 120, facing away from the trace layer 110, is flat, fundamentally avoiding the problem of uneven surface solder resist, thereby reducing the amount of solder applied during soldering. This reduces solder joint height (approximately 30μm to 70μm), saves solder paste usage, and reduces product production costs. Furthermore, because the cross-sectional aspect ratio of the solder is reduced, the stress resistance of the soldering point is further increased.

[0106] Both the first solder pad 200 and the signal transmission portion 300 are embedded in the first insulating dielectric layer 120. The first insulating dielectric layer 120 has much higher weather resistance, electromigration resistance, and penetration resistance than the surface solder resist. This allows the spacing between surface traces to be reduced from 70 μm to 40 μm, significantly improving the layout space utilization of the circuit board 10. This reduces the size of the circuit board 10, provides structural support for increasing the installation space for batteries, cameras, and other components in electronic devices, and improves the performance and market competitiveness of electronic devices.

[0107] Optionally, the shape of the first pad 200 of the present application includes any one of the following: a truncated cone shape, a square cone shape, and a multi-faceted cone shape. The longitudinal section of the first pad 200 is a trapezoidal shape.

[0108] Optionally, the shape of the signal transmission part 300 of the present application includes any one of the following: a truncated cone shape, a square cone shape, and a multi-faceted cone shape. The shape of the longitudinal section of the signal transmission part 300 is a trapezoid.

[0109] Optionally, the second pad 520 of the present application has any one of the following shapes: a truncated cone shape, a square cone shape, and a multi-faceted cone shape. The longitudinal section of the second pad 520 is a trapezoidal shape.

[0110] By embedding the first pad 200 and the signal transmission unit 300 in the first insulating dielectric layer 120, the thickness of the circuit board 10 can be reduced, and the uniformity of the mounting surface can be improved. The improved uniformity of the mounting surface further brings the benefit of reducing the solder height.

[0111] This application rationally designs the shape of the first pad 200 and the matching structure between the first pad 200 and the first insulating dielectric layer 120, so that the first pad 200 is positioned within the first groove 122 of the first insulating dielectric layer 120, and the cross-sectional area of ​​the first pad 200 gradually increases from the notch 1224 of the first groove to the bottom 1222 of the first groove. This arrangement shifts the high-stress area of ​​the first pad 200 to the surface of the first pad 200, and the tilt direction of the first pad 200 is opposite to the direction of external shear force, thereby utilizing the principle of leverage to solve the pad cracking problem in related technologies.

[0112] Optionally, the thickness of the solder resist 400 of the present application is 5 μm.

[0113] In related art, the spacing between two adjacent pads and the spacing between two adjacent signal lines are both relatively large (e.g., the spacing between two adjacent pads is greater than or equal to 120 μm, and the spacing between two adjacent signal lines is greater than or equal to 60 μm). However, the present application can reduce the spacing between two adjacent first pads 200 to less than 40 μm, and the spacing between two adjacent signal transmission parts 300 to less than 40 μm, thereby improving layout density.

[0114] In the present application, the first solder pad 200 is embedded in the first groove 122 of the first insulating dielectric layer 120. The strength, toughness, and aging resistance of the cured first insulating dielectric layer 120 are much higher than those of the solder resist, thereby improving the stress resistance of the first solder pad 200. Furthermore, by embedding the first solder pad 200 and the signal transmission portion 300, the overall thickness of the circuit board 10 can be reduced.

[0115] The first method of processing the circuit board 10 is as follows:

[0116] like Figure 3 As shown, in the first step, a first intermediate conductive layer 150 (eg, 3 μm ultra-thin copper) is attached to the carrier plate 140 ;

[0117] like Figure 4 As shown, in the second step, a regular trapezoidal line mask 160 is processed on the first intermediate conductive layer 150;

[0118] like Figure 5As shown, in the third step, the gaps between the circuit masks 160 are filled by electroplating to produce a second intermediate conductive layer 170 with an inverted trapezoidal cross section (the second intermediate conductive layer 170 is used to form the first pad 200 and the signal transmission portion 300);

[0119] like Figure 6 As shown, in the fourth step, the circuit mask 160 is stripped to expose the second intermediate conductive layer 170 having an inverted trapezoidal cross section;

[0120] like Figure 7 As shown, in the fifth step, the surface layer of the first solder pad 200 and the signal transmission portion 300 processed with an inverted trapezoidal cross section is reversely pressed onto the inner circuit board;

[0121] like Figure 8 As shown, in the sixth step, the carrier plate 140 is separated and the conductive holes 180 on the surface are processed to achieve conduction, and finally the entire plate is etched to expose the first pads 200.

[0122] The second method of processing the circuit board 10 is as follows:

[0123] like Figure 9 As shown, the first step is to complete the surface pad and circuit processing according to the circuit board process flow in the relevant technology.

[0124] like Figure 10 As shown, in the second step, an intermediate insulating dielectric layer 190 is laminated on the surface layer;

[0125] like Figure 11 As shown, in the third step, the redundant intermediate insulating dielectric layer 190 is removed by grinding and plasma desmearing to expose the first pad 200 .

[0126] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0127] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A circuit board, characterized in that: include: A circuit board body, the circuit board body comprising a plurality of wiring layers and a plurality of first insulating dielectric layers, the plurality of first insulating dielectric layers being stacked, and a wiring layer being disposed between any two adjacent first insulating dielectric layers; a first pad; Among the two outermost first insulating dielectric layers, at least one of the first insulating dielectric layers has a first groove on its outer surface, the first solder pad is arranged in the first groove, and the end surface of the first solder pad facing away from the bottom of the first groove is coplanar with the end surface of the first insulating dielectric layer facing away from the routing layer.

2. The circuit board according to claim 1, wherein: The outer surface of the first pad is arranged to fit the groove wall of the first groove; The cross-sectional area of ​​the first pad gradually increases from the opening of the first groove to the bottom of the first groove, and the cross-sectional area of ​​the first pad is perpendicular to the stacking direction of the plurality of first insulating medium layers.

3. The circuit board according to claim 1 or 2, characterized in that: Among the two outermost first insulating dielectric layers, at least one of the first insulating dielectric layers is provided with a second groove on a side facing away from the routing layer; The circuit board further includes a signal transmission portion, which is disposed in the second groove. An end surface of the signal transmission portion facing away from the groove bottom of the second groove is coplanar with an end surface of the first insulating medium layer facing away from the routing layer.

4. The circuit board according to claim 3, wherein: The outer surface of the signal transmission portion is arranged to fit the groove wall of the second groove; The cross-sectional area of ​​the signal transmission portion gradually increases from the notch of the second groove to the bottom of the second groove, and the cross-sectional area of ​​the signal transmission portion is perpendicular to the stacking direction of the plurality of first insulating dielectric layers.

5. The circuit board according to claim 4, wherein: Also includes: The solder resist portion is arranged on a side of the signal transmission portion away from the wiring layer.

6. The circuit board according to claim 5, characterized in that There are multiple first grooves and multiple first pads, each first pad is provided in one first groove, and multiple first grooves are arranged at intervals; and / or There are multiple second grooves and multiple signal transmission parts. Each signal transmission part is provided in one second groove. Multiple second grooves are arranged at intervals. The solder resist part covers the multiple signal transmission parts.

7. A circuit board assembly, characterized in that: include: chip; and The circuit board according to any one of claims 1 to 6, wherein the chip is stacked on one side of the circuit board, the chip has a second pad, and the first pad and the second pad are connected by a soldering portion.

8. The circuit board assembly according to claim 7, wherein: The chip includes: a second insulating dielectric layer, wherein a third groove is provided on a side of the second insulating dielectric layer facing the circuit board; The second soldering pad is disposed in the third groove, and an end surface of the second soldering pad facing the circuit board is coplanar with an end surface of the second insulating medium layer facing the circuit board.

9. The circuit board assembly according to claim 8, wherein: The outer surface of the second pad is arranged to fit the groove wall of the third groove; The cross-sectional area of ​​the second pad gradually increases from the opening of the third groove to the bottom of the third groove, and the cross-sectional area of ​​the second pad is perpendicular to the thickness direction of the chip.

10. An electronic device, characterized in that: include: power supply; and The circuit board according to any one of claims 1 to 6, wherein the circuit board is electrically connected to the power supply.

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