High-reliability through hole type vertical LED chip

Abstract

The utility model provides a high-reliability through hole type vertical LED chip. According to the high-reliability through hole type vertical LED chip, a metal bonding layer, an insulation structure, an integrated metal layer, an ohmic reflection layer and an epitaxial lamination layer are arranged on one side of a conductive substrate; wherein the side, facing the conductive substrate, of the epitaxial laminated layer is provided with a channel for exposing part of the surface of the active region, the insulating structure is arranged on the side, facing the conductive substrate, of the epitaxial laminated layer and covers the exposed surfaces of the channel, the integrated metal layer and the epitaxial laminated layer, and the channel is insulated through the insulating structure. The risk of side wall electric leakage caused by short circuit of PN junctions due to direct exposure of the side walls when cutting channels are formed in the LED chip can be avoided, and the reliability and the stability of the LED chip are further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of light emitting diodes, and more specifically to a high-reliability through-hole vertical LED chip. Background Art

[0002] Existing light-emitting diodes include horizontal and vertical types. Vertical light-emitting diodes are obtained by transferring the semiconductor structure to another substrate with better electrical and thermal conductivity and removing the original epitaxially grown substrate. The semiconductor structure includes at least a first-type semiconductor layer, an active area, and a second-type semiconductor layer stacked in sequence. The doping types of the first-type semiconductor layer and the second-type semiconductor layer are opposite. The first-type semiconductor layer can be a P-type semiconductor layer or an N-type semiconductor layer. Compared with the horizontal type, it can effectively improve the technical problems of light absorption, current crowding, or poor heat dissipation caused by the epitaxial growth substrate. The transfer of the substrate generally adopts a bonding process, and the bonding is mainly achieved through metal-metal high-temperature and high-pressure bonding, that is, a metal bonding layer is formed between one side of the semiconductor structure and the conductive substrate. The other side of the semiconductor structure serves as the light-emitting side. The light-emitting side is provided with a wire electrode to provide current injection or outflow. The conductive substrate below the semiconductor structure provides current outflow or inflow, thereby forming a light-emitting diode in which the current passes vertically through the semiconductor structure.

[0003] In the existing through-hole vertical structure LED chips, the sidewalls of the semiconductor structure will directly expose the PN junction when forming the cutting path. When the physical separation of the LED chip devices is achieved through the cutting path, the sidewalls of the semiconductor structure will be protected by a passivation layer to improve reliability. However, leakage of the LED chip sidewalls will still occur, such as Figure 1 As shown in the figure, when the LED chip is tested for leakage through EMMI (micro-light microscope), the leakage points are all on the side wall of the core particle as shown in the dotted box. Figure 2 As shown in FIG. 1 , in another display mode of EMMI, the leakage point in the dotted box is more obvious. The sidewall leakage will seriously affect the reliability and stability of the LED chip, thereby reducing the yield of the LED chip. Utility Model Content

[0004] In view of this, the present invention provides a high-reliability through-hole vertical LED chip to solve the problem of sidewall leakage in the through-hole vertical LED chip in the prior art, which affects the reliability and stability of the LED chip.

[0005] In order to achieve the above purpose, the technical solution adopted by the present utility model is as follows:

[0006] A high-reliability through-hole vertical LED chip, comprising:

[0007] Conductive substrate;

[0008] A metal bonding layer, an insulating structure, an integrated metal layer, an ohmic reflective layer, and an epitaxial stack are provided on one side of the conductive substrate; the epitaxial stack comprises at least a second-type semiconductor layer, an active region, and a first-type semiconductor layer stacked in sequence along a first direction, wherein a channel is provided on a side of the epitaxial stack facing the conductive substrate, exposing a portion of the surface of the active region;

[0009] A groove exposing a portion of the surface of the first-type semiconductor layer is provided on a side of the epitaxial stack between the channels facing the conductive substrate, and the first direction is perpendicular to the conductive substrate and points from the conductive substrate to the epitaxial stack;

[0010] The ohmic reflective layer is stacked on a surface of the second-type semiconductor layer facing away from the active region;

[0011] The integrated metal layer covers the exposed surface of the ohmic reflective layer, and the side of the integrated metal layer facing the epitaxial stack has an exposed surface for external electrical connection;

[0012] The insulating structure is disposed on a side of the epitaxial stack facing the conductive substrate, covers the channel, the integrated metal layer, and the exposed surface of the epitaxial stack, and extends to the sidewall of the groove; the insulating structure is patterned to form a first through hole exposing a portion of the bottom of the groove;

[0013] The metal bonding layer is stacked on a surface of the insulating structure facing away from the epitaxial stack, and fills the first through hole to form an electrical connection with the first-type semiconductor layer; the conductive substrate is stacked on a surface of the metal bonding layer facing away from the epitaxial stack;

[0014] Furthermore, the insulating structure located in the trench has an exposed surface on a side facing away from the conductive substrate for use as a cutting path, and the epitaxial stack is formed into a plurality of sub-epitaxial stacks spaced apart from each other through the cutting path.

[0015] Preferably, the patterned insulating structure also forms a second through hole exposing part of the bottom of the trench, the metal bonding layer fills the second through hole, and the cutting path exposes part of the metal bonding layer in the second through hole so that the insulating structure is not within the vertical projection range of the cutting path.

[0016] Preferably, a dam is provided between the cutting street and each sub-epitaxial stack, and the dam is separated from the corresponding sub-epitaxial stack by an isolation groove, the isolation groove exposes part of the surface of the insulating structure, and the dam surrounds the corresponding sub-epitaxial stack.

[0017] Preferably, the insulating structure includes a dielectric film layer and an insulating protective layer, the dielectric film layer is provided on a portion of the surface of the second-type semiconductor layer and extends to the sidewalls of the groove, a portion of the bottom of the groove, the sidewalls of the channel, and a portion of the bottom of the channel, and the dielectric film layer includes a dielectric through-hole, the dielectric through-hole exposes a portion of the second-type semiconductor layer, and the ohmic reflective layer is electrically connected to the second-type semiconductor layer through the dielectric through-hole;

[0018] The insulating protection layer covers the integrated metal layer and the exposed surfaces of each sub-epitaxial stack facing the conductive substrate.

[0019] Preferably, a buffer metal is provided on the surface of the dielectric film layer at the corners of the groove and the channel, and the buffer metal is spaced apart from the integrated metal layer and the metal bonding layer through the insulating protection layer.

[0020] Preferably, the integrated metal layer and the buffer metal both include one of chromium, nickel, aluminum, titanium, platinum and gold.

[0021] Preferably, the dielectric film layer includes one of Al2O3, SiO2, and MgF2; and the insulating protective layer includes one of Al2O3, SiO2, and SiN.

[0022] Preferably, the channel sidewall depth is H, the second-type semiconductor layer thickness is M, and the active region thickness is N, then, M<H<M+N.

[0023] Preferably, the ohmic reflective layer is made of a metal material with high reflectivity, including one of gold, silver, aluminum, magnesium, nickel, titanium, rhodium, platinum, and ITO.

[0024] Preferably, a passivation layer is further included, which covers the exposed surface of the first-type semiconductor layer and extends to the sidewalls of each sub-epitaxial stack to connect with the dielectric film layer.

[0025] Through the above technical solution, the following effects are achieved:

[0026] 1. The utility model provides a high-reliability through-hole vertical LED chip, which is provided by arranging a metal bonding layer, an insulating structure, an integrated metal layer, an ohmic reflective layer, and an epitaxial stack on one side of a conductive substrate. A channel is provided on the side of the epitaxial stack facing the conductive substrate, exposing a portion of the surface of the active area. The insulating structure is provided on the side of the epitaxial stack facing the conductive substrate and covers the channel, the integrated metal layer, and the exposed surface of the epitaxial stack. The insulating structure insulates the channel, that is, the active area and the second-type semiconductor layer exposed by the channel. This can avoid the risk of sidewall leakage caused by the direct exposure of the PN junction of the LED chip during cutting lines, thereby improving the reliability and stability of the LED chip.

[0027] 2. Furthermore, the patterned insulating structure also forms a second through hole at the bottom of a portion of the exposed trench, the metal bonding layer fills the second through hole, and the cutting path exposes a portion of the metal bonding layer in the second through hole, so that the insulating structure is not within the vertical projection range of the cutting path, thereby avoiding the situation where the insulating structure is made of brittle material and is affected by the cutting stress to fall off and break when the LED chip device is physically separated by the cutting path. The insulating structure is also not exposed on the cutting surface, thereby preventing the insulating structure from being damaged by external sharp objects, causing leakage of the LED chip, and affecting the reliability and stability of the LED chip.

[0028] 3. Furthermore, a dam is set between the cutting path and each sub-epitaxial stack. By setting the dam, when the physical separation of the LED chip device is achieved through the cutting path, adjacent chips can be prevented from colliding with each other due to the influence of cutting stress, causing the problem of edge and corner collapse of the LED chip. The dam can also be used as a cutting positioning point to avoid cutting deviation, which can improve the reliability and stability of the LED chip.

[0029] 4. Furthermore, a buffer metal is provided on the surface of the dielectric film layer at the corners of the grooves and channels, so that the dielectric film layer at the corners of the grooves and channels can be buffered when subjected to stress, thereby avoiding fracture caused by stress, such as stress in the bonding process or the cutting process. Moreover, the buffer metal is spaced apart from the integrated metal layer and the metal bonding layer by an insulating protective layer, so that the buffer metal is non-conductive, thereby avoiding current conduction to the side walls of the grooves and channels, which affects the reliability and stability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0031] Figures 1 to 2 This is an EMMI (micro-light microscope) image of leakage detection of a through-hole vertical LED chip in the prior art;

[0032] Figure 3 A schematic structural diagram of a high-reliability through-hole vertical LED chip provided by an embodiment of the present utility model;

[0033] Figure 4 A schematic structural diagram of another high-reliability through-hole vertical LED chip provided by an embodiment of the present utility model;

[0034] Figure 5A schematic structural diagram of another high-reliability through-hole vertical LED chip provided by an embodiment of the present utility model;

[0035] Figure 6 A schematic diagram of the structure of an LED light-emitting unit of a high-reliability through-hole vertical LED chip provided by an embodiment of the present utility model;

[0036] Figure 7 A flow chart of a method for manufacturing a high-reliability through-hole vertical LED chip provided by an embodiment of the present utility model;

[0037] Figures 8 to 16 This is a structural schematic diagram corresponding to each step of a method for manufacturing a through-hole vertical structure LED chip provided by an embodiment of the present invention.

[0038] Explanation of symbols in the figure:

[0039] 01, growth substrate; A, cutting street; B, isolation trench; C, dam; K, dielectric through hole; T1, first through hole; T2, second through hole; H, channel sidewall depth; M, second-type semiconductor layer thickness; N, active area thickness;

[0040] 1. Conductive substrate; 2. First-type semiconductor layer; 21. Groove; 3. Active area; 31. Channel; 4. Second-type semiconductor layer; 5. Insulation structure: 51. Dielectric film layer; 52. Insulation protection layer; 6. Ohmic reflection layer; 7. Integrated metal layer; 8. Metal bonding layer; 9. Buffer metal; 10. Passivation layer. DETAILED DESCRIPTION

[0041] To make the content of this utility model clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0043] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0044] In view of this, the embodiment of the present application provides a high reliability through-hole vertical LED chip, such as Figure 3 Shown, including:

[0045] Conductive substrate 1;

[0046] A metal bonding layer 8, an insulating structure 5, an integrated metal layer 7, an ohmic reflective layer 6, and an epitaxial stack are provided on one side of a conductive substrate 1; the epitaxial stack comprises at least a second-type semiconductor layer 4, an active region 3, and a first-type semiconductor layer 2 stacked in sequence along a first direction, wherein a channel 31 is provided on the side of the epitaxial stack facing the conductive substrate 1, exposing a portion of the surface of the active region 3;

[0047] A groove 21 exposing a portion of the surface of the first-type semiconductor layer 2 is provided on the side of the epitaxial stack between the channels 31 facing the conductive substrate 1. The first direction is perpendicular to the conductive substrate 1 and points from the conductive substrate 1 to the epitaxial stack.

[0048] The ohmic reflective layer 6 is stacked on the surface of the second-type semiconductor layer 4 facing away from the active area 3;

[0049] The integrated metal layer 7 covers the exposed surface of the ohmic reflective layer 6, and the side of the integrated metal layer 7 facing the epitaxial stack has an exposed surface for external electrical connection;

[0050] The insulating structure 5 is disposed on the side of the epitaxial stack facing the conductive substrate 1 and covers the trench 31, the integrated metal layer 7, and the exposed surface of the epitaxial stack, and extends to the sidewalls of the recess 21. The patterned insulating structure 5 forms a first through hole T1 that exposes a portion of the bottom of the recess 21.

[0051] The metal bonding layer 8 is stacked on the side of the insulating structure 5 away from the epitaxial stack, and fills the first through hole T1 to form an electrical connection with the first-type semiconductor layer 2; the conductive substrate 1 is stacked on the side of the metal bonding layer 8 away from the epitaxial stack;

[0052] Furthermore, the insulating structure 5 located in the trench 31 has an exposed surface on the side facing away from the conductive substrate 1 , which is used as a cutting line A. The epitaxial stack is formed into a plurality of sub-epitaxial stacks spaced apart from each other through the cutting line A.

[0053] It should be noted that, in this embodiment, the ohmic reflective layer 6 can be used for ohmic contact and realize light reflection; in this embodiment, the specific doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are not limited, the doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are opposite, the first-type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer, and the materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0054] In one embodiment of the present application, the channel sidewall depth is H, the first-type semiconductor layer thickness is M, and the active region thickness is N, then, M<H<M+N.

[0055] In one embodiment of the present application, the ohmic reflective layer 6 is made of a metal material with high reflectivity, including but not limited to a stack of one or more of gold, silver, aluminum, magnesium, nickel, titanium, rhodium, platinum, and ITO.

[0056] In one embodiment of the present application, the metal bonding layer 8 includes but is not limited to one or more alloys of nickel, tin, gold, and indium.

[0057] Based on the above embodiments, in an embodiment of the present application, Figure 4 As shown, the patterned insulating structure 5 also forms a second through hole T2 that exposes part of the bottom of the trench 31, the metal bonding layer 8 fills the second through hole T2, and the cutting line A exposes part of the metal bonding layer 8 in the second through hole T2, so that the insulating structure 5 is not within the vertical projection range of the cutting line A.

[0058] Based on the above embodiments, in one embodiment of the present application, refer to Figure 4 As shown, a dam C is set between the cutting street A and each sub-epitaxial stack, and the dam C is separated from the corresponding sub-epitaxial stack by an isolation trench B. The isolation trench B exposes part of the surface of the insulating structure 5, and the dam C surrounds the corresponding sub-epitaxial stack.

[0059] Based on the above embodiments, in an embodiment of the present application, Figure 5 As shown, the insulating structure 5 includes a dielectric film layer 51 and an insulating protection layer 52. The dielectric film layer 51 is disposed on a portion of the surface of the second-type semiconductor layer 4 and extends to the sidewalls of the groove 21, a portion of the bottom of the groove 21, the sidewalls of the channel 31, and a portion of the bottom of the channel 31. The dielectric film layer 51 includes a dielectric through hole K, which exposes a portion of the second-type semiconductor layer 4. The ohmic reflective layer 6 is electrically connected to the second-type semiconductor layer 4 through the dielectric through hole K.

[0060] The insulating protection layer 52 covers the integrated metal layer 7 and the exposed surfaces of each sub-epitaxial stack facing the conductive substrate 1 .

[0061] In one embodiment of the present application, the dielectric film layer 51 includes but is not limited to a stack of one or more of Al2O3, SiO2, and MgF2; the insulating protection layer 52 includes but is not limited to a stack of one or more of Al2O3, SiO2, and SiN.

[0062] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, a buffer metal 9 is provided on the surface of the dielectric film layer 51 at the corner of the groove 21 and the channel 31 , and the buffer metal 9 is spaced apart from the integrated metal layer 7 and the metal bonding layer 8 by an insulating protection layer 52 .

[0063] In one embodiment of the present application, the integrated metal layer 7 and the buffer metal 9 both include, but are not limited to, a stack of one or more of chromium, nickel, aluminum, titanium, platinum, and gold.

[0064] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, a passivation layer 10 is also included. The passivation layer 10 covers the exposed surface of the first-type semiconductor layer 2 and extends to the sidewalls of each sub-epitaxial stack to connect with the dielectric film layer 51.

[0065] Based on the above embodiments, in an embodiment of the present application, Figure 6 As shown, through the cutting process, cutting is carried out along the cutting line A to separate and form several independent LED light-emitting units.

[0066] It should be noted that, in this embodiment, the insulating protective layer 52 is not exposed on the sidewalls of each LED light-emitting unit, so as to prevent the insulating protective layer 52 from being damaged by external sharp objects and causing leakage of the LED chip.

[0067] The present invention also provides a method for manufacturing a high-reliability through-hole vertical LED chip. Figure 7 As shown, the production method includes:

[0068] Step S01: providing a growth substrate, and forming an epitaxial stack on a surface of one side of the growth substrate, wherein the epitaxial stack includes a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence along a growth direction;

[0069] Step S02, forming channels by etching the epitaxial stack to a portion of the surface of the active area, and simultaneously forming grooves between the channels by etching the epitaxial stack to a portion of the surface of the first-type semiconductor layer;

[0070] Step S03: preparing an insulating structure to cover the groove, the channel and a portion of the second-type semiconductor layer;

[0071] Step S04: preparing an ohmic reflective layer to cover the exposed second-type semiconductor layer;

[0072] Step S05: preparing an integrated metal layer to cover the exposed surface of the ohmic reflective layer;

[0073] Step S06: depositing the entire insulating structure again to cover the exposed surface of the integrated metal layer and the epitaxial stack, and patterning the insulating structure to expose a portion of the bottom of the groove to form a first through hole;

[0074] Step S07: evaporating a metal bonding layer, wherein the metal bonding layer is stacked on a surface of the insulating structure facing away from the epitaxial stack, and fills the first through hole to form a connection with the first-type semiconductor layer;

[0075] Step S08: fixing the chip structure formed in step S07 to a conductive substrate through a bonding process, wherein the conductive substrate is formed on a surface of the metal bonding layer that is away from the epitaxial stack;

[0076] Step S09: peeling off the growth substrate to expose the first-type semiconductor layer;

[0077] Step S10, etching the side of the epitaxial stack facing away from the conductive substrate so that the insulating structure located in the trench has an exposed surface for serving as a cutting path, and the epitaxial stack is formed into a plurality of sub-epitaxial stacks spaced apart from each other through the cutting path;

[0078] At the same time, each of the sub-epitaxial stacks is etched to form an opening for external electrical connection by exposing a portion of the surface of the integrated metal layer.

[0079] The following describes in detail the method for manufacturing a high-reliability through-hole vertical LED chip provided by an embodiment of the present invention in conjunction with the accompanying drawings corresponding to each step, including:

[0080] Step S01: Figure 8 As shown, a growth substrate 01 is provided, and an epitaxial stack is formed on one side surface of the growth substrate 01. The epitaxial stack includes a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 4 stacked in sequence along a growth direction.

[0081] In one embodiment of the present application, the provided growth substrate 01 may be a substrate made of sapphire or other materials, and this embodiment of the utility model does not impose any specific limitation on this.

[0082] In this embodiment, the specific doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are not limited. The doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are opposite. The first-type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0083] In one embodiment of the present application, the epitaxial stack provided by the embodiment of the present utility model can be a GaN-based epitaxial wafer, and the light-emitting layer is a multi-quantum well layer.

[0084] Step S02: Figure 9 As shown, the channels 31 are formed by etching the epitaxial stack to a portion of the surface of the active region 3 , and the recesses 21 are formed by etching the epitaxial stack to a portion of the surface of the first-type semiconductor layer 2 between the channels 31 .

[0085] In an embodiment of the present application, the channel 31 and the groove 21 may be formed by coating, exposing, developing, and etching processes.

[0086] In one embodiment of the present application, the channel sidewall depth is H, the second-type semiconductor layer thickness is M, and the active region thickness is N, then, M<H<M+N.

[0087] Step S03: Figure 10 As shown, an insulating structure 5 is prepared to cover the groove 21 , the channel 31 and a portion of the second-type semiconductor layer 4 .

[0088] Step S04: Figure 11 As shown, an ohmic reflective layer 6 is prepared to cover the exposed second-type semiconductor layer 4 .

[0089] It should be noted that, in this embodiment, the ohmic reflective layer 6 can be used for ohmic contact and realize light reflection.

[0090] In one embodiment of the present application, the ohmic reflective layer 6 may be formed by first performing coating, exposure, and development, and then adopting an evaporation or sputtering process.

[0091] In one embodiment of the present application, the ohmic reflective layer 6 is made of a metal material with high reflectivity, including but not limited to a stack of one or more of gold, silver, aluminum, magnesium, nickel, titanium, rhodium, platinum, and ITO.

[0092] Step S05: Figure 12 As shown, an integrated metal layer 7 is prepared to cover the exposed surface of the ohmic reflective layer 6 .

[0093] Step S06: Figure 13 As shown, the entire insulating structure 5 is deposited again to cover the exposed surface of the integrated metal layer 7 and the epitaxial stack, and the insulating structure 5 is patterned to expose a portion of the bottom of the groove 21 to form a first through hole T1.

[0094] Step S07: Figure 14 As shown, a metal bonding layer 8 is evaporated and stacked on a surface of the insulating structure 5 facing away from the epitaxial stack, and fills the first through hole T1 to form a connection with the first type semiconductor layer 2.

[0095] In one embodiment of the present application, the metal bonding layer 8 includes but is not limited to one or more alloys of nickel, tin, gold, and indium.

[0096] Step S08: Figure 15 As shown, the chip structure formed in step S07 is fixed to the conductive substrate 1 through a bonding process, and the conductive substrate 1 is formed on a surface of the metal bonding layer 8 that is away from the epitaxial stack.

[0097] Step S09: Figure 16 As shown, the growth substrate 01 is peeled off to expose the first type semiconductor layer 2 .

[0098] In one embodiment of the present application, the growth substrate 01 may be removed by a laser cutting process or chemical etching.

[0099] Step S10, reference Figure 3 As shown, etching is performed on the side of the epitaxial stack facing away from the conductive substrate 1 so that the insulating structure 5 located in the trench 31 has an exposed surface for serving as a cutting line A, thereby exposing a portion of the trench 31 to form the cutting line A. The epitaxial stack is formed into a plurality of sub-epitaxial stacks spaced apart from each other through the cutting line A.

[0100] At the same time, each sub-epitaxial stack is etched to form an opening for external electrical connection by exposing a portion of the surface of the integrated metal layer 7 .

[0101] In one embodiment of the present application, the cutting street A can be formed by coating, exposing, developing, and etching processes. In this embodiment, the etching process can be ICP etching or wet etching.

[0102] Based on the above embodiments, in one embodiment of the present application, refer to Figure 4 As shown, the patterned insulating structure 5 also forms a second through hole T2 that exposes part of the bottom of the trench 31, the metal bonding layer 8 fills the second through hole T2, and the cutting line A exposes part of the metal bonding layer 8 in the second through hole T2, so that the insulating structure 5 is not within the vertical projection range of the cutting line A.

[0103] In an embodiment of the present application, the insulating structure 5 may be patterned to simultaneously form the first through hole T1 and the second through hole T2 .

[0104] In one embodiment of the present application, the insulating structure 5 may be patterned by first performing photoresist coating, exposure, and development, and then adopting a wet etching process. The etching solution may be a BOE etching solution.

[0105] Based on the above embodiments, in one embodiment of the present application, refer to Figure 4As shown, by etching part of the epitaxial stack between the cutting path A and each sub-epitaxial stack, a dam C is formed between the cutting path A and each sub-epitaxial stack, and the dam C is separated from the corresponding sub-epitaxial stack by the isolation groove B. The isolation groove B exposes part of the surface of the insulating structure 5, and the dam C surrounds the corresponding sub-epitaxial stack.

[0106] In one embodiment of the present application, the cutting streets A, the dams C, and the openings for external electrical connection by exposing a portion of the surface of the integrated metal layer 7 can be formed simultaneously by one photolithography process.

[0107] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, the insulating structure 5 includes a dielectric film layer 51 and an insulating protection layer 52. The dielectric film layer 51 is disposed on a portion of the surface of the second-type semiconductor layer 4 and extends to the sidewalls of the groove 21, a portion of the bottom of the groove 21, the sidewalls of the channel 31, and a portion of the bottom of the channel 31. The dielectric film layer 51 includes a dielectric through hole K, which exposes a portion of the second-type semiconductor layer 4. The ohmic reflective layer 6 is electrically connected to the second-type semiconductor layer 4 through the dielectric through hole K.

[0108] The insulating protection layer 52 covers the integrated metal layer 7 and the exposed surfaces of each sub-epitaxial stack facing the conductive substrate 1 .

[0109] In one embodiment of the present application, the dielectric film layer 51 includes but is not limited to a stack of one or more of Al2O3, SiO2, and MgF2; the insulating protection layer 52 includes but is not limited to a stack of one or more of Al2O3, SiO2, and SiN.

[0110] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, a buffer metal 9 is provided on the surface of the dielectric film layer 51 at the corner of the groove 21 and the channel 31 , and the buffer metal 9 is spaced apart from the integrated metal layer 7 and the metal bonding layer 8 by an insulating protection layer 52 .

[0111] In one embodiment of the present application, the integrated metal layer 7 and the buffer metal 9 both include, but are not limited to, a stack of one or more of chromium, nickel, aluminum, titanium, platinum, and gold.

[0112] In one embodiment of the present application, the buffer metal 9 may be formed while forming the integrated metal layer 7 .

[0113] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, a passivation layer 10 is also included. The passivation layer 10 covers the exposed surface of the first-type semiconductor layer 2 and extends to the sidewalls of each sub-epitaxial stack to connect with the dielectric film layer 51.

[0114] Based on the above embodiments, in one embodiment of the present application, refer to Figure 6 As shown, through the cutting process, cutting is carried out along the cutting line A to separate and form several independent LED light-emitting units.

[0115] It should be noted that, in this embodiment, the insulating protective layer 52 is not exposed on the sidewalls of each LED light-emitting unit, so as to prevent the insulating protective layer 52 from being damaged by external sharp objects and causing leakage of the LED chip.

[0116] In one embodiment of the present application, independent LED light-emitting units are formed by laser cutting and splitting.

[0117] In summary, through the above technical solution, the following effects are achieved:

[0118] 1. This embodiment provides a high-reliability through-hole vertical LED chip, which comprises a metal bonding layer, an insulating structure, an integrated metal layer, an ohmic reflective layer, and an epitaxial stack disposed on one side of a conductive substrate. A channel is provided on the side of the epitaxial stack facing the conductive substrate, exposing a portion of the surface of the active region. The insulating structure is disposed on the side of the epitaxial stack facing the conductive substrate and covers the channel, the integrated metal layer, and the exposed surface of the epitaxial stack. The insulating structure insulates the channel, that is, the active region and the second-type semiconductor layer exposed by the channel. This avoids the risk of sidewall leakage caused by the direct exposure of the PN junction of the LED chip during cutting lines, thereby improving the reliability and stability of the LED chip.

[0119] 2. Furthermore, the patterned insulating structure also forms a second through hole at the bottom of a portion of the exposed trench, the metal bonding layer fills the second through hole, and the cutting path exposes a portion of the metal bonding layer in the second through hole, so that the insulating structure is not within the vertical projection range of the cutting path, thereby avoiding the situation where the insulating structure is made of brittle material and is affected by the cutting stress to fall off and break when the LED chip device is physically separated by the cutting path. The insulating structure is also not exposed on the cutting surface, thereby preventing the insulating structure from being damaged by external sharp objects, causing leakage of the LED chip, and affecting the reliability and stability of the LED chip.

[0120] 3. Furthermore, a dam is set between the cutting path and each sub-epitaxial stack. By setting the dam, when the physical separation of the LED chip device is achieved through the cutting path, adjacent chips can be prevented from colliding with each other due to the influence of cutting stress, causing the problem of edge and corner collapse of the LED chip. The dam can also be used as a cutting positioning point to avoid cutting deviation, which can improve the reliability and stability of the LED chip.

[0121] 4. Furthermore, a buffer metal is provided on the surface of the dielectric film layer at the corners of the grooves and channels, so that the dielectric film layer at the corners of the grooves and channels can be buffered when subjected to stress, thereby avoiding fracture caused by stress, such as stress in the bonding process or the cutting process. Moreover, the buffer metal is spaced apart from the integrated metal layer and the metal bonding layer by an insulating protective layer, so that the buffer metal is non-conductive, thereby avoiding current conduction to the side walls of the grooves and channels, which affects the reliability and stability of the LED chip.

[0122] 5. The present embodiment provides a method for manufacturing a high-reliability through-hole vertical LED chip. While achieving the beneficial effects of the above-mentioned LED chip, its manufacturing process is simple and convenient, and is easy to produce.

[0123] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "horizontal", "longitudinal", "upper", "lower", etc. indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms cannot be understood as limiting the present invention.

[0124] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0125] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-reliability through-hole vertical LED chip, characterized in that: include: Conductive substrate; A metal bonding layer, an insulating structure, an integrated metal layer, an ohmic reflective layer, and an epitaxial stack are provided on one side of the conductive substrate; the epitaxial stack comprises at least a second-type semiconductor layer, an active region, and a first-type semiconductor layer stacked in sequence along a first direction, wherein a channel is provided on a side of the epitaxial stack facing the conductive substrate, exposing a portion of the surface of the active region; A groove exposing a portion of the surface of the first-type semiconductor layer is provided on a side of the epitaxial stack between the channels facing the conductive substrate, and the first direction is perpendicular to the conductive substrate and points from the conductive substrate to the epitaxial stack; The ohmic reflective layer is stacked on a surface of the second-type semiconductor layer facing away from the active region; The integrated metal layer covers the exposed surface of the ohmic reflective layer, and the side of the integrated metal layer facing the epitaxial stack has an exposed surface for external electrical connection; The insulating structure is disposed on a side of the epitaxial stack facing the conductive substrate, covers the channel, the integrated metal layer, and the exposed surface of the epitaxial stack, and extends to the sidewall of the groove; the insulating structure is patterned to form a first through hole exposing a portion of the bottom of the groove; The metal bonding layer is stacked on a surface of the insulating structure facing away from the epitaxial stack, and fills the first through hole to form an electrical connection with the first-type semiconductor layer; the conductive substrate is stacked on a surface of the metal bonding layer facing away from the epitaxial stack; Furthermore, the insulating structure located in the trench has an exposed surface on a side facing away from the conductive substrate for use as a cutting path, and the epitaxial stack is formed into a plurality of sub-epitaxial stacks spaced apart from each other through the cutting path.

2. The high-reliability through-hole vertical LED chip according to claim 1, characterized in that: The patterned insulating structure also forms a second through hole exposing part of the bottom of the trench, the metal bonding layer fills the second through hole, and the cutting path exposes part of the metal bonding layer in the second through hole so that the insulating structure is not within the vertical projection range of the cutting path.

3. The high-reliability through-hole vertical LED chip according to claim 1, characterized in that: A dam is provided between the cutting street and each sub-epitaxial stack, and the dam is separated from the corresponding sub-epitaxial stack by an isolation groove, the isolation groove exposes a portion of the surface of the insulating structure, and the dam surrounds the corresponding sub-epitaxial stack.

4. The high-reliability through-hole vertical LED chip according to claim 1, characterized in that: The insulating structure includes a dielectric film layer and an insulating protective layer, wherein the dielectric film layer is disposed on a portion of the surface of the second-type semiconductor layer and extends to the sidewalls of the groove, a portion of the bottom of the groove, the sidewalls of the channel, and a portion of the bottom of the channel, and the dielectric film layer includes a dielectric through hole, wherein the dielectric through hole exposes a portion of the second-type semiconductor layer, and the ohmic reflective layer is electrically connected to the second-type semiconductor layer through the dielectric through hole; The insulating protection layer covers the integrated metal layer and the exposed surfaces of each sub-epitaxial stack facing the conductive substrate.

5. The high-reliability through-hole vertical LED chip according to claim 4, characterized in that: A buffer metal is provided on the surface of the dielectric film layer at the corners of the groove and the channel, and the buffer metal is spaced apart from the integrated metal layer and the metal bonding layer through the insulating protection layer.

6. The high-reliability through-hole vertical LED chip according to claim 1, characterized in that: The channel sidewall depth is H, the second-type semiconductor layer thickness is M, and the active region thickness is N, then, M<H<M+N.

7. The high-reliability through-hole vertical LED chip according to claim 1, characterized in that: The invention also includes a passivation layer, which covers the exposed surface of the first-type semiconductor layer and extends to the side walls of each sub-epitaxial stack and is connected to the dielectric film layer.

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