Splicing type chip test carrier plate

Abstract

The utility model discloses a splicing type chip test carrier plate, which belongs to the technical field of chip test carrier plates and comprises at least two test split plates, the two test split plates can form a flat plate structure after being spliced, and a butt joint end face is formed at the splicing position of the two test split plates. Wherein one side, located on the butt joint end face, of one test sub-plate and the opposite side of the other test sub-plate are both provided with lower abutting plates in a protruding mode, the two test sub-plates are both provided with upper abutting plates corresponding to the lower abutting plates in a protruding mode, the upper abutting plates abut against the lower abutting plates in an abutting mode, fixing pieces are fixedly installed on the lower abutting plates, positioning pins are installed on the fixing pieces, and the positioning pins are connected with the test sub-plates. A limiting hole is formed in the upper abutting plate, and the positioning pin is inserted into the limiting hole in a matched mode. According to the utility model, a plurality of small test sub-plates can be spliced together according to test requirements to form a complete chip test carrier plate, and part of the test sub-plates can be abandoned according to requirements during splicing, so that the waste problem caused by abandoning the whole test carrier plate is avoided, the cost is reduced, the operation is easy, and the connection is reliable.

Description

Technical Field

[0001] The utility model relates to the technical field of chip test carriers, in particular to a spliced ​​chip test carrier. Background Art

[0002] With the rapid development of chip technology and the increase in chip complexity, chip testing needs to be given more and more attention. The carrier of chip functional testing is the chip test carrier. The design and manufacture of chip test carriers is an indispensable component in the entire semiconductor industry.

[0003] An ATE (Auto Test Equipment) test board, also known as a chip test carrier, is an interface circuit board (PCB) specifically used to connect the chip under test to the test equipment and test its performance. Chip test carriers can be 5-8mm thick, have up to 60 layers, and measure up to 0.5 x 0.5m. Designing a chip test carrier is time-consuming and expensive. Before mass production begins, a chip test carrier is typically designed to verify the feasibility of the chip test solution. This involves testing and verifying as many different chips as possible, or multiple test solutions for the same chip. This typically requires the design of multiple different test carriers. If a test solution proves ineffective, the entire chip test carrier is discarded, significantly increasing production costs.

[0004] Therefore, how to further reduce design costs while ensuring test performance and test requirements is a technical problem that needs to be urgently solved in this industry. Utility Model Content

[0005] The technical problem to be solved by the present invention is that in the prior art, multiple test schemes are all provided on the same chip test carrier. When some test schemes are proven to be invalid, the entire test carrier will be discarded, which greatly increases the production cost.

[0006] The technical solution adopted by the present invention to solve its technical problems is: a spliced ​​chip test carrier, comprising at least two test sub-boards, which can form a flat plate structure after being spliced ​​together, and a butt joint surface is formed at the splicing point of the two test sub-boards, wherein a lower abutment plate is protruded on one side of the butt joint surface of one of the test sub-boards and on the opposite side of the other test sub-board, and an upper abutment plate is protruded on the two test sub-boards corresponding to the lower abutment plate, the upper abutment plate is overlapped on the lower abutment plate, a fixing part is fixedly installed on the lower abutment plate, a positioning pin is installed on the fixing part, a limiting hole is provided on the upper abutment plate, and the positioning pin is inserted into the limiting hole.

[0007] Furthermore, one side of the docking end face is recessed inwardly to form a groove corresponding to the upper support plate, and the groove cooperates with the upper support plate. The groove wall connected to the docking end face is set as a first inclined surface, and one side of the upper support plate is set as a second inclined surface, and the second inclined surface is in contact with the first inclined surface.

[0008] Furthermore, the fixing member is a rivet nut fixedly mounted on the lower support plate, the positioning pin includes a threaded section and a polished rod section connected above the threaded section, the threaded section is threadedly connected to the rivet nut, and the polished rod section is inserted into the limiting hole.

[0009] Furthermore, the lower surface of the rivet nut is higher than the lower surface of the lower abutment plate, and the upper surface of the rivet nut is lower than the upper surface of the lower abutment plate.

[0010] Furthermore, the limiting hole is a waist-shaped hole, and the positioning pin contacts two mutually parallel hole walls of the waist-shaped hole.

[0011] Furthermore, there are two test sub-plates, both of which are semicircular flat plate structures.

[0012] Furthermore, the connection line between the two positioning pins is arranged along the radial direction of the test sub-plate.

[0013] The beneficial effects of the present invention are as follows: the spliced ​​chip test carrier of the present invention can splice together multiple smaller test sub-boards according to test needs to flexibly form a complete chip test carrier, realizing a combination mode of parallel testing of multiple different chips. Before combination, the test sub-boards that do not meet the test needs can be discarded. Compared with the traditional scrapped entire test carrier, the production cost is greatly reduced, and the splicing structure between the test sub-boards is highly reliable, easy to operate, and convenient for promotion and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0015] Figure 1 This is a three-dimensional diagram of the spliced ​​chip test carrier of the present invention;

[0016] Figure 2 yes Figure 1 A partial enlarged view of point A in the spliced ​​chip test carrier shown;

[0017] Figure 3 yes Figure 1 A partially exploded view of the spliced ​​chip test carrier shown;

[0018] Figure 4 yes Figure 3A partial enlarged view of point B in the spliced ​​chip test carrier shown;

[0019] Figure 5 yes Figure 3 Exploded view of the test sub-board, fixtures, and locating pins in the spliced ​​chip test carrier shown.

[0020] In the figure: 1. test sub-plate, 101. docking end face, 102. groove, 1021. first inclined surface, 11. lower abutment plate, 12. upper abutment plate, 121. limiting hole, 122. second inclined surface, 2. fixing part, 3. positioning pin. DETAILED DESCRIPTION

[0021] The present invention will now be described in detail with reference to the accompanying drawings. This drawing is a simplified schematic diagram, which only illustrates the basic structure of the present invention in a schematic manner, and therefore only shows the components related to the present invention.

[0022] See also Figure 1-Figure 5 The present invention provides a spliced ​​chip test carrier, comprising at least two test sub-boards 1, which can form a flat plate structure after being spliced ​​together. The splicing of the two test sub-boards 1 forms a butt joint face 101, and a lower abutment plate 11 is protrudingly provided on one side of the butt joint face 101 of one test sub-board 1 and on the opposite side of the other test sub-board 1. An upper abutment plate 12 is protrudingly provided on the corresponding lower abutment plates 11 of the two test sub-boards 1, and the upper abutment plate 12 rests on the lower abutment plate 11. A fixing member 2 is fixedly installed on the lower abutment plate 11, and a positioning pin 3 is installed on the fixing member 2. A limiting hole 121 is provided on the upper abutment plate 12, and the limiting hole 121 is a through hole. The positioning pin 3 is cooperatively inserted into the limiting hole 121.

[0023] The spliced ​​chip test carrier of the present invention divides the chip test carrier into multiple test sub-boards 1 that can be spliced ​​with each other, and different test chips and different test circuit schemes are designed on different test sub-boards 1 respectively. Each individual test sub-board 1 can perform independent test scheme verification on the chip. In other words, the tester can select one of the test sub-boards 1 to use according to the test needs, and other unrelated test sub-boards 1 do not need to participate in the test work, avoiding the problem of large-area space waste caused by still using a full-size test carrier when the number of chips to be tested is small.

[0024] When it is desired to verify multiple chips or multiple test schemes for a chip, the tester can arbitrarily combine multiple test sub-boards 1 according to the test needs and connect them to each other to form a complete test carrier board. The test sub-boards 1 corresponding to those test schemes that are proven to be invalid can be directly discarded. Compared with the traditional scrapping of the entire test carrier board, the utility model achieves a geometric reduction in production costs and provides a favorable guarantee for the rapid and accurate verification of chip schemes.

[0025] When two adjacent test panels 1 are docked, one of the test panels 1 moves horizontally and joins to one side of the other test panel 1. At this point, the upper support plate 12 abuts the lower support plate 11 on both opposing sides of the test support plate. Thus, when one test panel 1 moves longitudinally relative to the other, the alternating abutment between the two sides prevents the two from easily separating, thus limiting longitudinal movement. After the two test panels 1 are in place, the tester can operate the locating pin 3, passing one end of the locating pin through the limiting hole 121 and connecting it to the fixing member 12. Once the locating pin 3 is in place, it contacts the wall of the limiting hole 121. At this point, the upper and lower support plates 12, 11, are locked together by the locating pin 3, effectively preventing the upper and lower support plates 12, 11 from easily moving relative to each other in the horizontal direction.

[0026] As a preferred embodiment, one side of the butt end face 101 is recessed inwardly corresponding to the upper support plate 12 to form a groove 102. The groove 102 cooperates with the upper support plate 12. The horizontal groove wall of the groove 102 is coplanar with the lower support plate 11. The groove wall of the groove 102 connected to the butt end face 101 is set as a first inclined surface 1021, and a side wall of the upper support plate 12 is set as a second inclined surface 122. The second inclined surface 122 is in contact with the first inclined surface 1021. By setting the first inclined surface 1021 and the second inclined surface 122 to be in contact with each other, the movement of the two test sub-boards 1 along the length direction of the butt end face 101 is limited. At the same time, it also provides a guarantee that the subsequent positioning pin 3 can be quickly inserted into the limit hole 121, which is conducive to the test personnel to quickly splice multiple test sub-boards 1.

[0027] In this embodiment, the fixing member 2 is a self-clinching nut fixedly mounted on the lower support plate 11, and the positioning pin 3 includes a threaded section and a polished rod section connected above the threaded section. The threaded section is threadedly connected to the self-clinching nut, and the polished rod section is inserted into the limiting hole 121. Furthermore, the lower surface of the self-clinching nut is higher than the lower surface of the lower support plate 11, and the upper surface of the self-clinching nut is lower than the upper surface of the lower support plate 11. Therefore, the self-clinching nut does not protrude outside the upper and lower surfaces of the lower support plate 11, thereby avoiding the situation where the upper support plate 12 cannot fully overlap the lower support plate 1.

[0028] Furthermore, the limiting hole 121 is a round hole, and the positioning pin 3 contacts two parallel walls of the round hole. This means that the diameter of the polished rod segment is equal to the width of the limiting hole 121. The width of the limiting hole 121 is the distance between the two parallel walls of the round hole. By designing the limiting hole 121 as a round hole, the positioning pin 3 is prevented from being misaligned with the limiting hole 121 due to machining errors.

[0029] In this embodiment, two test sub-plates 1 are provided, each having a roughly semicircular flat plate structure. The two test sub-plates 1, when joined, form the test carrier of the present invention, forming a complete circular plate-like structure. The line connecting the two locating pins 3 is arranged along the radial direction of the test sub-plates 1 (i.e., the radial direction of the test carrier). It will be appreciated that in other embodiments (not shown), the shape and number of the test sub-plates 1 can be designed based on testing needs and are not limited here.

[0030] The spliced ​​chip test carrier of the present invention can splice together multiple smaller test sub-boards 1 with different test schemes according to test needs, and flexibly form a complete chip test carrier, realizing a combination mode of parallel testing of multiple different chips. Before combination, some test sub-boards 1 that do not meet the test needs can be discarded. Compared with the traditional scrapping of the entire test carrier, the production cost is greatly reduced, and the splicing structure between the test sub-boards 1 is highly reliable, easy to operate, and convenient for promotion and use.

[0031] Based on the above-mentioned ideal embodiment of the present invention, and in accordance with the above description, relevant personnel can make various changes and modifications without departing from the scope of the present invention. The technical scope of this utility model is not limited to the content of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A spliced ​​chip test carrier, characterized by: It comprises at least two test sub-plates, which can form a flat plate structure after being spliced ​​together, and a butt joint surface is formed at the splicing point of the two test sub-plates, a lower support plate is protruding from one side of the butt joint surface on one of the test sub-plates and an opposite side on the other test sub-plate, and an upper support plate is protruding from the two test sub-plates corresponding to the lower support plate, the upper support plate is overlapped with the lower support plate, a fixing part is fixedly installed on the lower support plate, a positioning pin is installed on the fixing part, a limiting hole is provided on the upper support plate, and the positioning pin is inserted into the limiting hole.

2. The spliced ​​chip test carrier according to claim 1, wherein: One side of the butt joint end face corresponds to the upper support plate and is recessed inward to form a groove, the groove and the upper support plate cooperate with each other, the groove wall connected to the butt joint end face on the groove is set as a first inclined surface, and one side of the upper support plate is set as a second inclined surface, and the second inclined surface and the first inclined surface are in contact with each other.

3. The spliced ​​chip test carrier according to claim 1, wherein: The fixing member is a rivet nut fixedly mounted on the lower support plate, and the positioning pin includes a threaded section and a polished rod section connected above the threaded section. The threaded section is threadedly connected to the rivet nut, and the polished rod section is inserted into the limiting hole.

4. The spliced ​​chip test carrier according to claim 3, wherein: The lower surface of the rivet nut is higher than the lower surface of the lower abutment plate, and the upper surface of the rivet nut is lower than the upper surface of the lower abutment plate.

5. The spliced ​​chip test carrier according to claim 1, wherein: The limiting hole is a waist-shaped hole, and the positioning pin contacts two hole walls on the waist-shaped hole that are parallel to each other.

6. The spliced ​​chip test carrier according to claim 1, wherein: There are two test sub-plates, both of which are semicircular flat plate structures.

7. The spliced ​​chip test carrier according to claim 6, wherein: The connecting line between the two positioning pins is arranged along the radial direction of the test sub-plate.

Images