Chip detection system
By using a combination of electronic equipment and a burner on a mobile terminal to directly detect the register status of the chip I/O port, the problem of cumbersome chip I/O port damage detection in the existing technology is solved, and efficient chip detection is achieved.
Patent Information
- Application Number
- CN202421994668.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-08-16
AI Technical Summary
In the prior art, chip I/O port damage detection requires removing the chip for tedious testing, which is inefficient and cannot be effectively performed.
A chip detection system is provided. By combining an electronic device with a burner and a connection device, the chip can be directly tested on a mobile terminal. The SWD protocol is used to read and write the chip's I/O port registers, and the I/O port register status is analyzed to determine damage without removing the chip.
This method enables efficient detection of chip I/O port damage without removing the chip, simplifies the detection process, and improves detection efficiency.
Smart Images
Figure CN223400995U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of chip detection, in particular to a chip detection system. Background Art
[0002] Chips may be damaged during the factory production process, so the chips need to be tested.
[0003] For example, a common situation in which a chip is damaged is when the I / O port is damaged, for example, when the I / O port is opened by static electricity.
[0004] However, currently, testing the I / O port requires removing the chip for testing, such as removing the chip and placing it in a socket and testing it on a Design Verification Test (DVT) board. This testing is very tedious and time-consuming. Utility Model Content
[0005] In response to the deficiencies in the prior art, the present application provides a chip detection system that is conducive to detecting the chip of a mobile terminal without removing the chip.
[0006] In order to solve the above problems, the present invention provides the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a chip detection system, the system comprising:
[0008] Electronic equipment connected to the programmer;
[0009] A programmer connected to a connecting device with a probe;
[0010] A connecting device, wherein a probe in the connecting device contacts a burning contact on the mobile terminal;
[0011] Mobile terminals, including burning contacts and chips;
[0012] The electronic device is used to control the chip.
[0013] In some embodiments, the system comprises:
[0014] The connecting device contacts the burning contact of the display screen on the mobile terminal through the probe;
[0015] The electronic device is used to control the chip in the display screen on the mobile terminal.
[0016] In some embodiments, the chip comprises a scaler chip.
[0017] In some implementations, the electronic device reads and writes registers of the I / O ports in the chip via the SWD protocol.
[0018] In some embodiments, the electronic device is connected to the writer via a USB cable.
[0019] In some embodiments, the writer is connected to a connection device with probes via DuPont wires in line sequence.
[0020] In some embodiments, the chip includes at least one I / O port, each of the I / O ports includes an I / O port bit circuit, and the I / O port bit circuit includes a first register, a first driver module, a second driver module, a second register, and an I / O pin;
[0021] The first register is connected to the first driving module;
[0022] The first driving module is connected to the second driving module and the I / O pin;
[0023] The second driving module is connected to the second register.
[0024] In some embodiments, the second driving module includes a voltage control submodule and a detection resistor;
[0025] A first end of the detection resistor is connected to the voltage control submodule, and a second end of the detection resistor is connected to the I / O pin and the first driving module.
[0026] In some embodiments, the voltage control submodule includes a first voltage source, a first switch, a second voltage source, and a second switch;
[0027] The first voltage source is connected to a first end of the first switch, and a second end of the first switch is connected to the detection resistor and the second register;
[0028] The second voltage source is connected to a first end of the second switch, and a second end of the second switch is connected to the detection resistor and the second register.
[0029] In some embodiments, the second driving module further includes a TTL Schottky trigger;
[0030] A first end of the TTL Schottky trigger is connected to the second register, and a second end of the TTL Schottky trigger is connected to the second end of the first switch, the second end of the second switch, and the detection resistor.
[0031] The present application provides a chip detection system, comprising: an electronic device connected to a programmer; the programmer connected to a connection device with probes; the connection device, wherein the probes in the connection device contact programming contacts on the mobile terminal; the mobile terminal including the programming contacts and a chip; and the electronic device for controlling the chip. In the present application, the electronic device is directly connected to the mobile terminal via the programmer and the connection device, and can detect the chip in the mobile terminal without removing the chip from the mobile terminal for detection. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 This is a system schematic diagram of a chip detection system provided in this application.
[0033] Figure 2 This is a first schematic diagram of an I / O port bit circuit provided in an embodiment of the present application.
[0034] Figure 3 This is a second schematic diagram of an I / O port bit circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this utility model, "plurality" means two or more, unless otherwise specifically defined.
[0037] For ease of description, in the embodiments of the present application, a scaler chip is used as an example for description.
[0038] During the factory production process, scaler chips may be damaged, the most common of which is I / O damage (open circuit caused by static electricity).
[0039] The conventional detection method includes the following three steps:
[0040] 1. Remove the scaler chip and place it in the socket for testing on the DVT board. You need to measure the diode characteristics of the I / O port.
[0041] 2. Configure the I / O port to GPIO mode and input direction through software, connect a controllable level to the I / O pin as input, and test the function of the input data register (second register) in the I / O port.
[0042] 3. Use software to configure the I / O port to GPIO mode and output direction, write data to the output data register (the first register), and make the I / O pin output a specific waveform to test its output function.
[0043] The above measurement process requires tools such as a socket, a DVT board, a programming board, a logic analyzer, and DuPont wires to assist in testing. This is complex and inefficient. Furthermore, only one GPIO port can be tested at a time, and testing all GPIO ports of a chip is very time-consuming.
[0044] See also Figure 1 , Figure 1 This is a schematic diagram of a chip detection system provided by this application. Figure 1 As shown, the chip detection system 100 includes: an electronic device 110 , a burner 120 , a connecting device 130 and a mobile terminal 140 .
[0045] Optionally, the electronic device 110 may be a computer, a laptop, or the like.
[0046] Optionally, the mobile terminal 140 is a mobile terminal with a display screen, such as a mobile phone, a tablet computer, etc.
[0047] In some embodiments, the connection device 130 contacts the programming contacts of the display screen on the mobile terminal 140 through the probe; and the electronic device 110 is used to control a chip in the display screen on the mobile terminal 140 .
[0048] Specifically, the probe is used to accurately dock with the burning contacts of the electronic device to perform data burning or reading operations. The probe can be made of metal or special plastic with good conductivity and wear resistance to ensure stable contact with the burning contacts and reliability of data transmission.
[0049] In some implementations, the programmer may be directly equipped with probes corresponding to the programming contacts of the device to be programmed. In this case, the probes of the programmer can be brought into contact with the programming contacts of the mobile terminal without the aid of a connecting device.
[0050] In some embodiments, the chip is a scaler chip.
[0051] Specifically, a scaler chip is a video processing chip that adjusts the resolution of video signals to suit different display devices. It can convert high-definition video signals to standard-definition signals, or vice versa, and can also perform operations such as zooming in, out, and cropping images.
[0052] In some implementations, the electronic device reads and writes registers of the I / O ports in the chip via a Serial Wire Debug (SWD) protocol.
[0053] Optionally, the I / O port bit circuit includes a first register and a second register. The electronic device can write a value into the first register or read the value stored in the second register to detect the chip in the mobile terminal, which will be specifically introduced in the rest of the specification.
[0054] In some embodiments, the electronic device is connected to the writer via a USB cable.
[0055] In some embodiments, the writer is connected to a connection device with probes via DuPont wires in line sequence.
[0056] In some embodiments, the electronic device 110 is connected to a burner 120 via a USB cable, and the burner 120 is connected to a connecting device 130 with probes via DuPont wires in a certain line sequence. The probes of the connecting device 130 contact the burning contacts on the mobile terminal 140 in a line sequence. After the connection is completed, the electronic device 110 reads and writes the registers of the chip in the mobile terminal 140 through the SWD protocol to detect the chip, such as detecting the I / O port in the chip.
[0057] In some implementations, a firmware that can be burned into the chip can be directly designed. The electronic device 110 burns the firmware into the chip in the mobile terminal 140 through the SWD protocol, allowing the chip to perform autonomous detection through the firmware. The electronic device 110 is only used to obtain the detection results.
[0058] Optionally, the mobile terminal 140 is a mobile phone, the display screen is a mobile phone screen, and the chip is a scaler chip in the mobile phone screen.
[0059] In some embodiments, the chip includes multiple I / O ports, each of which includes an I / O port bit circuit, see Figure 2 , Figure 2 This is a first schematic diagram of an I / O port bit circuit provided by an embodiment of the present application. Figure 2As shown, the I / O port bit circuit 1 includes: a first register 10 , a first driving module 20 , a second driving module 30 , a second register 40 and an I / O pin 50 .
[0060] In some embodiments, the first register 10 is connected to the first driving module 20 ; the first driving module 20 is connected to the second driving module 30 and the I / O pin 50 ; and the second driving module 30 is connected to the second register 40 .
[0061] See also Figure 3 , Figure 3 This is a second schematic diagram of an I / O port bit circuit provided in an embodiment of the present application.
[0062] like Figure 3 As shown, in some embodiments, the second driving module 30 includes a detection resistor R1. The inventor of the present application analyzed a large number of chips with damaged I / O and found that when the chip I / O is damaged, the detection resistor R1 must be damaged first to form an open circuit, that is, the second register 40 fails, and then the high static electricity will continue to cause damage to the NMOS tube and / or PMOS at the first driving module 20, resulting in the failure of the first register 10. The subsequent detection of this application is also based on this principle.
[0063] In some implementations, the first register 10 may be written with 0 or 1 by the electronic device.
[0064] In some embodiments, when 0 is written to the first register of the first driving module 20, the NMOS is turned on and the PMOS is turned off, and a low-level signal is output to the second driving module 30; when 1 is written to the first register of the first driving module 20, the PMOS is turned on and the NMOS is turned off, and a high-level signal is output to the second driving module 30.
[0065] In some embodiments, the second driving module 30 further includes a voltage control submodule 31 , a first end of the detection resistor R1 is connected to the voltage control submodule 31 , and a second end of the detection resistor R1 is connected to the I / O pin and the first driving module 20 .
[0066] In some embodiments, the voltage control submodule 31 includes a first voltage source, a first switch K1 , a second voltage source, and a second switch K2 .
[0067] The first voltage source is connected to a first end of the first switch K1, and a second end of the first switch K1 is connected to the detection resistor R1 and the second register 40;
[0068] The second voltage source is connected to a first end of the second switch K2 , and a second end of the second switch K2 is connected to the detection resistor R1 and the second register 40 .
[0069] In some embodiments, the electronic device can control the first switch K1 and the second switch K2 to be turned on or off.
[0070] When the first switch K1 is turned on and the second switch K2 is turned off, the second register 40 is connected to the first voltage source, and the first voltage source is used to provide a low-level signal.
[0071] When the first switch K1 is turned off and the second switch K2 is turned on, the second register 40 is connected to the second voltage source, and the second voltage source is used to provide a high-level signal.
[0072] In some embodiments, the second driving module further includes a TTL Schottky trigger;
[0073] A first end of the TTL Schottky trigger is connected to the second register 40 , and a second end of the TTL Schottky trigger is connected to the second end of the first switch K1 , the second end of the second switch K2 , and the detection resistor R1 .
[0074] In some embodiments, the I / O port bit circuit 1 further includes a bit set / clear register 60 , which is used to control the value of a single bit in the first register 10 .
[0075] Specifically, a bit set / clear register is a type of register commonly found in computer hardware, especially embedded systems and microcontrollers. It allows users to set or clear specific bits individually without affecting other bits in the register.
[0076] Furthermore, a register generally includes a plurality of bits, and these bits can be independently set to 0 or 1. For example, a register includes an 8-bit register, a 16-bit register, a 32-bit register, and the like.
[0077] In some embodiments, the second register 40 corresponds to a transition threshold. When the voltage input to the second register 40 is less than the transition threshold, the value of the second register 40 is 0. When the voltage input to the second register 40 is greater than the transition threshold, the value of the second register 40 is 1.
[0078] In some embodiments, in order to achieve detection purposes, the level signal output by the first driving module 20 to the second driving module 30 is opposite to the level signal output by the voltage control submodule 31 .
[0079] In some embodiments, when the detection resistor R1 is normal and the I / O pin does not receive an external voltage, the second register 40 simultaneously receives opposite level signals output by the first driving module 20 and the voltage control submodule 31, but the value of the second register 40 is controlled by the level signal output by the first driving module 20 to the second driving module 30.
[0080] Exemplarily, when the detection resistor R1 is normal and the I / O pin does not receive an external voltage, if the first driver module 20 outputs a high-level signal to the second driver module 30, the voltage control submodule 31 outputs a low-level signal, and the value of the second register 40 is controlled to be 1 by the high-level signal output by the first driver module 20; if the first driver module 20 outputs a low-level signal to the second driver module 30, the voltage control submodule 31 outputs a high-level signal, and the value of the second register 40 is controlled to be 0 by the low-level signal output by the first driver module 20.
[0081] Furthermore, multiplexed I / O means that a physical I / O port can perform different functions according to different configurations or operating modes. This means that the same I / O port can be used for multiple purposes, such as being used as a general-purpose input / output (GPIO) and configured as a serial peripheral interface (SPI), an inter-integrated circuit (I2C), or other peripheral communication interfaces.
[0082] In some embodiments, due to the limited internal space of the device and the large number of peripherals that need to be connected, the chip design usually reuses the I / O ports as much as possible to reduce the number of pins. When the I / O port being tested is a multiplexed I / O port, there may be a strong pull-up or strong pull-down situation at the I / O pin.
[0083] Strong pull-up can be understood as a high-level signal being input to the I / O pin, and when the detection resistor R1 is normal, this high-level signal will always make the voltage received by the second register 40 higher than the transition threshold, so that the value written to the first register 10 cannot affect the value of the second register 40, that is, when the detection resistor R1 is normal, the strong pull-up will lock the value of the second register 40 to 1.
[0084] Strong pull-down can be understood as a low-level signal input at the I / O pin, and when the detection resistor R1 is normal, this low-level signal will always make the voltage received by the second register 40 lower than the jump threshold, so that the value written to the first register 10 cannot affect the value of the second register 40, that is, when the detection resistor R1 is normal, the strong pull-down will lock the value of the second register 40 to 0.
[0085] It is understandable that if the chip is removed for testing, there will be no strong pull-up and strong pull-down.
[0086] In the present application, the electronic device controls the level signal output by the first driver module by controlling the value written to the first register; controls the level signal output by the voltage control submodule by controlling the opening and closing of the first switch K1 and the second switch K2; and controls the level signal output by the first driver module and the level signal output by the voltage control submodule to be opposite, so that:
[0087] 1. When the detection resistor is damaged and the circuit is open, the value of the second register is controlled by the level signal output by the voltage control submodule; illustratively, when the voltage control submodule outputs a low-level signal, the value of the second register is 0; when the voltage control submodule outputs a high-level signal, the value of the second register is 1.
[0088] 2. When the detection resistor is normal and the I / O pin does not receive an external voltage, the value of the second register is controlled by the level signal output by the first driver module to the second driver module; illustratively, when the first driver module outputs a low-level signal, the value of the second register is 0; when the first driver module outputs a high-level signal, the value of the second register is 1.
[0089] 3. When the detection resistor is normal and the I / O pin receives an external voltage, the value of the second register is controlled by the external voltage; if the external voltage is a high-level signal, that is, there is a strong pull-up, the value of the second register is always 1; if the external voltage is a low-level signal, that is, there is a strong pull-down, the value of the second register is always 0.
[0090] Exemplarily, when the first driver module outputs a high-level signal by writing 1 to the first register and the voltage control submodule outputs a low-level signal by closing the first switch K1, the first value of the second register is read; when the first driver module outputs a low-level signal by writing 0 to the first register and the voltage control submodule outputs a high-level signal by closing the second switch K2, the second value of the second register is read.
[0091] As long as the first value of the second register is equal to 1 and / or the second value is equal to 0, it proves that the I / O port is not damaged. If the first value of the second register is equal to 0 and the second value is equal to 1, it proves that the I / O port is damaged.
[0092] Therefore, in the chip detection system of the present application, the electronic device is connected to the chip in the mobile terminal, specifically the register and switch of the scaler chip in the display screen of the mobile phone, so as to read the value of the second register under different control conditions. By analyzing the value of the second register, it is possible to determine whether the chip I / O port is damaged, and detection can be performed without removing the chip.
[0093] In summary, the present application provides a chip detection system, comprising: an electronic device connected to a programmer; the programmer connected to a connection device with probes; the connection device, wherein the probes in the connection device contact programming contacts on the mobile terminal; the mobile terminal, including the programming contacts and a chip; and the electronic device for controlling the chip. In the present application, the electronic device is directly connected to the mobile terminal via the programmer and the connection device, and can detect the chip in the mobile terminal without removing the chip from the mobile terminal for detection.
[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A chip detection system, characterized in that: The system comprises: Electronic equipment connected to the programmer; A programmer connected to a connecting device with a probe; A connecting device, wherein a probe in the connecting device contacts a burning contact on the mobile terminal; The mobile terminal includes a programming contact and a chip; The electronic device is used to control the chip.
2. The system according to claim 1, wherein: The connecting device contacts the burning contact of the display screen on the mobile terminal through the probe; The electronic device is used to control the chip in the display screen on the mobile terminal.
3. The system according to claim 2, characterized in that The chip includes a scaler chip.
4. The system according to claim 2, wherein: The electronic device reads and writes registers of the I / O ports in the chip through the SWD protocol.
5. The system according to claim 1, wherein: The electronic device is connected to the writer via a USB cable.
6. The system according to claim 1, wherein: The writer is connected to the connection device with probes through DuPont lines in line sequence.
7. The system according to claim 1, wherein: The chip includes at least one I / O port, each of the I / O ports includes an I / O port bit circuit, and the I / O port bit circuit includes a first register, a first driver module, a second driver module, a second register, and an I / O pin; The first register is connected to the first driving module; The first driving module is connected to the second driving module and the I / O pin; The second driving module is connected to the second register.
8. The system according to claim 7, characterized in that The second driving module includes a voltage control submodule and a detection resistor; A first end of the detection resistor is connected to the voltage control submodule, and a second end of the detection resistor is connected to the I / O pin and the first driving module.
9. The system according to claim 8, characterized in that The voltage control submodule includes a first voltage source, a first switch, a second voltage source and a second switch; The first voltage source is connected to a first end of the first switch, and a second end of the first switch is connected to the detection resistor and the second register; The second voltage source is connected to a first end of the second switch, and a second end of the second switch is connected to the detection resistor and the second register.
10. The system according to claim 9, characterized in that The second driving module further includes a TTL Schottky trigger; A first end of the TTL Schottky trigger is connected to the second register, and a second end of the TTL Schottky trigger is connected to the second end of the first switch, the second end of the second switch, and the detection resistor.