Chip packaging structure integrating CIS-TSV technology and FOPLP technology

Abstract

The utility model discloses a chip packaging structure integrating a CIS-TSV technology and an FOPLP technology. The chip packaging structure comprises a wafer-level glass bearing plate and a wafer-level CIS chip, bonding the wafer-level CIS chip with the bearing plate, and arranging a first conductive through hole structure on the wafer-level CIS chip; a first metal rewiring layer is arranged, and a plurality of wafer-level CIS chips are pasted on the bearing plate to form a plate-level composite body; a first plastic package layer is arranged on the first chip, and a second chip is pasted on the first plastic package layer to form a second plastic package layer; a second conductive through hole structure and a third conductive through hole structure are sequentially arranged on the second plastic packaging layer, and a second metal charging and wiring layer is formed; an insulating layer, a conductive structure through hole and a third metal rewiring layer are sequentially arranged on the second metal rewiring layer; reballing on the third metal rewiring layer, and removing the board-level bearing board and the adhesive film; and cutting to obtain a single chip. According to the packaging structure, integration of the CIS chip and other types of chips can be achieved, the packaging process is completed through the FOWLP technology, integration of different types of chips is achieved, meanwhile, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor chip packaging, in particular to a chip packaging structure integrating CIS-TSV technology and FOPLP technology. Background Art

[0002] A CMOS image sensor (CIS) is an image sensor based on the semiconductor CMOS process and began widespread commercialization in the late 1990s. Currently, CIS chips are widely used in mobile phones, cameras, automotive electronics, security, and other fields. As mobile consumer electronics such as mobile phones, computers, and digital cameras increasingly demand high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system-integrated electronic product packaging, high-density, multi-type chip system-in-package products are becoming mainstream in the next generation of electronic products. Currently, CIS chips are primarily manufactured using wafer-level packaging (CIS-TSV) technology.

[0003] The difference between the fan-out panel level package (FOPLP) process and FOWLP is that it uses a larger panel instead of a wafer, and there are differences in the materials, equipment, and line width and line spacing of the products used. The emergence of FOPLP technology can effectively achieve larger overall packaging, further increase packaging efficiency, reduce packaging costs, and have broader development prospects. At present, the size of FOPLP samples has gradually developed from the initial 300*300mm to 500*500mm, 600*600mm, and even larger package sizes. Compared with FOWLP technology, FOPLP technology has the advantages of lower cost, flexible design, good electrothermal performance, diverse business models and a wide range of applications.

[0004] Based on the respective advantages of CIS-TSV technology and FOPLP technology, how to integrate CIS-TSV technology with FOPLP technology and prepare high-density, multi-type chip system packaging electronic products with high performance, low power consumption, miniaturization, heterogeneous process integration and low cost is gradually becoming a hot technology in the chip packaging field. Utility Model Content

[0005] To address the aforementioned technical issues, the present invention aims to provide a chip packaging structure that integrates CIS-TSV and FOPLP technologies. This packaging structure and method can achieve the integration of CIS-TSV and FOPLP technologies, significantly improving packaging efficiency and reducing processing costs while enabling the integration of different types of chips.

[0006] A chip packaging structure integrating CIS-TSV technology and FOPLP technology, comprising a wafer-level glass carrier plate (10) and a wafer-level CIS chip (12); a cofferdam structure (11) is provided on the wafer-level glass carrier plate (10);

[0007] Bonding the wafer-level CIS chip (12) to a wafer-level glass carrier plate (10);

[0008] A first conductive through-hole structure (204) is provided on the back side of the bonded wafer-level CIS chip;

[0009] A first metal redistribution layer (15) is provided at the first conductive through-hole structure (204), and a plurality of wafer-level CIS chips provided with the first metal redistribution layer (15) are adhered to a board-level carrier plate (301) to form a board-level composite body; and a first plastic sealing layer (16) is provided on the board-level composite body;

[0010] Pasting a second chip (18) on the first plastic packaging layer (16) of the board-level composite body; forming a second plastic packaging layer (207) on the second chip (18) of the board-level composite body;

[0011] Arranging a second / third conductive through-hole structure (208, 209) on the second plastic packaging layer (207) on the board-level composite;

[0012] forming a second metal-filled wiring layer (21) on the second / third conductive through-hole structure (208, 209) of the board-level composite;

[0013] An insulating layer (22) and a conductive structure through hole (211) are provided on the second metal-filled wiring layer (21) of the board-level composite body;

[0014] A third metal redistribution layer (23) is provided on the insulating layer (22) and the conductive structure through hole (211) of the board-level complex; balls are planted on the third metal redistribution layer (23) of the board-level complex; a board-level carrier plate and an adhesive film are removed from the board-level complex; and single chips are obtained by cutting.

[0015] The beneficial effects of the present invention are mainly the following three points: (1) Integrating wafer-level packaging technology with board-level packaging technology to fully utilize wafer-level packaging equipment and technology and board-level packaging equipment and technology. (2) Integrating CIS chips with other types of chips (second chips) to achieve high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products. (3) Most of the process steps in the entire packaging process are board-level packaging, which has high packaging efficiency, low cost, and large production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 、 Figure 2A cofferdam structure is formed on a wafer-level high-transmittance glass carrier plate.

[0017] Figure 3 For the general Figure 1 / 2 Schematic diagram of the structure shown in Figure 2 being bonded to a wafer-level CIS chip through a pressing process.

[0018] Figure 4 For the general Figure 3 In the structure shown, the back side of the wafer-level CIS chip is thinned and a conductive through-hole structure is formed at a position corresponding to the Al Pad structure.

[0019] Figure 5 For Figure 4 A first metal redistribution layer is formed at the conductive via structure in the wafer-level structure.

[0020] Figure 6 / 7 for generals Figure 5 Schematic diagram of the wafer-level structure attached to the carrier plate.

[0021] Figure 8 For Figure 6 / The board-level composite shown in 7 is pasted on top of the wafer to form the first plastic packaging layer.

[0022] Figure 9 Schematic diagram of the Die structure on the upper part of the board-level complex.

[0023] Figure 10 For Figure 9 The schematic diagram of the structure of the second chip is pasted on the first plastic packaging layer of the board-level complex.

[0024] Figure 11 For Figure 10 A second plastic packaging layer is formed on the board-level composite.

[0025] Figure 12 For Figure 11 A related conductive through-hole structure is formed on the second plastic packaging layer of the board-level composite.

[0026] Figure 13 For Figure 12 A second metal redistribution layer is formed on the board-level composite.

[0027] Figure 14 For Figure 13 An insulating layer and a conductive via structure are formed on the board-level composite.

[0028] Figure 15 For Figure 14 A third metal redistribution layer is formed on the board-level composite structure.

[0029] Figure 16 For Figure 15The ball planting process is formed on the board-level complex shown.

[0030] Figure 17 To dismantle Figure 16 Schematic diagram of the board-level composite carrier board and adhesive film.

[0031] Figure 18 Schematic diagram of a single chip obtained after cutting. DETAILED DESCRIPTION

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0033] (1) Figure 1 The cofferdam structure is formed on the wafer-level high-transmittance glass carrier plate as shown in FIG. Figure 1 The structure shown. 10 is a wafer-level high-transmittance glass carrier plate, 11 is a cofferdam structure. 201 is the lower surface of the wafer-level high-transmittance glass carrier plate, and 202 is the upper surface of the wafer-level high-transmittance glass carrier plate. Figure 1 The adhesive layer is formed on the cofferdam structure shown by rolling glue or printing glue to obtain the following Figure 2 The structure shown. 11a is the adhesive layer. (The adhesive layer is relatively thin and will not be shown in detail in the subsequent steps.)

[0034] (2) Figure 1 The structure shown in / 2 is bonded to the wafer-level CIS chip (8-inch or 12-inch) through a press bonding process to obtain Figure 3 The structure shown in the figure is described using a portion of the die structure in a wafer-level sample as an example. 12 is the wafer-level CIS chip, 13 is the wafer-level CIS chip conductive structure (i.e., Al pad), 14 is the wafer-level CIS chip photosensitive area, and 203 is the bottom surface of the wafer-level CIS chip.

[0035] (3) Figure 3 In the structure shown, the back of the wafer-level CIS chip is thinned, and a conductive through-hole structure is formed at a position corresponding to the Al Pad structure, as shown in FIG. Figure 4 The structure shown in FIG. 204 is a first conductive through-hole structure.

[0036] (4) Figure 4 The first metal redistribution layer is formed at the conductive via structure in the wafer-level structure shown in FIG. Figure 5 The structure shown in FIG. 15 is the first metal redistribution layer.

[0037] (5) Figure 5 The wafer-level structure shown is pasted on the carrier plate (glass carrier plate facing down), and the Figure 6The structure shown. 301 is a carrier plate, 302 is an adhesive film, and 303 is a wafer-level structure. In this step, the size of the carrier plate is usually 2 times, 4 times, or a larger multiple of the size of the wafer-level structure. In this embodiment, the size of the carrier plate is 4 times that of the wafer-level structure, that is, 4 wafer-level structures can be attached to the carrier plate at the same time, thereby obtaining a board-level composite structure. The top view of the board-level composite structure is shown in FIG. Figure 7 As shown, the side view of the board-level complex is as follows Figure 8 Wherein 205 is the lower surface of the carrying plate.

[0038] (6) In Figure 8 The board-level composite body shown is attached to the wafer to form a first plastic layer, and the Figure 9 The structure shown in FIG. 16 is the first plastic sealing layer, and 206 is the upper surface of the plastic sealing layer.

[0039] (7) Figure 9 The figure shows the die structure of the upper portion of the board-level composite. All subsequent steps are described based on this structure. 10 is the glass carrier plate, 11 is the cofferdam structure, 12 is the CIS chip, 13 is the CIS chip conductive structure (i.e., Al Pad), 14 is the CIS chip photosensitive area, 15 is the first metal redistribution layer, 16 is the first plastic layer, 205 is the lower surface of the carrier plate, and 206 is the upper surface of the first plastic layer.

[0040] (8) Figure 9 The second chip (the second chip is usually a non-CIS chip) is attached to the first plastic packaging layer of the board-level composite body, and the following is obtained: Figure 10 17 is the adhesive film layer, 18 is the second chip, and 19 is the conductive structure of the second chip (i.e., Al Pad).

[0041] (9) Figure 10 A second plastic encapsulation layer is formed on the board-level composite body shown in FIG. Figure 11 The structure shown in FIG. 20 is the second plastic sealing layer, and 207 is the upper surface of the second plastic sealing layer.

[0042] (10) Figure 11 The second / third conductive through-hole structure is formed on the second plastic packaging layer of the board-level composite body shown in FIG. Figure 12 The structure shown in FIG. 208 and 209 are the second and third conductive via structures. It is worth noting that the third conductive via structure 209 must correspond to the second chip conductive structure 19, and the position of the second conductive via structure 208 must be staggered with the position of the second chip conductive structure 19.

[0043] (11) Figure 12 A second metal redistribution layer is formed on the board-level composite body as shown, and the Figure 13The structure shown in FIG. 21 is the second metal redistribution layer.

[0044] (12) Figure 13 An insulating layer and a conductive through-hole structure are formed on the board-level composite body as shown, and a Figure 14 22 is an insulating layer, 210 is an upper surface of the insulating layer, and 211 is a conductive through-hole structure formed on the insulating layer.

[0045] (13) Figure 14 A third metal redistribution layer is formed on the board-level composite structure shown in FIG. Figure 15 The structure shown in FIG. 23 is the third metal redistribution layer.

[0046] (14) Figure 15 The ball planting process is formed on the board-level complex shown in the figure, and the Figure 16 The structure shown in FIG. 24 is a conductive structure (i.e., a solder ball).

[0047] (15) Demolition Figure 16 The board-level composite carrier board and adhesive film are shown to obtain Figure 17 The structure shown.

[0048] (16) is cut to obtain Figure 18 A single chip with the structure shown.

[0049] like Figure 18 As shown in the structure, the present embodiment prepares a system-integrated electronic product with high performance, low power consumption, miniaturization, heterogeneous process integration, and low cost by integrating CIS-TSV technology and FOPLP technology. The specific layers in the structure are as follows: 10-glass carrier plate, 11-cofferdam structure, 12-CIS chip, 13-CIS chip conductive structure (Al Pad), 14-CIS chip photosensitive area, 15-first metal redistribution layer, 16-first plastic sealing layer, 17-adhesive film, 18-second chip, 19-second chip conductive structure (Al Pad), 20-second plastic sealing layer, 21-second metal redistribution layer, 22-insulating layer, 23-third metal redistribution layer, 24-conductive structure (solder ball).

[0050] It is worth noting that: in the description of this utility model, the meaning of "plurality" is two or more, unless otherwise clearly specified and specifically defined. In this utility model, unless otherwise clearly specified and defined, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in this utility model are all commonly used circuits in the field, and other related components are all existing commonly used components. For ordinary technicians in this field, the specific meanings of the above terms in this utility model can be understood according to the specific circumstances.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and is intended to encompass all variations within the meaning and scope of the claims. Any reference signs in the claims should not be construed as limiting the claim to which they relate.

Claims

1. A chip packaging structure integrating CIS-TSV technology and FOPLP technology, characterized in that: It comprises a wafer-level glass carrier plate (10) and a wafer-level CIS chip (12); a cofferdam structure (11) is provided on the wafer-level glass carrier plate (10); Bonding the wafer-level CIS chip (12) to a wafer-level glass carrier plate (10); A first conductive through-hole structure (204) is provided on the back side of the bonded wafer-level CIS chip; A first metal redistribution layer (15) is provided at the first conductive through-hole structure (204), and a plurality of wafer-level CIS chips provided with the first metal redistribution layer (15) are adhered to a board-level carrier plate (301) to form a board-level composite body; and a first plastic sealing layer (16) is provided on the board-level composite body; Pasting a second chip (18) on the first plastic packaging layer (16) of the board-level composite body; forming a second plastic packaging layer (207) on the second chip (18) of the board-level composite body; A second conductive through-hole structure (208) and a third conductive through-hole structure (209) are provided on the second plastic packaging layer (207) on the board-level composite body; forming a second metal-filled wiring layer (21) on the second conductive through-hole structure (208) and the third conductive through-hole structure (209) of the board-level composite; An insulating layer (22) and a conductive structure through hole (211) are provided on the second metal-filled wiring layer (21) of the board-level composite body; A third metal redistribution layer (23) is provided on the insulating layer (22) and the conductive structure through hole (211) of the board-level complex; balls are planted on the third metal redistribution layer (23) of the board-level complex; a board-level carrier plate and an adhesive film are removed from the board-level complex; and single chips are obtained by cutting.

2. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 1, characterized in that: An adhesive layer (11a) is formed on the cofferdam structure by a glue rolling or glue printing process.

3. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 1, characterized in that: The wafer-level glass carrier plate (10) and the wafer-level CIS chip (12) are bonded by a pressing process; the back of the bonded wafer-level CIS chip is thinned, and a conductive through-hole structure is formed at a position corresponding to the conductive structure (13) of the wafer-level CIS chip.

4. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 1, characterized in that: The third conductive through-hole structure (209) must correspond to the second chip conductive structure (19), and the position of the second conductive through-hole structure (208) must be staggered with the position of the second chip conductive structure (19).

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