P-type heterojunction cell and photovoltaic module
By using a combination of carbon-doped polysilicon and silicon oxide layers in heterojunction cells, the high cost issue is resolved, enabling efficient and economical production of photovoltaic modules.
Patent Information
- Application Number
- CN202422158729.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-09-02
AI Technical Summary
Existing heterojunction cells have high production costs while maintaining high conversion efficiency.
Carbon-doped polysilicon is used as the doping layer and silicon oxide is used as the tunneling layer to replace the traditional hydrogenated amorphous silicon and hydrogenated microcrystalline silicon structures, simplifying the polysilicon manufacturing process and reducing energy consumption.
While ensuring conversion efficiency, the production cost is reduced, the band gap width and filling efficiency of polysilicon are improved, and the stability and durability of the battery are enhanced.
Smart Images
Figure CN223402765U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of solar cells, in particular to a P-type heterojunction cell and a photovoltaic module. Background Art
[0002] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0003] The heterojunction battery in the prior art has the technical problem of maintaining high conversion efficiency while having excessively high production costs. Utility Model Content
[0004] The utility model provides a P-type heterojunction battery and a photovoltaic module, which can reduce production costs while ensuring conversion efficiency.
[0005] The embodiment of the present utility model can be implemented as follows:
[0006] The embodiment of the present utility model provides a P-type heterojunction battery, which includes a silicon wafer, a first passivation layer, a doping layer, a tunneling layer, an amorphous silicon thin film layer and a second passivation layer;
[0007] Among them, the first passivation layer, doping layer and tunneling layer are arranged on the front side of the silicon wafer, the amorphous silicon thin film layer and the second passivation layer are arranged on the back side of the silicon wafer, the doping layer is a carbon-doped polysilicon layer, and the tunneling layer is a silicon oxide layer.
[0008] Optionally, the thickness of the doping layer is 20 nm-70 nm.
[0009] Optionally, the thickness of the tunneling layer is 0.8 nm-3 nm.
[0010] Optionally, the P-type heterojunction battery also includes a first electrode and a second electrode, the first electrode is arranged on the first passivation layer, the second electrode is arranged on the back side of the silicon wafer, and one end of the second electrode is used to pass through the amorphous silicon film and the second passivation layer, thereby making ohmic contact with the back side of the silicon wafer.
[0011] Optionally, the thickness of the amorphous silicon thin film layer is 5nm-30nm.
[0012] Optionally, the sum of the thickness of the tunneling layer and the thickness of the doping layer is 0.8 times to 2.5 times the thickness of the amorphous silicon thin film layer.
[0013] Optionally, the thickness of the silicon wafer is 80 μm-180 μm.
[0014] Optionally, the thickness of the first passivation layer is 70 nm to 120 nm; and / or,
[0015] The thickness of the second passivation layer is 80 nm-140 nm.
[0016] Optionally, the first passivation layer is a transparent conductive oxide film; and / or,
[0017] The second passivation layer is a transparent conductive oxide film.
[0018] An embodiment of the present invention further provides a photovoltaic assembly, comprising at least one cell string, wherein the cell string comprises at least two P-type heterojunction cells.
[0019] The beneficial effects of the P-type heterojunction cell and photovoltaic module of the present invention include, for example:
[0020] The P-type heterojunction cell includes a silicon wafer, a first passivation layer, a doping layer, a tunneling layer, an amorphous silicon thin film layer, and a second passivation layer; wherein the first passivation layer, doping layer, and tunneling layer are arranged on the front side of the silicon wafer, the amorphous silicon thin film layer and the second passivation layer are arranged on the back side of the silicon wafer, the doping layer is a carbon-doped polycrystalline silicon layer, and the tunneling layer is a silicon oxide layer. During use, the doping layer is made of carbon-doped polycrystalline silicon material, and the tunneling layer is made of silicon oxide. Carbon doping can increase the band gap width of polycrystalline silicon, thereby improving filling efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in the prior art, and the manufacturing process of polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs. The P-type heterojunction cell can reduce production costs while ensuring conversion efficiency.
[0021] This photovoltaic module includes at least one cell string, each comprising at least two P-type heterojunction cells. During use, the doping layer utilizes carbon-doped polycrystalline silicon, while the tunneling layer utilizes silicon oxide. Carbon doping increases the bandgap of the polycrystalline silicon, thereby improving fill efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in existing technologies, and the manufacturing process for polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 This is a schematic structural diagram of the P-type heterojunction battery provided in this embodiment.
[0024] Icon: 10 - first passivation layer; 20 - doping layer; 30 - tunneling layer; 40 - silicon wafer; 50 - amorphous silicon thin film layer; 60 - second passivation layer; 70 - first electrode; 80 - second electrode. DETAILED DESCRIPTION
[0025] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.
[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0028] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the utility model product is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.
[0029] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.
[0030] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention can be combined with each other.
[0031] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0032] The heterojunction battery in the prior art has the technical problem of maintaining high conversion efficiency while having excessively high production costs.
[0033] This embodiment provides a photovoltaic module comprising at least one cell string including at least two P-type heterojunction cells, which can effectively address the aforementioned technical issues and reduce production costs while maintaining conversion efficiency.
[0034] Please refer to Figure 1 This embodiment provides a P-type heterojunction battery including a silicon wafer 40, a first passivation layer 10, a doping layer 20, a tunneling layer 30, an amorphous silicon thin film layer 50 and a second passivation layer 60; wherein, the first passivation layer 10, the doping layer 20, and the tunneling layer 30 are arranged on the front side of the silicon wafer 40, the amorphous silicon thin film layer 50 and the second passivation layer 60 are arranged on the back side of the silicon wafer 40, the doping layer 20 is a carbon-doped polycrystalline silicon layer, and the tunneling layer 30 is a silicon oxide layer.
[0035] It can be understood that the tunneling layer 30 , the doping layer 20 and the first passivation layer 10 are sequentially stacked on the front side of the silicon wafer 40 , and the amorphous silicon thin film layer 50 and the second passivation layer 60 are sequentially stacked on the back side of the silicon wafer 40 .
[0036] Specifically, the doping layer 20 and tunneling layer 30 in the prior art generally adopt a-Si:H and uc-Si:H structures. a-Si:H is a hydrogenated amorphous silicon layer that can passivate the heterojunction cell, reducing interface defects and internal recombination; uc-Si:H is a hydrogenated microcrystalline silicon layer that needs to be doped with N / P-type elements to act as a built-in electric field to collect carriers. Compared to amorphous silicon, microcrystalline silicon can achieve higher conversion efficiency. However, the manufacturing technology of microcrystalline silicon is complex and the cost is high in various aspects. To address this technical problem, the doping layer 20 of the P-type heterojunction cell provided in this embodiment uses carbon-doped polycrystalline silicon and the tunneling layer 30 uses silicon oxide. Carbon doping can increase the band gap of polycrystalline silicon, thereby improving filling efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in the prior art, and the manufacturing process of polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs. This P-type heterojunction cell can reduce production costs while maintaining conversion efficiency.
[0037] It should be noted that the use of carbon-doped polysilicon in the doping layer 20 can reduce recombination centers, wherein carbon, as an effective recombination center passivator, can reduce non-radiative recombination, thereby increasing carrier lifetime; carbon doping can also improve the passivation effect of the polysilicon surface; and carbon doping helps to improve the stability and durability of heterojunction batteries.
[0038] In addition, compared with single crystal silicon in the prior art, the manufacturing process of polycrystalline silicon is simpler and the manufacturing cost is lower. The doping layer 20 made of carbon-doped polycrystalline silicon can reduce the production cost while ensuring the conversion efficiency.
[0039] In this embodiment, the thickness of the doping layer 20 is 20 nm to 70 nm. Specifically, the thickness of the doping layer 20 is 20 nm. In other embodiments, the thickness of the doping layer 20 may also be 24 nm, 30 nm, 45 nm, 70 nm, etc., which is not specifically limited here.
[0040] In this embodiment, the thickness of the tunneling layer 30 is 0.8 nm to 3 nm. Specifically, the thickness of the tunneling layer 30 is 0.8 nm. In other embodiments, the thickness of the tunneling layer 30 may also be 0.9 nm, 1.2 nm, 2 nm, 3 nm, etc., which is not specifically limited here.
[0041] In this embodiment, the thickness of the amorphous silicon thin film layer 50 is 5 nm to 30 nm. Specifically, the thickness of the amorphous silicon thin film layer 50 is 5 nm. In other embodiments, the thickness of the amorphous silicon layer can also be 5.7 nm, 6 nm, 20 nm, 30 nm, etc., which are not specifically limited here.
[0042] In this embodiment, the sum of the thickness of the tunneling layer 30 and the thickness of the doping layer 20 is 0.8 to 2.5 times the thickness of the amorphous silicon thin film layer 50. Specifically, the sum of the thickness of the tunneling layer 30 and the thickness of the doping layer 20 is 0.8 times the thickness of the amorphous silicon thin film layer 50. In other embodiments, the sum of the thickness of the tunneling layer 30 and the thickness of the doping layer 20 may also be 1 times, 1.2 times, 2.5 times, etc., the thickness of the amorphous silicon thin film layer 50, and is not specifically limited here.
[0043] It should be noted that the amorphous silicon thin film layer 50 is made of aluminum oxide material, specifically Al2O3 thin film. The amorphous silicon thin film layer 50 can also be made of aluminum nitride, phosphorus nitride or titanium nitride.
[0044] In this embodiment, the thickness of the silicon wafer 40 is 80 μm-180 μm. Specifically, the thickness of the silicon wafer 40 is 80 μm. In other embodiments, the thickness of the silicon wafer 40 can be 100 μm, 120 μm, 180 μm, etc., which is not specifically limited here.
[0045] More preferably, the resistivity of the silicon wafer 40 is 0.1 Ω·cm-10 Ω·cm. Specifically, the resistivity of the silicon wafer 40 is 0.1 Ω·cm, 1 Ω·cm, 4 Ω·cm, 10 Ω·cm, etc., which is not specifically limited here.
[0046] In this embodiment, the thickness of the first passivation layer 10 is 70 nm to 120 nm, and the thickness of the second passivation layer 60 is 80 nm to 140 nm. Specifically, the thickness of the first passivation layer 10 is 70 nm, and the thickness of the second passivation layer 60 is 80 nm. In other embodiments, the thickness of the first passivation layer 10 may be 92 nm, 100 nm, or 120 nm, and the thickness of the second passivation layer 60 may be 85 nm, 108 nm, 128 nm, or 140 nm, without specific limitation herein.
[0047] Specifically, the thickness of the second passivation layer 60 needs to be greater than the thickness of the first passivation layer 10, so as to reduce the recombination on the back side of the silicon wafer 40. The second passivation layer 60 is located on the back side of the silicon wafer 40, which can effectively reduce the recombination rate on the back surface of the silicon wafer 40, thereby improving the carrier lifetime.
[0048] In this embodiment, the first passivation layer 10 and the second passivation layer 60 are both transparent conductive oxide films. Specifically, the transparent conductive oxide film is deposited on the silicon wafer 40 using PVD technology or PRD technology. The material of the transparent conductive oxide film includes but is not limited to a tin-doped indium oxide (ITO) film, a tungsten-doped indium oxide (IWO) film, a titanium-doped indium oxide (ITiO) film, or an aluminum-doped zinc oxide (AZO) film.
[0049] In addition, the P-type heterojunction battery also includes a first electrode 70 and a second electrode 80. The first electrode 70 is arranged on the first passivation layer 10, and the second electrode 80 is arranged on the back of the silicon wafer 40. One end of the second electrode 80 is used to pass through the amorphous silicon film and the second passivation layer 60, thereby making ohmic contact with the back of the silicon wafer 40.
[0050] It should also be noted that the preparation method of the P-type heterojunction battery includes:
[0051] S1: Cleaning and velveting.
[0052] Specifically, a silicon wafer 40 is provided, the silicon wafer 40 is cleaned to remove organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer 40 , and then a velvet layer is formed on the front side of the silicon wafer 40 after cleaning.
[0053] S2: Deposition of the passivation and doping layer 20 .
[0054] Specifically, a tunneling layer 30 and an N-type doping layer 20-Si:H(n+) are deposited on a silicon wafer 40 using techniques including but not limited to PECVD, HWCVD or LPCVD. After the doping layer 20 is prepared, a high-temperature annealing treatment is performed at a temperature of 750°C-900°C to form carbon-doped polysilicon Poly-Si(n+).
[0055] Then, Al 2 O 3 is deposited on the back side of the silicon wafer 40 using a technique including but not limited to PECVD, HWCVD or ALD.
[0056] S3 : depositing a first passivation layer 10 and a second passivation layer 60 on the front and back sides of the silicon wafer 40 .
[0057] S4: Metallization of the silicon wafer 40.
[0058] Specifically, screen printing technology or electroplating technology is used for metallization, and the heterojunction battery pattern adopts a multi-busbar or no busbar solution.
[0059] The P-type heterojunction cell and photovoltaic module provided in this embodiment have at least the following advantages:
[0060] The doping layer 20 and tunneling layer 30 in the prior art generally adopt a-Si:H and uc-Si:H structures. The a-Si:H is a hydrogenated amorphous silicon layer that can passivate the heterojunction cell, reducing interface defects and internal recombination. The uc-Si:H is a hydrogenated microcrystalline silicon layer that needs to be doped with N / P-type elements to act as a built-in electric field to collect carriers. Compared to amorphous silicon, microcrystalline silicon can achieve higher conversion efficiency. However, the manufacturing technology of microcrystalline silicon is complex and the cost is high. To address this technical problem, the doping layer 20 of the P-type heterojunction cell provided in this embodiment uses carbon-doped polycrystalline silicon and the tunneling layer 30 uses silicon oxide. Carbon doping can increase the band gap of polycrystalline silicon, thereby improving filling efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in the prior art, and the manufacturing process of polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs. This P-type heterojunction cell can reduce production costs while maintaining conversion efficiency.
[0061] The doping layer 20 of the P-type heterojunction battery uses carbon-doped polysilicon to reduce recombination centers. Carbon, as an effective recombination center passivator, can reduce non-radiative recombination, thereby increasing carrier lifetime. Carbon doping can also improve the passivation effect of the polysilicon surface. In addition, carbon doping helps to improve the stability and durability of the heterojunction battery.
[0062] In addition, the doping layer 20 of the P-type heterojunction battery uses carbon-doped polycrystalline silicon. Compared with the single crystal silicon in the prior art, the manufacturing process of polycrystalline silicon is simpler and the manufacturing cost is lower. The doping layer 20 made of carbon-doped polycrystalline silicon can reduce production costs while ensuring conversion efficiency.
[0063] In summary, the embodiments of the present invention provide a P-type heterojunction cell and photovoltaic module. The P-type heterojunction cell includes a first passivation layer 10, a doping layer 20, a tunneling layer 30, a silicon wafer 40, an amorphous silicon thin film layer 50, and a second passivation layer 60, which are stacked in sequence from top to bottom. The doping layer 20 is a carbon-doped polycrystalline silicon layer, and the tunneling layer 30 is a silicon oxide layer. During use, the doping layer 20 is made of carbon-doped polycrystalline silicon material, and the tunneling layer 30 is made of silicon oxide. Carbon doping can increase the band gap of polycrystalline silicon, thereby improving filling efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in the prior art, and the manufacturing process of polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs. This P-type heterojunction cell can reduce production costs while ensuring conversion efficiency.
[0064] The photovoltaic module includes at least one cell string, each comprising at least two P-type heterojunction cells. During use, the doping layer 20 is made of carbon-doped polycrystalline silicon, and the tunneling layer 30 is made of silicon oxide. Carbon doping increases the bandgap of the polycrystalline silicon, thereby improving fill efficiency. The energy consumption of polycrystalline silicon during production is lower than that of microcrystalline silicon in the prior art, and the manufacturing process for polycrystalline silicon is simpler than that of microcrystalline silicon, thereby reducing production costs.
[0065] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this utility model should be included in the scope of protection of the present utility model. Therefore, the scope of protection of the present utility model should be based on the scope of protection of the claims.
Claims
1. A P-type heterojunction battery, characterized in that: It comprises a silicon wafer (40), a first passivation layer (10), a doping layer (20), a tunneling layer (30), an amorphous silicon thin film layer (50) and a second passivation layer (60); The first passivation layer (10), the doping layer (20) and the tunneling layer (30) are arranged on the front side of the silicon wafer (40), the amorphous silicon thin film layer (50) and the second passivation layer (60) are arranged on the back side of the silicon wafer (40), the doping layer (20) is a carbon-doped polysilicon layer, and the tunneling layer (30) is a silicon oxide layer.
2. The P-type heterojunction battery according to claim 1, characterized in that: The thickness of the doping layer (20) is 20nm-70nm.
3. The P-type heterojunction battery according to claim 1, characterized in that: The thickness of the tunneling layer (30) is 0.8 nm to 3 nm.
4. The P-type heterojunction battery according to claim 1, characterized in that: The P-type heterojunction battery further includes a first electrode (70) and a second electrode (80), wherein the first electrode (70) is arranged on the first passivation layer (10), and the second electrode (80) is arranged on the back side of the silicon wafer (40), and one end of the second electrode (80) is used to pass through the amorphous silicon thin film and the second passivation layer (60), thereby making ohmic contact with the back side of the silicon wafer (40).
5. The P-type heterojunction battery according to claim 1, characterized in that: The thickness of the amorphous silicon thin film layer (50) is 5nm-30nm.
6. The P-type heterojunction battery according to claim 1, characterized in that: The sum of the thickness of the tunneling layer (30) and the thickness of the doping layer (20) is 0.8 to 2.5 times the thickness of the amorphous silicon thin film layer (50).
7. The P-type heterojunction battery according to claim 1, characterized in that: The thickness of the silicon wafer (40) is 80 μm-180 μm.
8. The P-type heterojunction battery according to claim 1, characterized in that: The thickness of the first passivation layer (10) is 70 nm to 120 nm; and / or, The thickness of the second passivation layer (60) is 80nm-140nm.
9. The P-type heterojunction battery according to claim 1, characterized in that: The first passivation layer (10) is a transparent conductive oxide film; and / or, The second passivation layer (60) is a transparent conductive oxide film.
10. A photovoltaic module, characterized in that: The invention comprises at least one battery string, wherein the battery string comprises at least two P-type heterojunction batteries according to any one of claims 1 to 9.