Multi-test equipment cooperative control and data processing device

Abstract

The utility model discloses a multi-test equipment cooperative control and data processing device, which is characterized in that the processing device receives TCP protocol issuing data sent by an upper computer through an Ethernet transceiver, and a data processing module extracts the number of target test equipment to generate a control signal and encapsulates the TCP protocol issuing data into UDP (User Datagram Protocol) data; the bus control module receives the control signal and receives UDP data through the master control PHY chip; the Ethernet transceiving array comprises a plurality of slave control PHY chips, and any slave control PHY chip corresponds to one interface used for being in communication connection with test equipment; and the bus control module starts the slave control PHY chip corresponding to the serial number, sends the UDP data to the target test equipment, triggers the target test equipment to return the information, converts the return information into TCP protocol return data, and sends the TCP protocol return data to the upper computer. According to the invention, efficient cooperative control of multiple to-be-tested devices can be realized, and the burden of the upper computer is reduced.

Description

Technical Field

[0001] The present application relates to the field of digital communication technology, and in particular to a device for collaborative control and data processing of multiple test devices. Background Art

[0002] In existing automated test systems, remote control and data testing of multiple devices typically requires a host computer to establish communication links with each test device via Ethernet. However, existing technologies often rely on a single communication mode, requiring the host computer to directly participate in protocol conversion, target test device selection, and data transmission during the test process. This places a heavy burden on the host computer and reduces the overall response speed of the test system. Utility Model Content

[0003] In order to solve the deficiencies of the prior art, this application adopts the following technical solutions:

[0004] The present application provides a multi-test equipment collaborative control and data processing device, the device comprising:

[0005] Ethernet transceiver, including an RJ45 interface, the RJ45 interface is used to communicate with the host computer and receive TCP protocol data sent by the host computer;

[0006] a data processing module configured to be in communication with the Ethernet transceiver, for parsing the data sent by the TCP protocol, extracting the number of at least one target test device and generating a control signal based on the number, and processing and encapsulating the data sent by the TCP protocol into UDP data;

[0007] A master PHY chip, communicatively connected to the data processing module;

[0008] a bus control module, communicatively connected to the data processing module, receiving the control signal, and receiving the UDP data through the master control PHY chip;

[0009] An Ethernet transceiver array, communicatively connected to the bus control module, comprising a plurality of slave PHY chips controlled by the bus control module, each slave PHY chip corresponding to an interface for communicating with the test equipment;

[0010] The bus control module turns on the slave control PHY chip corresponding to the number based on the control signal, and sends the UDP data to the target test device through the turned-on slave control PHY chip, triggering the target test device to return the information to the data processing module via the original route. The data processing module converts the returned information into TCP protocol return data and sends it to the host computer.

[0011] In summary, the embodiment of the present application provides a multi-test equipment collaborative control and data processing device, which performs protocol conversion on the TCP protocol sent by the host computer, encapsulates the TCP protocol sent data processing into UDP data, and turns on the slave control PHY chip corresponding to the target test equipment through a control signal, and sends the UDP data to the target test equipment through the turned-on slave control PHY chip. The target test equipment performs the test task based on the UDP data and returns the feedback information, converts the feedback information into TCP protocol feedback data and sends it to the host computer, thereby completing the test process. During the test process, the multi-test equipment collaborative control and data processing device can automatically complete data protocol conversion, target test equipment selection and data forwarding, and realize efficient collaborative control of multiple devices under test. The host computer only needs to send TCP protocol data and receive TCP protocol feedback data, without the need to perform protocol conversion on the data, which reduces the burden on the host computer.

[0012] Furthermore, the device further comprises:

[0013] A first storage unit is configured to be in communication with the data processing module and is used to store the data sent by the TCP protocol and the control response data in the returned information;

[0014] The second storage unit is configured to be in communication with the data processing module and is used to store the test result data in the returned information.

[0015] Furthermore, the first storage unit and the second storage unit are respectively communicatively connected to the data processing module via a JESD interface.

[0016] Furthermore, the master PHY chip is communicatively connected to the data processing module and the bus control module respectively through an SGMII interface.

[0017] Furthermore, the master PHY chip is configured to convert the UDP data into an SGMII electrical signal recognizable by the slave PHY chip.

[0018] Furthermore, the Ethernet transceiver is connected to the data processing module via an SGMII interface.

[0019] Furthermore, the Ethernet transceiver adopts a dual PHY chip redundancy design.

[0020] Furthermore, the data processing module adopts a master-slave dual controller architecture, and the backup controller is activated when the master controller fails.

[0021] Furthermore, the device further comprises:

[0022] A clock module uses a high-precision temperature-compensated crystal oscillator combined with a phase-locked loop frequency multiplication circuit to provide a unified clock signal for the data processing module, the master PHY chip, the bus control module, the Ethernet transceiver, and the Ethernet transceiver array.

[0023] Furthermore, the device further comprises:

[0024] Power management module, which is an adaptive power consumption control system with power status monitoring and dynamic power regulation functions;

[0025] The thermal management module is a layered heat dissipation structure composed of a heat pipe heat dissipation unit and a fan control unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram showing the connection between the processing device provided in one embodiment of the present application and the host computer and the device under test;

[0027] Figure 2 A schematic diagram of the structure of a processing device provided in one embodiment of the present application;

[0028] Figure 3 A processing device provided in one embodiment of the present application further includes a structural schematic diagram of a first storage unit and a second storage unit;

[0029] Figure 4 A processing device provided for an embodiment of the present application also includes a structural diagram of a clock module, a power management module and a thermal management module. DETAILED DESCRIPTION

[0030] The present application will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in this field based on these embodiments are included in the scope of protection of the present application.

[0031] In order to solve the deficiencies of the prior art, the present invention provides a multi-test equipment collaborative control and data processing device, such as Figure 1 As shown, one end of the processing device 100 is connected to the host computer for communication, and the other end is connected to multiple devices under test. Figure 2 As shown, the processing device 100 includes an Ethernet transceiver 11 , a data processing module 12 , a master PHY (Physical) chip 13 , a bus control module 14 and an Ethernet transceiver array 15 .

[0032] The Ethernet transceiver 11 includes an RJ45 (Registered Jack 45) interface, which is used to communicate with a host computer and receive TCP (Transmission Control Protocol) data sent by the host computer. The data processing module 12 is configured to communicate with the Ethernet transceiver 11, parse the TCP data, extract the number of at least one target test device and generate a control signal based on the number, and process and encapsulate the TCP data into UDP (User Datagram Protocol) data.

[0033] The master PHY chip 13 is communicatively connected to the data processing module 14; the bus control module 14 is communicatively connected to the data processing module 12 to receive control signals, and the bus control module 14 receives UDP data through the master PHY chip 13; the Ethernet transceiver array 15 is communicatively connected to the bus control module 14, and the Ethernet transceiver array 15 includes multiple slave PHY chips controlled by the bus control module 14, and any slave PHY chip corresponds to an interface for communicating with the test equipment.

[0034] Among them, the bus control module 14 turns on the slave control PHY chip corresponding to the number based on the control signal, and sends the UDP data to the target test device through the turned-on slave control PHY chip, triggering the target test device to return the information to the data processing module 12 via the original route. The data processing module 12 converts the returned information into TCP protocol return data and sends it to the host computer.

[0035] Specifically, the processing device 100 is connected to the host computer through the Ethernet transceiver 11. The Ethernet transceiver 11 includes an RJ45 interface. The Ethernet transceiver 11 is connected to the host computer through the RJ45 interface. In addition, the Ethernet transceiver 11 is also connected to the data processing module 12.

[0036] The data processing module 12 is in communication with the master PHY chip 13. Furthermore, the data processing module is in communication with the bus control module 14, which is in communication with the master PHY chip 13. Furthermore, the bus control module 14 is in communication with an Ethernet transceiver array 15, which includes multiple slave PHY chips. Each slave PHY chip is controlled by the bus control module 14, and each slave PHY chip has an interface for communicating with the test equipment.

[0037] After receiving the TCP data from the host computer, the Ethernet transceiver 11 sends the data to the data processing module 12. The data processing module 12 parses the data and encapsulates it as UDP data. Furthermore, the module extracts the number of at least one target test device and generates a control signal based on the target test device number. The module transmits the encapsulated UDP data to the master PHY chip 13 and outputs the generated control signal to the bus control module 14. The master PHY chip 13 receives the UDP data from the data processing module 12 and transmits the UDP data to the bus control module 14.

[0038] Based on the target test device's number in the control signal, bus control module 14 activates the corresponding slave PHY chip in Ethernet transceiver array 15, thereby establishing a communication channel between processing device 100 and the target test device. Bus control module 14 then transmits the received UDP data to the target test device via the activated slave PHY chip. In response to the UDP data, the target test device executes the test task and, upon completion, generates return information, which includes the target test device's control response data and test result data.

[0039] The target test device returns the feedback information to the data processing module 12 through the corresponding slave PHY chip. The data processing module 12 parses the feedback information, converts the feedback information into TCP protocol feedback data, and sends the TCP protocol feedback data to the host computer through the Ethernet transceiver 11 to complete the test process.

[0040] According to the above description, the embodiment of the present application provides a multi-test equipment collaborative control and data processing device, which performs protocol conversion on the TCP protocol sent by the host computer, encapsulates the TCP protocol sent data processing into UDP data, and turns on the slave control PHY chip corresponding to the target test equipment through a control signal, and sends the UDP data to the target test equipment through the turned-on slave control PHY chip. The target test equipment performs the test task based on the UDP data and returns the feedback information, converts the feedback information into TCP protocol feedback data and sends it to the host computer, thereby completing the test process. During the test process, the multi-test equipment collaborative control and data processing device can automatically complete data protocol conversion, target test equipment selection and data forwarding, and realize efficient collaborative control of multiple devices under test. The host computer only needs to send TCP protocol data and receive TCP protocol feedback data, without the need to perform protocol conversion on the data, which reduces the burden on the host computer.

[0041] As an optional implementation method, the Ethernet transceiver 11 adopts a dual PHY chip redundant design, in which the main PHY chip is responsible for normal communication, and the backup PHY chip automatically switches when the main PHY chip fails, ensuring the stable operation of the Ethernet transceiver 11 and ensuring that the communication between the host computer and the data processing module 12 is not interrupted.

[0042] As an optional implementation, data processing module 12 employs a dual-controller architecture with a primary and backup controller. In the event of a primary controller failure, the backup controller is activated. While the primary controller is operating normally, the backup controller is on standby. The backup controller uses an internal monitoring link to monitor the primary controller's operating status in real time. If the primary controller fails, the backup controller quickly takes over, maintaining communication continuity with all modules. This prevents data processing interruptions caused by a single controller failure and ensures the continuity of command parsing, data conversion, and information exchange during the coordinated control of multiple test devices.

[0043] As an optional implementation, the Ethernet transceiver 11 and the data processing module 12 are respectively provided with an SGMII (Serial Gigabit Media Independent Interface) interface. The Ethernet transceiver 11 and the data processing module 12 communicate through the SGMII interface. The SGMII interface is a high-speed serial interface that can effectively reduce the number of pins required for connection and reduce signal interference between lines while maintaining a high transmission rate to meet the real-time transmission requirements of gigabit data.

[0044] In actual operation, after receiving TCP data from the host computer, Ethernet transceiver 11 quickly and accurately transmits this data to data processing module 12 via the SGMII interface. After data processing module 12 converts the test equipment's return information into TCP data, it also transmits this data to Ethernet transceiver 11 via the SGMII interface. Ethernet transceiver 11 then transmits this data back to the host computer via the RJ45 interface. The high-speed transmission characteristics of the SGMII interface ensure rapid data flow between Ethernet transceiver 11 and data processing module 12, avoiding delays caused by data backlogs. Furthermore, the SGMII interface has strong anti-interference capabilities, ensuring the integrity of data transmission.

[0045] As an optional implementation, the master PHY chip 13 and the bus control module 14 are each equipped with an SGMII interface. The data processing module 12 communicates with the master PHY chip 13 via the SGMII interface, and the master PHY chip 13 communicates with the bus control module 14 via the SGMII interface. After processing and encapsulating TCP data into UDP data, the data processing module 12 transmits the UDP data to the master PHY chip 13 via the SGMII interface. The master PHY chip 13 then forwards the UDP data to the bus control module 14 via another SGMII interface. The SGMII interface offers high-speed transmission, enabling rapid transfer of UDP data between the data processing module 12, the master PHY chip 13, and the bus control module 14, ensuring low latency in data transmission.

[0046] Further, as an optional implementation, the master PHY chip 13 is configured to convert UDP data into SGMII electrical signals recognizable by the slave PHY chip.

[0047] Specifically, after the data processing module 12 encapsulates the TCP protocol data sent by the host computer into UDP data, the master PHY chip 13 processes the UDP data and converts it into an SGMII electrical signal that can be recognized by the slave PHY chip. The SGMII electrical signal can meet the point-to-point MAC (Media Access Control Layer) communication requirements of the slave PHY chip in the Ethernet transceiver array 15.

[0048] The master PHY chip 13 transmits the SGMII electrical signal to the bus control module 14. Based on the control signal, the bus control module 14 enables the corresponding slave PHY chip. The SGMII electrical signal is then transmitted to the target slave PHY chip via the selected path. The master PHY chip 13 converts and processes the UDP data, enabling data connectivity between the data processing module 12 and the bus control module 14. This meets the signal reception requirements of the slave PHY chips and enables precise data transmission and control of multiple test devices.

[0049] As an optional implementation, such as Figure 3 As shown, the processing device 100 also includes a first storage unit 16 and a second storage unit 17. The first storage unit 16 and the second storage unit 17 are respectively configured to communicate with the data processing module 12. The first storage unit 16 is used to store the TCP protocol sent data and the control response data in the return information, and the second storage unit 17 is used to store the test result data in the return information.

[0050] Specifically, the first storage unit 16 is in communication with the data processing module 12 in the device 100. The data processing module 12 transmits received TCP protocol data to the first storage unit 16 for storage. The data processing module 12 can also read stored data from the first storage unit 16. The first storage unit 16 stores the TCP protocol data sent by the host computer and backs up the original TCP protocol data to prevent data loss due to accidents during the data processing process (such as temporary power outages, data transmission errors, etc.).

[0051] In one embodiment, the first storage unit 16 can be configured as a high-frequency storage unit. When the return information from the target test device is transmitted to the data processing module 12, the data processing module 12 judges the return information and stores the control response data in the return information in the first storage unit 16. The control response data is shorter than the test result data, and storing the control response data in the first storage unit 16 facilitates fast writing and reading of the control response data.

[0052] In one embodiment, the second storage unit 17 can be configured as a large-capacity storage unit. The data processing module 12 judges the returned information and stores the test result data in the returned information in the second storage unit 17. The test result data is larger than the control response data. Storing the test result data in the second storage unit 17 helps ensure the integrity of the test result data.

[0053] By storing the control response data and the test result data in the first storage unit 16 and the second storage unit 17 respectively, the efficiency of the processing device 100 in processing data can be improved, especially during high-frequency testing, which ensures the reliability of the processing device 100. In addition, it can also avoid problems such as transmission interruptions that lead to data errors, so as to facilitate subsequent tracing and analysis of the test process.

[0054] Furthermore, as an optional implementation, JESD (JEDEC Serial Data) interfaces are provided on first storage unit 16, second storage unit 17, and data processing module 12. First storage unit 16 communicates with data processing module 12 via the JESD interface, and second storage unit 17 communicates with data processing module 12 via the JESD interface. The JESD interface has high data transmission rates and strong anti-interference capabilities. After receiving data sent via the TCP protocol from the host computer, data processing module 12 can quickly and stably transfer the data to first storage unit 16 for storage via the JESD interface, thereby improving data storage efficiency.

[0055] As an optional implementation, such as Figure 4 As shown, the processing device 100 also includes a clock module 18. The clock module 18 uses a high-precision temperature-compensated crystal oscillator combined with a phase-locked loop frequency multiplication circuit to provide a unified clock signal for the Ethernet transceiver 11, the data processing module 12, the master PHY chip 13, the bus control module 14 and the Ethernet transceiver array 15.

[0056] Specifically, the clock module 18 establishes a signal transmission channel with the Ethernet transceiver 11, the master PHY chip 13, the bus control module 14, and the Ethernet transceiver array 15 through the data processing module 12. The clock module 18 uses a high-precision temperature-compensated crystal oscillator combined with a phase-locked loop frequency multiplication circuit. The high-precision temperature-compensated crystal oscillator has temperature stability and can maintain the stability of the output frequency under different ambient temperature conditions, thereby avoiding clock signal drift due to temperature changes. The phase-locked loop frequency multiplication circuit is responsible for processing the basic frequency output by the temperature-compensated crystal oscillator to meet the clock signal frequency requirements of various components. It should be noted that the clock module 18 can rely on the internal crystal oscillator of the processing device 100 to operate, or it can be operated through an external crystal oscillator.

[0057] The clock module 18 outputs the generated clock signal to each component that establishes a signal transmission channel with it. The stable and synchronized clock signal provided by the clock module 18 ensures the timing synchronization between the various components, reduces data errors, transmission delays or control failures caused by timing deviations, and thus improves the reliability and efficiency of the processing device 100.

[0058] As an optional implementation, such as Figure 4 As shown, the processing device 100 further includes a power management module 19 and a thermal management module 21. The power management module 19 is an adaptive power consumption control system with power state detection and dynamic power adjustment functions; the thermal management module 21 is a layered heat dissipation structure consisting of a heat pipe heat dissipation unit and a fan control unit.

[0059] Specifically, the power management module 19 establishes connections with the Ethernet transceiver 11, the master PHY chip 13, the bus control module 14, and the Ethernet transceiver array 15 through the data processing module 12. The power management module 19 monitors the current, voltage, and other power parameters of each module, as well as the overall power consumption level, through these connections. This allows the power management module 19 to detect the power status of the processing device 100 and promptly identify any power supply anomalies, such as voltage instability and current overload.

[0060] Furthermore, the power management module 19 is connected to a DC power supply and can optimize power allocation based on the real-time workload of each module within the processing device 100. For example, when the data processing module 12 is operating at high load (e.g., parsing a large amount of TCP protocol data or converting and transmitting information), the power management module 19 increases the power supply to the data processing module 12 to ensure that the computing capacity of the data processing module 12 is not restricted. When some modules are idle, the power management module 19 can reduce the power supplied to these modules, thereby achieving efficient energy utilization and avoiding unnecessary power consumption.

[0061] The processing device 100 also includes a thermal management module 21, which includes a heat pipe cooling unit and a fan control unit. The heat pipe cooling unit is in physical contact with heat-generating components such as the data processing module 12, the main control PHY chip 13, and the bus control module 14. The heat pipe cooling unit can quickly transfer the heat generated by the above modules from the heat source to areas such as the heat sink, thereby expanding the range of heat dissipation and accelerating the speed of heat diffusion.

[0062] The fan control unit includes a cooling fan, which regulates its operation based on the temperature within processing device 100. When the temperature is below a set threshold, the fan control unit controls the cooling fan to operate at a low speed or stop. When the temperature exceeds the set threshold, the fan control unit increases the cooling fan speed, accelerating air flow around the heat sink and enhancing heat dissipation through convection, ensuring that the temperature of each module remains within a safe range. Furthermore, when processing device 100 is simultaneously testing multiple test devices, the fan control unit increases the fan speed to improve heat dissipation efficiency and ensure the continued stable operation of processing device 100.

[0063] According to the above description, the embodiment of the present application provides a multi-test equipment collaborative control and data processing device, which performs protocol conversion on the TCP protocol sent by the host computer, encapsulates the TCP protocol sent data processing into UDP data, and turns on the slave control PHY chip corresponding to the target test equipment through a control signal, and sends the UDP data to the target test equipment through the turned-on slave control PHY chip. The target test equipment performs the test task based on the UDP data and returns the feedback information, converts the feedback information into TCP protocol feedback data and sends it to the host computer, thereby completing the test process. During the test process, the multi-test equipment collaborative control and data processing device can automatically complete data protocol conversion, target test equipment selection and data forwarding, and realize efficient collaborative control of multiple devices under test. The host computer only needs to send TCP protocol data and receive TCP protocol feedback data, without the need to perform protocol conversion on the data, which reduces the burden on the host computer.

[0064] It will be understood that the word "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily preferred or advantageous over other embodiments and / or does not exclude the ability to combine features of other embodiments. It will be understood that certain features of the present application, which are described in the context of separate embodiments for the sake of clarity, may also be provided in combination in a single embodiment. Conversely, various features of the present application, which are described in the context of a single embodiment for the sake of clarity, may also be provided separately or in any suitable combination or as any other described embodiment of the present application.

[0065] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. Words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0066] The above disclosure is only a preferred embodiment of the present application, but it is not intended to limit the scope of rights of the present application. Ordinary technicians in this field can understand that without departing from the spirit and scope of the present application and the appended claims, changes, modifications, substitutions, combinations, and simplifications should all be equivalent replacement methods and still fall within the scope covered by the present application.

Claims

1. A multi-test equipment collaborative control and data processing device, characterized in that: The device comprises: Ethernet transceiver, including an RJ45 interface, the RJ45 interface is used to communicate with the host computer and receive TCP protocol data sent by the host computer; a data processing module configured to be in communication with the Ethernet transceiver, for parsing the data sent by the TCP protocol, extracting the number of at least one target test device and generating a control signal based on the number, and processing and encapsulating the data sent by the TCP protocol into UDP data; A master PHY chip, communicatively connected to the data processing module; a bus control module, communicatively connected to the data processing module, receiving the control signal, and receiving the UDP data through the master control PHY chip; An Ethernet transceiver array, communicatively connected to the bus control module, comprising a plurality of slave PHY chips controlled by the bus control module, each slave PHY chip corresponding to an interface for communicating with the test equipment; The bus control module turns on the slave control PHY chip corresponding to the number based on the control signal, and sends the UDP data to the target test device through the turned-on slave control PHY chip, triggering the target test device to return the information to the data processing module via the original route. The data processing module converts the returned information into TCP protocol return data and sends it to the host computer.

2. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The device further comprises: A first storage unit is configured to be in communication with the data processing module and is used to store the data sent by the TCP protocol and the control response data in the returned information; The second storage unit is configured to be in communication with the data processing module and is used to store the test result data in the returned information.

3. The multi-test equipment collaborative control and data processing device according to claim 2, characterized in that: The first storage unit and the second storage unit are respectively connected to the data processing module for communication via a JESD interface.

4. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The master PHY chip is communicatively connected to the data processing module and the bus control module respectively through an SGMII interface.

5. The multi-test equipment collaborative control and data processing device according to claim 4, characterized in that: The master PHY chip is configured to convert the UDP data into an SGMII electrical signal recognizable by the slave PHY chip.

6. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The Ethernet transceiver is connected to the data processing module via an SGMII interface.

7. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The Ethernet transceiver adopts a dual PHY chip redundancy design.

8. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The data processing module adopts a master-slave dual controller architecture, and the backup controller is activated when the master controller fails.

9. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The device further comprises: A clock module uses a high-precision temperature-compensated crystal oscillator combined with a phase-locked loop frequency multiplication circuit to provide a unified clock signal for the data processing module, the master PHY chip, the bus control module, the Ethernet transceiver, and the Ethernet transceiver array.

10. The multi-test equipment collaborative control and data processing device according to claim 1, characterized in that: The device further comprises: Power management module, which is an adaptive power consumption control system with power status monitoring and dynamic power regulation functions; The thermal management module is a layered heat dissipation structure composed of a heat pipe heat dissipation unit and a fan control unit.

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