Injection structure and silicon carbide gate-controlled device structure
By adding a P-doped region and a split-gate structure to the power MOSFET device and optimizing the injection structure, the problems of channel density, on-resistance and switching loss in the existing technology are solved, and more efficient power MOSFET performance is achieved.
Patent Information
- Application Number
- CN202422536196.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-21
AI Technical Summary
While increasing the channel density, existing power MOSFET devices are difficult to effectively reduce on-resistance, switching loss and gate oxide electric field strength, and there are problems of increased reverse transfer capacitance and blocking leakage current.
By adding P-doped regions and split-gate structures to the cellular structure and optimizing the injection structure, a new cellular form is formed. Combined with a rectangular or regular hexagonal array arrangement, the gate oxide electric field strength and reverse transfer capacitance are reduced. At the same time, a gap is opened at the gate contact to form a split-gate structure, thereby reducing switching losses.
This improves the channel density while reducing on-resistance and switching loss, reducing gate oxide electric field strength and blocking leakage current, and optimizing the performance of power MOSFET.
Smart Images
Figure CN223415192U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to an injection structure and a silicon carbide gate-controlled device structure. Background Art
[0002] Forward resistance, blocking voltage, and switching losses are crucial performance parameters for power gate-controlled devices. Improving the performance of power MOSFETs requires reducing the device's on-resistance and switching losses while ensuring a high blocking voltage. Channel resistance accounts for a large proportion of the power MOSFET's on-resistance, and increasing channel density is an important approach to reducing channel resistance. Compared to strip-shaped cells, traditional square, polygonal, and circular cells can effectively increase channel density. However, the presence of large areas in the JFET region increases the device's reverse transfer capacitance, blocking leakage current, and gate oxide electric field strength, thereby increasing device switching losses and reducing device blocking voltage. Therefore, it is necessary to optimize the structure based on the original square, polygonal, and other cell structures to increase channel density while reducing device switching losses, blocking leakage current, and gate oxide electric field strength. Utility Model Content
[0003] The utility model addresses the problems existing in the prior art and provides an injection structure and a silicon carbide gate-controlled device structure that improves the channel density while reducing the gate oxide electric field strength and the blocking leakage current of the silicon carbide device by changing and increasing the injection structure and increasing the injection area at the same time. At the same time, it combines the split gate structure to reduce the reverse transfer capacitance of square and polygonal cells, and reduces the switching loss of the device.
[0004] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: an injection structure, comprising a plurality of cells arranged in an array, and at least one P-doped region; adjacent cells are provided with gaps, and the P-doped region is located at the intersection of the gaps;
[0005] The cell includes a pbase doping region, an N+ doping region and a P+ doping region;
[0006] A groove is formed on one end surface of the pbase doping region, the p+ doping region is located at the center of the groove, and one end surface of the p+ doping region is in contact with the bottom surface of the groove; the n+ doping region is located in the groove, one end surface of the n+ doping region is in contact with the bottom surface of the groove, and the n+ doping region is located between the side surface of the p+ doping region and the sidewall of the groove;
[0007] The injection structure is located in the JFET region, one end surface of the JFET region is connected to the epitaxial region, and the other end surface of the JFET region is connected to the gate dielectric region; the gate dielectric region is provided with a plurality of first notches, each of the first notches corresponding to the cells one by one, a source contact is provided in each of the first notches, and the source contact blocks the corresponding first notch; the surface of the gate dielectric region is covered with a gate contact, the gate contact is provided with at least one second notch, the second notch corresponding to the P-doped region; the gate contact is provided with a plurality of third notches, each of the third notches corresponding to the first notches one by one;
[0008] The other end surface of the P+ doped region is in contact with the corresponding source contact, and the edge of the source contact extends outward to partially cover the other end surface of the N+ doped region;
[0009] The end surface of the pbase doped region where the groove is formed is in contact with the gate dielectric region, and the other end surface of the pbase doped region is in contact with the epitaxial region;
[0010] One end surface of the P-doped region is connected to the gate dielectric region.
[0011] Furthermore, the cross section of the cell is square, circular or polygonal.
[0012] Furthermore, the plurality of cells are arranged in a rectangular array, and the P-doped regions are provided at the intersections between four adjacent cells.
[0013] Furthermore, the cross section of the cell is a regular hexagon.
[0014] Furthermore, the plurality of cells are arranged in a triangular array, and the P-doped regions are provided at the intersections between three adjacent cells.
[0015] Furthermore, the cross section of the P-doped region is circular.
[0016] Furthermore, the orthographic projection of the P-doped region on the gate dielectric region is a first projection, the orthographic projection of the second notch on the gate dielectric region is a second projection, and the first projection is within the range of the second projection.
[0017] Furthermore, the edge of the second projection extends beyond the edge of the first projection by 0-1 μm.
[0018] A silicon carbide gate-controlled device structure comprises the injection structure.
[0019] Furthermore, it also includes a drain contact, a substrate region, an epitaxial region, a JFET region, a gate dielectric region, a gate contact and a plurality of source contacts;
[0020] The substrate region, the epitaxial region, the JFET region and the gate dielectric region are sequentially stacked; the drain contact is laid on the surface of the substrate region.
[0021] Compared with the prior art, the present invention has the following beneficial effects:
[0022] The utility model changes and adds an injection structure to form a new cell on the basis of a conventional square or polygonal cell, and adds a P-doped region at the interval between the cells to form an injection region, which can reduce the gate oxide electric field strength and the blocking leakage current of the silicon carbide device while increasing the channel density. At the same time, a second gap and a third gap are opened on the gate contact to form a split gate structure, which reduces the reverse transfer capacitance of the square and polygonal cells and reduces the switching loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a schematic cross-sectional view of the downwardly inclined injection structure in Example 1 of the present invention.
[0024] Figure 2 This is a schematic top view of the injection structure in Example 1 of the present invention.
[0025] Figure 3 This is a front view of the surface where the gate contact of the silicon carbide gate-controlled device structure is located in Example 1 of the present invention.
[0026] Figure 4 for Figure 3 Schematic diagram of the cross section at AA in FIG.
[0027] Figure 5 for Figure 3 Schematic diagram of the cross section at BB in FIG.
[0028] Figure 6 This is a downward-inclined cross-sectional view of the injection structure in Example 2 of the present invention.
[0029] Figure 7 This is a schematic top view of the injection structure in Example 2 of the present invention.
[0030] Figure 8 This is a front view of the gate contact surface of the silicon carbide gate-controlled device structure in Example 2 of the present utility model.
[0031] Figure 9 It is a schematic longitudinal section diagram of the injection structure in Example 2 of the present utility model.
[0032] Among them, the figure markings are: 1. pbase doped region; 2. N+ doped region; 3. P+ doped region; 4. P doped region; 5. epitaxial region; 6. substrate region; 7. source contact; 8. gate contact; 9. drain contact; 10. gate dielectric region; 11. JFET region. DETAILED DESCRIPTION
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0034] It is worth noting that the methods used in the present invention are all conventional methods unless otherwise specified; the raw materials and devices used are all conventional commercially available products, and their sources are not specifically limited unless otherwise specified.
[0035] Example 1
[0036] See also Figure 1-5 , an injection structure, including a plurality of cells arranged in a rectangular array, and at least one P-doped region 4; there are gaps between adjacent cells, and the P-doped region 4 is located at the intersection of the gaps; the P-doped region 4 is set at the intersection of the gaps between four adjacent cells arranged in a rectangular array, and the cross-section of the P-doped region 4 is circular.
[0037] The cell includes a pbase doping region 1, an N+ doping region 2, and a P+ doping region 3; the cross section of the cell is square;
[0038] The doping element of the pbase doping region 1 is Al or B, and the doping concentration range is 1×10 15 cm -3 to 1×10 20 cm -3 between;
[0039] The doping element of the P+ doping region 3 is Al or B, and the doping concentration range is 1×10 18 cm -3 to 1×10 22 cm -3 between;
[0040] The doping element of the N+ doping region 2 is N or P, and the doping concentration range is 1×10 18 cm -3 to 1×10 22 cm -3 between;
[0041] The doping element of the P-doped region 4 is Al or B, and the doping concentration range is 1×10 15 cm -3 to 1×10 21 cm -3 between;
[0042] A groove is formed on one end surface of the pbase doping region 1, and the p+ doping region 3 is located at the center of the groove, and one end surface of the p+ doping region 3 is in contact with the bottom surface of the groove; the n+ doping region 2 is located in the groove, and one end surface of the n+ doping region 2 is in contact with the bottom surface of the groove, and the n+ doping region 2 is located between the side surface of the p+ doping region 3 and the sidewall of the groove;
[0043] The implantation structure is located in the JFET region 11; the doping element of the JFET region 11 is N or P, and the doping concentration range is 1×10 15 cm -3 to 1×10 18 cm -3 between;
[0044] One end surface of the JFET region 11 is connected to the epitaxial region 5, and the other end surface of the JFET region 11 is connected to the gate dielectric region 10; the epitaxial region 5 is made of a wide bandgap semiconductor, such as silicon carbide, and the gate dielectric 10 is an insulating dielectric, which is at least one of silicon oxide, silicon nitride, or other metal oxides;
[0045] The gate dielectric region 10 is provided with a plurality of first notches, each of which corresponds to a cell. A source contact 7 is provided in each first notch, and the source contact 7 blocks the corresponding first notch. The source contact 7 is made of a conductive medium such as metal or doped polysilicon.
[0046] The surface of the gate dielectric region 10 is covered with a gate contact 8. The gate contact 8 is made of a metal, a conductive medium doped with polysilicon, or a composite of a metal and a conductive medium doped with polysilicon. The gate contact 8 has at least one second notch corresponding to the P-doped region 4. The gate contact 8 has a plurality of third notches corresponding to the first notches.
[0047] The other end surface of the P+ doped region 3 is in contact with the corresponding source contact 7, and the edge of the source contact 7 extends outward to partially cover the other end surface of the N+ doped region 2, that is, the source contact 7 is in contact with the P+ doped region 3 and part of the N+ doped region 2 respectively;
[0048] The end surface of the pbase doped region 1 where the groove is formed is in contact with the gate dielectric region 10 , and the other end surface of the pbase doped region 1 is in contact with the epitaxial region 5 ;
[0049] One end surface of the P-doped region 4 is in contact with the gate dielectric region 10;
[0050] On the basis of conventional square or polygonal cells, the injection structure is changed and added to form new cells, and P-doped regions 4 are added at the intervals between the cells to form injection regions. This can increase the channel density while reducing the gate oxide electric field strength and the blocking leakage current of the silicon carbide device. At the same time, a second gap and a third gap are opened on the gate contact 8 to form a split gate structure, thereby reducing the reverse transfer capacitance of the square and polygonal cells and reducing the switching loss of the device.
[0051] The orthographic projection of the P-doped region 4 on the gate dielectric region 10 is a first projection, and the orthographic projection of the second notch on the gate dielectric region 10 is a second projection. The first projection is within the range of the second projection.
[0052] The edge of the second projection extends beyond the edge of the first projection by 0-1 μm.
[0053] That is, in addition to covering the end face corresponding to the JFET region 11, the gate dielectric region 10 also covers the pbase doped region 1 and part of the N+ doped region 2. The gate dielectric region 10 is connected to the source contact 7 at the N+ doped region 2. In addition, the surface of the P-doped region 4 is also covered by the gate dielectric region 10, and the gate contact 8 covering the surface of the gate dielectric region 10 has a second gap opened at the P-doped region 4.
[0054] The orthographic projection of the third notch on the gate dielectric region 10 is the third projection. The first notch is within the range of the corresponding third projection. The cross-sectional shape and size of the source contact 7 match the cross-sectional shape and size of the first notch, which can ensure that the source contact 7 and the gate contact 8 are not connected to each other.
[0055] This embodiment also provides a silicon carbide gate-controlled device structure, including an implantation structure, a drain contact 9, a substrate region 6, an epitaxial region 5, a JFET region 11, a gate dielectric region 10, a gate contact 8, and a plurality of source contacts 7;
[0056] The substrate region 6, the epitaxial region 5, the JFET region 11 and the gate dielectric region 10 are sequentially stacked; the drain contact 9 is laid on the surface of the substrate region 6;
[0057] In addition, the source contact 7 can serve as a source or emitter, and the drain contact 9 can serve as a drain or collector;
[0058] The material of the substrate region 6 and the material of the epitaxial region 5 are respectively wide bandgap semiconductors, such as silicon carbide;
[0059] The doping type of the epitaxial region 5 is n-type doping or p-type doping; the doping element of the n-type doping is at least one of the Group V elements in the semiconductor, such as phosphorus or nitrogen; the doping element of the p-type doping is at least one of the Group III elements in the semiconductor, such as aluminum or boron.
[0060] The doping type of the substrate region 6 is n-type doping or p-type doping; the doping element of the n-type doping is at least one of the Group V elements in the semiconductor, such as phosphorus or nitrogen; the doping element of the p-type doping is at least one of the Group III elements in the semiconductor, such as aluminum or boron.
[0061] Furthermore, the JFET region 11 includes a JFET region n-type doped region and a JFET region p-type doped region; the JFET region p-type doped region is square, circular, polygonal or irregular in shape; the JFET region p-type doped region is located between the JFET region n-type doped regions, or the JFET region p-type doped region is located at the edge of the JFET region n-type doped region;
[0062] In addition, the distribution and shape of the n-type doped region of the JFET region and the p-type doped region of the JFET region in the JFET region 11 are not limited. The number of the p-type doped region of the JFET region can be one or more, and the multiple p-type doped regions of the JFET region are irregularly distributed within the n-type doped region of the JFET region. The shape of the n-type doped region of the JFET region and the shape of the p-type doped region of the JFET region can be either regular or irregular.
[0063] The gate contact 8 may be in a disconnected state at the p-type doped region of the JFET region, and the disconnected area is close to the area of the p-type doped region of the JFET region. The disconnected area may be slightly larger than the area of the p-type doped region of the JFET region, or slightly smaller than the area of the p-type doped region of the JFET region. The area of the p-type doped region of the JFET region is the area where the p-type doped region of the JFET region contacts the gate dielectric region 10.
[0064] The doping element of the n-type doping region of the JFET region is at least one of the Group V elements in the semiconductor, such as phosphorus or nitrogen, and the doping concentration range is 1×10 14 cm -3 to 1×10 19 cm -3 between;
[0065] The doping element of the p-type doping region of the JFET region is at least one of the III group elements in the semiconductor, such as aluminum or boron, and the doping concentration range is 1×10 14 cm -3 to 1×10 19 cm -3 between;
[0066] The drain contact 9 is made of a conductive medium such as metal or doped polysilicon.
[0067] The silicon carbide gate-controlled device structure includes a silicon carbide MOSFET or a silicon carbide IGBT.
[0068] Example 2
[0069] See also Figure 6-9 Based on Example 1, the rest is the same as Example 1. The difference from Example 1 is that the cross section of the cell is a regular hexagon, and several cells are arranged in a triangular array, and a P-doped region 4 is provided at the intersection of the intervals between three adjacent cells.
[0070] Finally, it should be noted that the above content is only used to illustrate the technical solution of the utility model, rather than to limit the scope of protection of the utility model. Simple modifications or equivalent replacements of the technical solution of the utility model by ordinary technicians in this field do not deviate from the essence and scope of the technical solution of the utility model.
Claims
1. An injection structure, characterized in that: The device comprises a plurality of cells arranged in an array, and at least one P-doped region; spaces are provided between adjacent cells, and the P-doped region is located at the intersection of the spaces; The cell includes a pbase doping region, an N+ doping region and a P+ doping region; A groove is formed on one end surface of the pbase doping region, the p+ doping region is located at the center of the groove, and one end surface of the p+ doping region is in contact with the bottom surface of the groove; the n+ doping region is located in the groove, one end surface of the n+ doping region is in contact with the bottom surface of the groove, and the n+ doping region is located between the side surface of the p+ doping region and the sidewall of the groove; The injection structure is located in the JFET region, one end surface of the JFET region is connected to the epitaxial region, and the other end surface of the JFET region is connected to the gate dielectric region; the gate dielectric region is provided with a plurality of first notches, each of the first notches corresponding to the cells one by one, a source contact is provided in each of the first notches, and the source contact blocks the corresponding first notch; the surface of the gate dielectric region is covered with a gate contact, the gate contact is provided with at least one second notch, the second notch corresponding to the P-doped region; the gate contact is provided with a plurality of third notches, each of the third notches corresponding to the first notches one by one; The other end surface of the P+ doped region is in contact with the corresponding source contact, and the edge of the source contact extends outward to partially cover the other end surface of the N+ doped region; The end surface of the pbase doped region where the groove is formed is in contact with the gate dielectric region, and the other end surface of the pbase doped region is in contact with the epitaxial region; One end surface of the P-doped region is connected to the gate dielectric region.
2. The injection structure according to claim 1, characterized in that: The cross section of the cell is square, circular or polygonal.
3. The injection structure according to claim 2, characterized in that: The plurality of cells are arranged in a rectangular array, and the P-doped regions are arranged at the intersections between four adjacent cells.
4. The injection structure according to claim 1, characterized in that: The cross section of the cell is a regular hexagon.
5. The injection structure according to claim 4, characterized in that: The plurality of cells are arranged in a triangular array, and the P-doped regions are arranged at the intersections between three adjacent cells.
6. The injection structure according to any one of claims 2 to 4, characterized in that: The cross section of the P-doped region is circular.
7. The injection structure according to claim 6, characterized in that: The orthographic projection of the P-doped region on the gate dielectric region is a first projection, the orthographic projection of the second notch on the gate dielectric region is a second projection, and the first projection is within the range of the second projection.
8. The injection structure according to claim 7, characterized in that: The edge of the second projection extends beyond the edge of the first projection by 0-1 μm.
9. A silicon carbide gate-controlled device structure, characterized in that: The invention comprises the injection structure according to any one of claims 1 to 8.
10. The silicon carbide gate-controlled device structure according to claim 9, characterized in that: Also comprising a drain contact, a substrate region, the epitaxial region, the JFET region, the gate dielectric region, the gate contact and a plurality of the source contacts; The substrate region, the epitaxial region, the JFET region and the gate dielectric region are sequentially stacked; the drain contact is laid on the surface of the substrate region.