Heterojunction cell structure and photovoltaic module
By using a stacked structure of VTTO layer, SnOx layer and ITO layer in the heterojunction battery structure, the problems of high production cost and high contact resistance are solved, and the effect of reducing contact resistance and production cost is achieved.
Patent Information
- Application Number
- CN202422640112.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-30
AI Technical Summary
The existing heterojunction battery structure has high production costs and large contact resistance.
The second passivation layer is formed by stacking VTTO layer, SnOx layer and ITO layer in sequence. The ITO layer serves as the contact surface and contains a large amount of indium to ensure good contact. The VTTO layer and SnOx layer use indium-free materials to reduce contact resistance.
The contact resistance of the passivation layer is reduced, the indium content is reduced, and the production cost is reduced while ensuring the battery efficiency.
Smart Images
Figure CN223415216U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of solar cells, in particular to a heterojunction cell structure and a photovoltaic module. Background Art
[0002] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0003] The heterojunction battery structure in the prior art has technical problems of high production cost and large contact resistance. Utility Model Content
[0004] The utility model provides a heterojunction battery structure and a photovoltaic component, which can reduce the contact resistance of the passivation layer while ensuring the battery efficiency.
[0005] The embodiment of the present utility model can be implemented as follows:
[0006] An embodiment of the present invention provides a heterojunction battery structure, comprising a first passivation layer, a first doped layer, a silicon wafer, a second doped layer, and a second passivation layer, wherein the first passivation layer and the first doped layer are arranged on the front side of the silicon wafer, and the second passivation layer and the second doped layer are arranged on the back side of the silicon wafer;
[0007] Wherein, the second passivation layer includes VTTO layer, SnO x layer and ITO layer, the VTTO layer, the SnO x The layer and the ITO layer are sequentially arranged on the back side of the second doping layer.
[0008] Optionally, the SnO x The refractive index of the layer is 1.8-2.15.
[0009] Optionally, the SnO x The refractive index of the layer is not higher than the refractive index of the VTTO layer.
[0010] Optionally, the SnO x The thickness of the layer is 1.5 to 3.5 times the thickness of the VTTO layer.
[0011] Optionally, the thickness of the VTTO layer is 15 nm-45 nm.
[0012] Optionally, the refractive index of the ITO layer is not higher than that of the SnO x The refractive index of the layer.
[0013] Optionally, the refractive index of the ITO layer is 1.75-2.1.
[0014] Optionally, the thickness of the ITO layer is 10 nm-35 nm.
[0015] Optionally, the thickness of the first passivation layer is 60 nm-160 nm.
[0016] An embodiment of the present invention further provides a photovoltaic assembly, comprising a cell string, wherein the cell string comprises at least two heterojunction cell structures.
[0017] The beneficial effects of the heterojunction cell structure and photovoltaic module of the embodiments of the present invention include, for example:
[0018] The heterojunction battery structure includes a first passivation layer, a first doping layer, a silicon wafer, a second doping layer and a second passivation layer, wherein the first passivation layer and the first doping layer are arranged on the front side of the silicon wafer, and the second passivation layer and the second doping layer are arranged on the back side of the silicon wafer; wherein the second passivation layer includes a VTTO layer, a SnO x layer and ITO layer, the VTTO layer, the SnO x The VTTO layer, SnO layer and the ITO layer are sequentially arranged on the back of the second doping layer. x Layer and ITO layer, because the ITO layer contains a large amount of indium, the ITO layer is used as the contact surface of the second passivation layer to ensure good contact, and SnO is stacked on the ITO layer. x The VTTO layer and the AZCO layer can reduce the indium content of the passivation layer, thereby reducing the contact resistance of the second passivation layer body. Moreover, the VTTO layer, the AZCO layer, and the AZO layer all use indium-free materials, which reduces the contact resistance of the passivation layer body while ensuring battery efficiency.
[0019] The photovoltaic module includes a battery string, and the battery string includes at least two heterojunction battery structures. When in use, a VTTO layer, a SnO layer and a PVD layer are sequentially arranged on the back of the second doping layer. x Layer and ITO layer, because the ITO layer contains a large amount of indium, the ITO layer is used as the contact surface of the second passivation layer to ensure good contact, and SnO is stacked on the ITO layer. x The VTTO layer and the AZCO layer can reduce the indium content of the passivation layer, thereby reducing the contact resistance of the second passivation layer body. Moreover, the VTTO layer, the AZCO layer, and the AZO layer all use indium-free materials, which reduces the contact resistance of the passivation layer body while ensuring battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 This is a schematic diagram of the structure of the heterojunction battery provided in this embodiment.
[0022] Icons: 10-first passivation layer; 20-first doping layer; 30-silicon wafer; 40-second doping layer; 50-VTTO layer; 60-SnO x Layer; 70-ITO layer. DETAILED DESCRIPTION
[0023] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.
[0025] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0026] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the utility model product is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.
[0027] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.
[0028] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention can be combined with each other.
[0029] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0030] The heterojunction battery structure in the related art has technical problems of high production cost and large contact resistance.
[0031] Please refer to Figure 1 This embodiment provides a photovoltaic module comprising a cell string comprising at least two heterojunction cell structures. This photovoltaic module can effectively address the aforementioned technical issues, reducing the contact resistance of the passivation layer while maintaining cell efficiency.
[0032] Please refer to Figure 1 This embodiment provides a heterojunction battery structure including a first passivation layer 10, a first doping layer 20, a silicon wafer 30, a second doping layer 40 and a second passivation layer. The first passivation layer 10 and the first doping layer 20 are arranged on the front side of the silicon wafer 30, and the second passivation layer and the second doping layer 40 are arranged on the back side of the silicon wafer 30; wherein, the second passivation layer includes a VTTO layer 50, a SnOx layer 60 and an ITO layer 70, and the VTTO layer 50, the SnOx layer 60 and the ITO layer 70 are arranged in sequence on the back side of the second doping layer 40.
[0033] Currently, the existing heterojunction cell technology is an N-type bifacial cell. Its simple and efficient process, energy-saving low-temperature operation, and naturally high bifaciality suitable for thin-film production are among its many advantages, making it a hot topic in the photovoltaic field. Tin-doped indium oxide (ITO) is the most widely used transparent conductive film in the photovoltaic industry. This film contains over 90% indium. However, due to its high cost, the development of new low-indium transparent conductive films is an urgent challenge for heterojunction solar cells. When the heterojunction battery structure provided in this embodiment is used, the VTTO layer 50, the SnOx layer 60 and the ITO layer 70 are stacked together to form a second passivation layer. The ITO layer 70 serves as the contact surface of the second passivation layer and has a large indium content, which can ensure good contact resistance. The VTTO layer 50 and the SnOx layer 60 serve as the main structure of the second passivation layer and both use indium-free materials, which can reduce the indium content of the second passivation layer. The ITO layer 70 cooperates with the VTTO layer 50 and the SnOx layer 60 to ensure good photoelectric performance while ensuring good contact resistance, thereby ensuring battery efficiency and reducing production costs.
[0034] Specifically, the VTTO layer 50 , the SnOx layer 60 , and the ITO layer 70 are sequentially stacked on the back side of the second doping layer 40 from top to bottom.
[0035] Specifically, the VTTO layer 50 is a thin film made of vertical target tin oxide using PVD technology. During the sputtering process, VTTO forms a tin oxide target material in a vertical direction, exhibiting excellent conductivity and optical properties. The target material has a purity of at least 99.99% and a density of at least 99%. Its composition is In2O3:SnO2 in a ratio of 95% to 99.5% by weight, preferably 99% by weight.
[0036] In this embodiment, the thickness of the VTTO layer 50 is 15 nm to 45 nm. Specifically, the thickness of the VTTO layer 50 is 15 nm. In other embodiments, the thickness of the VTTO layer 50 may be 16 nm, 23 nm, 33 nm, or 45 nm, which is not specifically limited here.
[0037] In this embodiment, the refractive index of the VTTO layer 50 is 2.15-2.35. Specifically, the refractive index of the VTTO layer 50 is 2.2. In other embodiments, the refractive index of the VTTO layer 50 may also be 2.15, 2.18, or 2.35, etc., which are not specifically limited here.
[0038] It should be noted that the SnOx layer 60 is a thin film layer made of tin oxide, which has a low production cost, good conductivity, can effectively collect and transmit current, has good optical properties, and has high transparency, which is beneficial to improving the light absorption rate of the battery.
[0039] Specifically, one of aluminum-doped zinc oxide, gallium-doped zinc oxide, cerium-doped zinc oxide, and tin oxide is prepared using ALD, PVD, and RPD equipment technologies. Preferably, the SnOx layer 60 is prepared using PVD equipment technology. The work function of the SnOx layer 60 is not less than 4.8 eV. x The optical band gap of the film is above 3.5 eV. The use of the SnOx layer 60 with a high work function can facilitate the formation of a good ohmic contact, thereby reducing contact resistance and improving fill factor.
[0040] In this embodiment, the refractive index of the SnOx layer 60 is 1.8-2.15. The refractive index of the SnOx layer 60 is no higher than that of the VTTO layer 50. Specifically, the refractive index of the SnOx layer 60 is 1.8. In other embodiments, the refractive index of the SnOx layer 60 may be 1.9, 2, or 2.15, etc., which are not specifically limited herein.
[0041] In this embodiment, the thickness of the SnOx layer 60 is 1.5 to 3.5 times the thickness of the VTTO layer 50. Specifically, the thickness of the SnOx layer 60 is 1.5 times the thickness of the VTTO layer 50. In other embodiments, the thickness of the SnOx layer 60 may be 2 times, 2.5 times, or 3.5 times the thickness of the VTTO layer 50, which is not specifically limited here.
[0042] Specifically, the ITO layer 70 is prepared using technology including but not limited to PVD technology, CVD technology or ALD technology. Preferably, PVD technology is used in combination with an ITO target material, the target material has a purity of not less than 99.99%, a density of not less than 99%, and a composition of In2O3:SnO2=90:10wt%~97:3wt%.
[0043] In this embodiment, the thickness of the ITO layer 70 is 10-35 nm. Specifically, the thickness of the ITO layer 70 is 12 nm. In other embodiments, the thickness of the ITO layer 70 may also be 10 nm, 28 nm, or 35 nm, which is not specifically limited here.
[0044] In this embodiment, the refractive index of the ITO layer 70 is 1.75-2.1, and the refractive index of the ITO layer 70 is not higher than the refractive index of the SnOx layer 60. Specifically, the refractive index of the ITO layer 70 is 1.78. In other embodiments, the refractive index of the ITO layer 70 may also be 1.75, 1.93, or 2.1, etc., which are not specifically limited here.
[0045] It should be noted that the refractive index of the ITO layer 70 is not higher than the refractive index of the SnOx layer 60, and the refractive index of the SnOx layer 60 is not higher than the refractive index of the VTTO layer 50. After the VTTO layer 50, the SnOx layer 60, and the ITO layer 70 are stacked in sequence, a stacked structure with a refractive index increasing from bottom to top can be obtained, thereby reducing the reflection loss of the passivation layer, promoting carrier transfer, and ensuring maximum utilization of light.
[0046] It should be noted that the ITO layer 70 is prepared on the bottom surface of the second passivation layer. Using the ITO layer 70 as the contact layer can ensure good contact resistance, and using the VTTO layer 50 and the SnOx layer 60 as the main body of the passivation layer, so that the main structure of the passivation layer is made of indium-free material, so that the passivation layer has good conductivity and light transmittance, and is simple to prepare.
[0047] More preferably, the first passivation layer 10 is an ITO thin film, wherein the thickness of the first passivation layer 10 is 60 nm-160 nm.
[0048] In this embodiment, the thickness of the first passivation layer 10 is 60 nm. In other embodiments, the thickness of the first passivation layer 10 is 70 nm, 90 nm, 120 nm, or 160 nm, which is not specifically limited here.
[0049] In addition, the thickness of the silicon wafer 30 is 80um-180um. After cleaning the silicon wafer 30 to remove organic dirt, metal impurities and surface damage layer on the surface, the front and back sides of the silicon wafer 30 are textured.
[0050] In this embodiment, the first doped layer 20 and the second doped layer 40 are both made of amorphous silicon, amorphous silicon carbide, microcrystalline silicon, or microcrystalline silicon carbide. Preferably, an intrinsic amorphous silicon thin film a-Si:H(i) and doped microcrystalline silicon μ-Si:H(n+) and μ-Si:H(p+) are deposited on the silicon wafer 30 using one of PECVD, HWCVD, or LPCVD equipment techniques. The intrinsic amorphous silicon layer has a thickness of 2nm-20nm; the n-type doped microcrystalline silicon layer has a thickness of 15nm-60nm; and the p-type doped microcrystalline silicon layer has a thickness of 10nm-55nm.
[0051] More often, the PN junction adopts a back-side junction mode. The first doping layer 20 and the second doping layer 40 are both prepared by a microcrystalline process.
[0052] In this embodiment, the thickness of the silicon wafer 30 is 90 μm. In other embodiments, the thickness of the silicon wafer 30 may also be 80 μm, 100 μm, or 180 μm, which is not specifically limited here.
[0053] In addition, gate lines are formed on the surfaces of the first passivation layer 10 and the second passivation layer using screen printing technology.
[0054] In summary, the embodiment of the present invention provides a heterojunction cell structure and a photovoltaic module, wherein the heterojunction cell structure includes a first passivation layer 10, a first doping layer 20, a silicon wafer 30, a second doping layer 40, and a second passivation layer. The first passivation layer 10 and the first doping layer 20 are arranged on the front surface of the silicon wafer 30, and the second passivation layer and the second doping layer 40 are arranged on the back surface of the silicon wafer 30; wherein the second passivation layer includes a VTTO layer 50, a SnO X layer and ITO layer 70, VTTO layer 50, SnO X The VTTO layer 50, SnO layer and ITO layer 70 are sequentially arranged on the back of the second doping layer 40. X Layer and ITO layer 70, since the ITO layer 70 contains a large amount of indium, the ITO layer 70 serves as the contact surface of the second passivation layer, which can ensure good contact, and SnO is stacked on the ITO layer 70. X The VTTO layer 50 and the AZCO layer 50 can reduce the indium content of the passivation layer, thereby reducing the contact resistance of the second passivation layer body. Moreover, the VTTO layer 50, the AZCO layer, and the AZO layer all use indium-free materials, which reduces the contact resistance of the passivation layer body while ensuring battery efficiency.
[0055] The photovoltaic module includes a battery string, and the battery string includes at least two heterojunction battery structures. When in use, a VTTO layer 50, a SnO layer 51, and a second doping layer 40 are sequentially provided on the back of the second doping layer 40. X Layer and ITO layer 70, since the ITO layer 70 contains a large amount of indium, the ITO layer 70 serves as the contact surface of the second passivation layer, which can ensure good contact, and SnO is stacked on the ITO layer 70. X The VTTO layer 50 and the AZCO layer 50 can reduce the indium content of the passivation layer, thereby reducing the contact resistance of the second passivation layer body. Moreover, the VTTO layer 50, the AZCO layer, and the AZO layer all use indium-free materials, which reduces the contact resistance of the passivation layer body while ensuring battery efficiency.
[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A heterojunction battery structure, characterized in that: The invention comprises a first passivation layer (10), a first doping layer (20), a silicon wafer (30), a second doping layer (40), and a second passivation layer, wherein the first passivation layer (10) and the first doping layer (20) are arranged on the front side of the silicon wafer (30), and the second passivation layer and the second doping layer (40) are arranged on the back side of the silicon wafer (30); The second passivation layer comprises a VTTO layer (50), a SnOx layer (60) and an ITO layer (70), and the VTTO layer (50), the SnOx layer (60) and the ITO layer (70) are sequentially arranged on the back side of the second doping layer (40).
2. The heterojunction battery structure according to claim 1, characterized in that: The refractive index of the SnOx layer (60) is 1.8-2.
15.
3. The heterojunction battery structure according to claim 2, characterized in that: The refractive index of the SnOx layer (60) is not higher than the refractive index of the VTTO layer (50).
4. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the SnOx layer (60) is 1.5 to 3.5 times the thickness of the VTTO layer (50).
5. The heterojunction battery structure according to claim 4, characterized in that: The thickness of the VTTO layer (50) is 15nm-45nm.
6. The heterojunction battery structure according to claim 1, characterized in that: The refractive index of the ITO layer (70) is not higher than the refractive index of the SnOx layer (60).
7. The heterojunction battery structure according to claim 6, characterized in that: The refractive index of the ITO layer (70) is 1.75-2.
1.
8. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the ITO layer (70) is 10 nm to 35 nm.
9. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the first passivation layer (10) is 60nm-160nm.
10. A photovoltaic module, characterized in that: The invention comprises a battery string, wherein the battery string comprises at least two heterojunction battery structures according to any one of claims 1 to 9.