Heterojunction cell structure and photovoltaic module
By using a multilayer gradient film structure of VTTO, AZCO, AZO and ITO layers in the heterojunction battery structure, the problem of high contact resistance is solved, and efficient battery performance and low-cost production are achieved.
Patent Information
- Application Number
- CN202422640127.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-30
AI Technical Summary
The contact resistance in existing heterojunction battery structures is large, resulting in high production costs and low efficiency.
A multi-layer gradient film structure of VTTO layer, AZCO layer, AZO layer and ITO layer is adopted to reduce the indium content of the passivation layer, and indium-free materials are used to ensure good conductivity and transmittance.
Effectively reduce contact resistance, improve battery efficiency and reduce production costs.
Smart Images
Figure CN223415217U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of solar cells, in particular to a heterojunction cell structure and a photovoltaic module. Background Art
[0002] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0003] The heterojunction battery structure in the prior art has the technical problem of large contact resistance. Utility Model Content
[0004] The utility model provides a heterojunction battery structure and a photovoltaic component, which can reduce contact resistance while ensuring battery efficiency.
[0005] The embodiment of the present utility model can be implemented as follows:
[0006] An embodiment of the present invention provides a heterojunction battery structure, comprising a first passivation layer, a first doped layer, a silicon wafer, a second doped layer, and a second passivation layer, wherein the first passivation layer and the first doped layer are arranged on the front side of the silicon wafer, and the second passivation layer and the second doped layer are arranged on the back side of the silicon wafer;
[0007] The first passivation layer includes a VTTO layer, an AZCO layer, an AZO layer, and an ITO layer, and the VTTO layer, the AZCO layer, the AZO layer, and the ITO layer are sequentially arranged on the front side of the first doping layer.
[0008] Optionally, the thickness of the AZCO layer is 2 to 5 times the thickness of the VTTO layer.
[0009] Optionally, the thickness of the VTTO layer is 15 nm-45 nm.
[0010] Optionally, the refractive index of the VTTO layer is 2.15-2.35.
[0011] Optionally, the thickness of the AZO layer is 1.5 to 2.5 times the thickness of the VTTO layer.
[0012] Optionally, the refractive index of the AZCO layer and the refractive index of the AZO layer are both 1.8-2.15.
[0013] Optionally, the refractive index of the AZCO layer is greater than the refractive index of the AZO layer.
[0014] Optionally, the thickness of the ITO layer is 10 nm-35 nm.
[0015] Optionally, the refractive index of the ITO layer is 1.75-2.1, and the refractive index of the ITO layer is not greater than the refractive index of the AZO layer.
[0016] An embodiment of the present invention further provides a photovoltaic assembly, comprising a cell string, wherein the cell string comprises at least two heterojunction cell structures.
[0017] The beneficial effects of the heterojunction cell structure and photovoltaic module of the embodiments of the present invention include, for example:
[0018] The heterojunction battery structure includes a first passivation layer, a first doped layer, a silicon wafer, a second doped layer, and a second passivation layer. The first passivation layer and the first doped layer are arranged on the front side of the silicon wafer, and the second passivation layer and the second doped layer are arranged on the back side of the silicon wafer. The first passivation layer includes a VTTO layer, an AZCO layer, an AZO layer, and an ITO layer, and the VTTO layer, the AZCO layer, the AZO layer, and the ITO layer are arranged in sequence on the front side of the first doped layer. During use, the VTTO layer, the AZCO layer, the AZO layer, and the ITO layer are arranged in sequence on the front side of the first doped layer. Because the ITO layer contains a large amount of indium, the ITO layer, the VTTO layer, the AZCO layer, and the AZO layer are jointly formed into a bottom high-refractive-index gradient film structure. While ensuring the passivation effect, the indium content of the passivation layer can be reduced, thereby reducing the contact resistance. Moreover, the VTTO layer, the AZCO layer, and the AZO layer are all made of indium-free materials, ensuring good conductivity and transmittance of the battery, thereby ensuring battery efficiency.
[0019] The photovoltaic module includes a cell string comprising at least two heterojunction cell structures. During use, a VTTO layer, an AZCO layer, an AZO layer, and an ITO layer are sequentially arranged on the front surface of the first doped layer. Because the ITO layer contains a large amount of indium, the ITO layer, the VTTO layer, the AZCO layer, and the AZO layer are combined to form a bottom layer high-refractive-index gradient film structure. While maintaining a passivation effect, the indium content of the passivation layer can be reduced, thereby reducing contact resistance. Furthermore, the VTTO layer, the AZCO layer, and the AZO layer are all made of indium-free materials, ensuring good conductivity and transmittance of the cell, thereby guaranteeing cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 This is a schematic diagram of the structure of the heterojunction battery provided in this embodiment.
[0022] Icon: 10-ITO layer; 20-AZO layer; 30-AZCO layer; 40-VTTO layer; 50-first doped layer; 60-silicon wafer; 70-second doped layer; 80-second passivation layer. DETAILED DESCRIPTION
[0023] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.
[0025] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0026] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the utility model product is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.
[0027] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.
[0028] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention can be combined with each other.
[0029] With the continuous advancement and development of science and technology, the photovoltaic field has gradually expanded, and more and more different types of batteries are widely used in industry and daily life. Heterojunction batteries are one of these types of batteries. Heterojunction solar cells, abbreviated as HIT (Heterojunction with Intrinsic Thin-layer), have the advantages of high conversion efficiency, good temperature characteristics, and a short manufacturing process.
[0030] The heterojunction battery structure in the related art has a technical problem of large contact resistance.
[0031] Please refer to Figure 1 This embodiment provides a photovoltaic module comprising a cell string comprising at least two heterojunction cell structures. This photovoltaic module can effectively address the aforementioned technical issues, reducing contact resistance while maintaining cell efficiency.
[0032] Please refer to Figure 1 This embodiment provides a heterojunction battery structure including a first passivation layer, a first doping layer 50, a silicon wafer 60, a second doping layer 70 and a second passivation layer 80. The first passivation layer and the first doping layer 50 are arranged on the front side of the silicon wafer 60, and the second passivation layer 80 and the second doping layer 70 are arranged on the back side of the silicon wafer 60; wherein, the first passivation layer includes a VTTO layer 40, an AZCO layer 30, an AZO layer 20 and an ITO layer 10, and the VTTO layer 40, the AZCO layer 30, the AZO layer 20 and the ITO layer 10 are arranged in sequence on the front side of the first doping layer 50.
[0033] Currently, most existing battery structures use tin-doped indium oxide (ITO) as a transparent conductive film. ITO contains over 90% indium, a rare and expensive metal. Using ITO as a transparent conductive film significantly increases production costs. Using a low-indium transparent conductive film can result in excessively high interface contact resistance. In order to solve this technical problem, when the heterojunction battery structure provided in this embodiment is used, a VTTO layer 40, an AZCO layer 30, an AZO layer 20 and an ITO layer 10 are sequentially arranged on the front side of the first doping layer 50. Since the ITO layer 10 contains a large amount of indium, the ITO layer 10 and the VTTO layer 40, the AZCO layer 30 and the AZO layer 20 are jointly made into a bottom layer high refractive index gradient film structure. While ensuring the passivation effect, the indium content of the passivation layer can be reduced, thereby reducing the contact resistance. Moreover, the VTTO layer 40, the AZCO layer 30 and the AZO layer 20 are all made of indium-free materials, which ensures that the conductivity and transmittance of the battery are good, thereby ensuring the battery efficiency.
[0034] Specifically, the VTTO layer 40 is a thin film made of vertical target tin oxide using PVD technology. During the sputtering process, VTTO forms a tin oxide target material in a vertical direction, exhibiting excellent conductivity and optical properties. The target material has a purity of no less than 99.99% and a density of no less than 99%. Its composition is In2O3:SnO2 = 95% to 99.5% by weight, preferably In2O3:SnO2 = 99% by weight.
[0035] In this embodiment, the thickness of the VTTO layer 40 is 15 nm to 45 nm. Specifically, the thickness of the VTTO layer 40 is 20 nm. In other embodiments, the thickness of the VTTO layer 40 may be 15 nm, 26 nm, 30 nm, or 45 nm, which is not specifically limited here.
[0036] In this embodiment, the refractive index of the VTTO layer 40 is 2.15-2.35. Specifically, the refractive index of the VTTO layer 40 is 2.15. In other embodiments, the refractive index of the VTTO layer 40 may also be 2.2, 2.3, or 2.35, etc., which is not specifically limited here.
[0037] As can be understood, the AZCO layer 30 is a thin film layer made of aluminum (Al) doped with zinc oxide and cadmium oxide, and has good light transmittance and electrical conductivity. The AZO layer 20 is a thin film layer made of a zinc oxide aluminum target doped with aluminum (Al) and cerium (Ce), and has good light transmittance and electrical conductivity.
[0038] Specifically, the AZO layer 20 and the AZCO layer 30 are prepared using, but not limited to, PVD technology or ALD technology. The Al content in the AZO layer 20 and the AZCO layer 30 is 1%-7.5%, the Ce content is 1%-15%, and the refractive index of the AZO layer 20 and the AZCO layer 30 is 1.8-2.15. The refractive index of the AZCO layer 30 is greater than that of the AZO layer 20.
[0039] In this embodiment, the Al content in the AZO layer 20 and the AZCO layer 30 is 2%. In other embodiments, the Al content in the AZO layer 20 and the AZCO layer 30 may also be 1%, 4%, or 7.5%, etc., which is not specifically limited here.
[0040] In this embodiment, the Ce content in the AZO layer 20 and the AZCO layer 30 is 1%. In other embodiments, the Ce content in the AZO layer 20 and the AZCO layer 30 may also be 6%, 8%, or 15%, etc., which is not specifically limited here.
[0041] In this embodiment, the refractive index of the AZCO layer 30 is 1.8, and the refractive index of the AZO layer 20 is 2. In other embodiments, the refractive index of the AZCO layer 30 may be 1.9 or 2, and the refractive index of the AZO layer 20 may be 2.1 or 2.15, etc., which are not specifically limited here.
[0042] In this embodiment, the thickness of the AZO layer 20 is 1.5 to 2.5 times the thickness of the VTTO layer 40. Specifically, the thickness of the AZO layer 20 is 1.5 times the thickness of the VTTO layer 40. In other embodiments, the thickness of the AZO layer 20 may be 1.7 times, 2 times, or 2.5 times the thickness of the VTTO layer 40, which is not specifically limited herein.
[0043] In this embodiment, the thickness of the AZCO layer 30 is 2 to 5 times the thickness of the VTTO layer 40. Specifically, the thickness of the AZCO layer 30 is 2 times the thickness of the VTTO layer 40. In other embodiments, the thickness of the AZCO layer 30 may be 3, 4, or 5 times the thickness of the VTTO layer 40, etc., which is not specifically limited here.
[0044] Specifically, the ITO layer 10 is prepared using technology including but not limited to PVD technology, CVD technology or ALD technology. Preferably, PVD technology is used in combination with an ITO target material, the target material has a purity of not less than 99.99%, a density of not less than 99%, and a composition of In2O3:SnO2=90:10wt%~98:2wt%.
[0045] In this embodiment, the thickness of the ITO layer 10 is 10-35 nm. Specifically, the thickness of the ITO layer 10 is 10 nm. In other embodiments, the thickness of the ITO layer 10 may also be 20 nm, 30 nm, or 35 nm, which is not specifically limited here.
[0046] In this embodiment, the refractive index of the ITO layer 10 is 1.75-2.1, and the refractive index of the ITO layer 10 is not greater than the refractive index of the AZO layer 20. Specifically, the refractive index of the ITO layer 10 is 1.75. In other embodiments, the refractive index of the ITO layer 10 may also be 1.8, 1.9, or 2.1, etc., which are not specifically limited here.
[0047] It should be noted that the refractive index of the ITO layer 10 is not greater than the refractive index of the AZO layer 20, the refractive index of the AZCO layer 30 is greater than the refractive index of the AZO layer 20, and the refractive index of the VTTO layer 40 is greater than the refractive index of the AZCO layer 30. After the VTTO layer 40, the AZCO layer 30, the AZO layer 20 and the ITO layer 10 are stacked in sequence, a stacked structure in which the refractive index decreases from bottom to top can be obtained, thereby reducing the reflection loss of the passivation layer, promoting carrier transfer, and ensuring maximum utilization of light.
[0048] In this embodiment, a VTTO layer 40, an AZCO layer 30, an AZO layer 20 and an ITO layer 10 are stacked in sequence on the front side of the first doping layer 50, thereby obtaining a multi-layered passivation layer structure, which reduces the indium content of the passivation layer and reduces the contact resistance at the interface, thereby ensuring the battery efficiency.
[0049] It should be noted that the ITO layer 10 is prepared on the top layer of the passivation layer. Using the ITO layer 10 as the contact layer can ensure good contact resistance, and the VTTO layer 40, the AZCO layer 30 and the AZO layer 20 are used as the main body of the passivation layer, so that the main structure of the passivation layer is made of indium-free material, so that the passivation layer has good conductivity and light transmittance, and is simple to prepare.
[0050] Furthermore, the thickness of the silicon wafer 60 of the heterojunction cell structure is 80um-180um. After cleaning the silicon wafer 60 to remove organic dirt, metal impurities and surface damage layer on the surface, the front and back sides of the silicon wafer 60 are textured.
[0051] In this embodiment, the first doped layer 50 and the second doped layer 70 are both made of amorphous silicon, amorphous silicon carbide, microcrystalline silicon, or microcrystalline silicon carbide. Preferably, an intrinsic amorphous silicon thin film a-Si:H(i) and doped microcrystalline silicon μ-Si:H(n+) and μ-Si:H(p+) are deposited on the silicon wafer 60 using one of PECVD, HWCVD, or LPCVD equipment techniques. The intrinsic amorphous silicon layer has a thickness of 5nm-15nm; the n-type doped microcrystalline silicon layer has a thickness of 20nm-60nm; and the p-type doped microcrystalline silicon layer has a thickness of 15nm-50nm.
[0052] Specifically, the first doping layer 50 and the second doping layer 70 are both prepared by using a microcrystal process.
[0053] More preferably, the second passivation layer 80 is an ITO thin film.
[0054] In addition, gate lines are formed on the surfaces of the first passivation layer and the second passivation layer 80 using a screen printing technique.
[0055] In summary, the embodiments of the present invention provide a heterojunction battery structure and a photovoltaic module, which heterojunction battery structure includes a first passivation layer, a first doping layer 50, a silicon wafer 60, a second doping layer 70 and a second passivation layer 80. The first passivation layer and the first doping layer 50 are arranged on the front side of the silicon wafer 60, and the second passivation layer 80 and the second doping layer 70 are arranged on the back side of the silicon wafer 60; wherein, the first passivation layer includes a VTTO layer 40, an AZCO layer 30, an AZO layer 20 and an ITO layer 10, and the VTTO layer 40, the AZCO layer 30, the AZO layer 20 and the ITO layer 10 are arranged in sequence on the front side of the first doping layer 50. When in use, a VTTO layer 40, an AZCO layer 30, an AZO layer 20 and an ITO layer 10 are sequentially arranged on the front side of the first doping layer 50. Since the ITO layer 10 contains a large amount of indium, the ITO layer 10, the VTTO layer 40, the AZCO layer 30 and the AZO layer 20 are jointly made into a bottom layer high refractive index gradient film structure. While ensuring the passivation effect, the indium content of the passivation layer can be reduced, thereby reducing the contact resistance. Moreover, the VTTO layer 40, the AZCO layer 30 and the AZO layer 20 are all made of indium-free materials, which ensures that the conductivity and transmittance of the battery are good, thereby ensuring the battery efficiency.
[0056] The photovoltaic module includes a cell string, which includes at least two heterojunction cell structures. During use, a VTTO layer 40, an AZCO layer 30, an AZO layer 20, and an ITO layer 10 are sequentially arranged on the front surface of a first doped layer 50. Because the ITO layer 10 contains a large amount of indium, the ITO layer 10, the VTTO layer 40, the AZCO layer 30, and the AZO layer 20 are collectively formed into a bottom layer high-refractive-index gradient film structure. While ensuring the passivation effect, the indium content of the passivation layer can be reduced, thereby reducing contact resistance. Moreover, the VTTO layer 40, the AZCO layer 30, and the AZO layer 20 are all made of indium-free materials, ensuring good conductivity and transmittance of the cell, thereby ensuring cell efficiency.
[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A heterojunction battery structure, characterized in that: The invention comprises a first passivation layer, a first doping layer (50), a silicon wafer (60), a second doping layer (70), and a second passivation layer (80), wherein the first passivation layer and the first doping layer (50) are arranged on the front side of the silicon wafer (60), and the second passivation layer (80) and the second doping layer (70) are arranged on the back side of the silicon wafer (60); The first passivation layer comprises a VTTO layer (40), an AZCO layer (30), an AZO layer (20), and an ITO layer (10); the VTTO layer (40), the AZCO layer (30), the AZO layer (20), and the ITO layer (10) are sequentially arranged on the front surface of the first doping layer (50).
2. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the AZCO layer (30) is 2 to 5 times the thickness of the VTTO layer (40).
3. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the VTTO layer (40) is 15nm-45nm.
4. The heterojunction battery structure according to claim 1, characterized in that: The refractive index of the VTTO layer (40) is 2.15-2.
35.
5. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the AZO layer (20) is 1.5 to 2.5 times the thickness of the VTTO layer (40).
6. The heterojunction battery structure according to claim 1, characterized in that: The refractive index of the AZCO layer (30) and the refractive index of the AZO layer (20) are both 1.8-2.
15.
7. The heterojunction battery structure according to claim 6, characterized in that: The refractive index of the AZCO layer (30) is greater than the refractive index of the AZO layer (20).
8. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the ITO layer (10) is 10 nm to 35 nm.
9. The heterojunction battery structure according to claim 1, characterized in that: The refractive index of the ITO layer (10) is 1.75-2.1, and the refractive index of the ITO layer (10) is not greater than the refractive index of the AZO layer (20).
10. A photovoltaic module, characterized in that: The invention comprises a battery string, wherein the battery string comprises at least two heterojunction battery structures according to any one of claims 1 to 9.