Electrostatic discharge test system
The relay matrix in the electrostatic discharge test system automatically controls the connection between the test socket, the electrostatic discharge generation module and the source meter, solving the tedious problem of multi-pin IC testing and achieving efficient and reliable electrostatic discharge testing.
Patent Information
- Application Number
- CN202422804342.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-18
AI Technical Summary
Existing electrostatic discharge test devices are cumbersome to operate when dealing with multi-pin ICs, have difficulty connecting to small-sized pins, and have low test efficiency and cannot guarantee test consistency.
An electrostatic discharge test system is used, including an electrostatic discharge generation module, a relay matrix, a test socket, a source meter, and a residual voltage discharge module. The relay matrix automatically controls the connection between the test socket and the electrostatic discharge generation module and the source meter, realizing an automated test process and simplifying manual operations.
It improves the efficiency and reliability of electrostatic discharge testing, ensures the consistency of test quality, simplifies the test process, and reduces human errors.
Smart Images
Figure CN223450096U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to semiconductor element test technical field especially relates to electrostatic discharge test system. BACKGROUND
[0002] ESD (Electro-Static discharge) represents electrostatic discharge. The ESD of human body discharge mode (HBM) refers to the static electricity that has accumulated on the human body due to the friction or other factors when the human body walks on the ground, when the human body touches the IC, the static electricity on the human body will enter the IC through the pin of the IC, and then discharge to the ground through the IC. The process of discharge can generate a few hundred nanosecond of instantaneous discharge current in a few hundred nanoseconds, which will burn the components in the IC.
[0003] The existing electrostatic discharge test device, when the number of pins of the IC device to be tested increases, the number of manual connections required by the operator will increase exponentially. When the size of the IC pin to be tested is small, it cannot be directly connected to the existing electrostatic discharge device, so an additional PCB adapter plate needs to be added for testing. After each test is completed, the IC needs to be connected to the semiconductor tester to determine whether the IC is damaged. The test process is extremely complicated, inefficient, and the increase in uncertain factors causes uncontrollable test differences. UTILITY MODEL CONTENT
[0004] The utility model aims at providing electrostatic discharge test system, can solve one or more of the above prior art problems.
[0005] According to one aspect of the utility model, an electrostatic discharge test system is provided, comprising an electrostatic discharge generation module, a relay matrix, a test seat, a source table and a residual voltage discharge module. The electrostatic discharge generation module is connected to the test seat through the relay matrix. The source table is connected to the test seat through the relay matrix. The residual voltage discharge module is connected to the test seat. The electrostatic discharge generation module is used to generate test voltage. The relay matrix is used to control the on-off between the test seat and the electrostatic discharge generation module, and is used to control the on-off between the test seat and the source table. The test seat is used to place the chip to be tested. The source table is used to measure the IV curve of the chip to be tested. The residual voltage discharge module is used to release the residual voltage of the chip to be tested.
[0006] In some embodiments, the relay matrix comprises a relay S1, a relay S2 and a plurality of relay branches, the static contacts of the relay S1 are connected to the negative terminal of the source table and the common terminal of the electrostatic discharge generation module respectively, the static contacts of the relay S2 are connected to the positive terminal of the source table and the output terminal of the electrostatic discharge generation module respectively, each relay branch comprises a first branch relay and a second branch relay connected in series, the static contacts of the first branch relay are connected to the moving contacts of the relay S1 and the moving contacts of the relay S2 respectively, the moving contact of the first branch relay is connected to the moving / static contact of the second branch relay, and the static / moving contact of the second branch relay is connected to the pin of the test socket.
[0007] In some embodiments, the residual voltage discharge module comprises a relay S5 and a resistor R1, one end of the resistor R1 is connected to the moving contact of the relay S2, and the other end of the resistor R1 is grounded through the relay S5.
[0008] In some embodiments, the test socket is provided with 32 pins, and the number of relay branches of the relay matrix is 32.
[0009] In some embodiments, a control module is further included, the control module is electrically connected with the relay matrix and the residual voltage discharge module, and the control module is used for controlling the on-off of each relay in the relay matrix and the residual voltage discharge module.
[0010] In some embodiments, a host computer is further included, the host computer is in communication connection with the electrostatic discharge generation module and the source table through a LAN switch.
[0011] The electrostatic discharge test system provided by the utility model connects the test socket, the electrostatic discharge generation module and the source table through the relay matrix, replaces manual switching with the relay matrix, takes points on the IV curve of the chip to be tested in real time through the source table, judges whether the chip to be tested is damaged after electrostatic discharge test, simplifies the electrostatic discharge test process, improves test reliability and efficiency, and guarantees test quality.
[0012] In addition, in the technical scheme of the utility model, any part not specially described can be realized by using conventional means in the art. BRIEF DESCRIPTION OF DRAWINGS
[0013] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the utility model, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.
[0014] Fig. 1The utility model provides a structure schematic drawing of electrostatic discharge test system of an embodiment of the utility model.
[0015] Fig. 2 The utility model provides a circuit diagram of electrostatic discharge test system of an embodiment of the utility model. DETAILED DESCRIPTION
[0016] In order to make the purpose, technical scheme and advantage of the utility model embodiment more clear, the technical scheme in the utility model embodiment will be clearly and completely described below in conjunction with the drawings in the utility model embodiment, obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiment. Based on the embodiment in the utility model, all other embodiments obtained by the ordinary skill in the art without making the creative labor belong to the range of the utility model protection.
[0017] EMBODIMENT
[0018] In the embodiment, reference is made to the drawings in the specification Figs. 1-2 , provide electrostatic discharge test system, and the system includes electrostatic discharge generation module 1, relay matrix 2, test seat 3, source table 4, residual voltage discharge module 5, control module 6, host computer 7 and LAN switch 8.
[0019] Among them, electrostatic discharge generation module 1 is connected with test seat 3 through relay matrix 2, and source table 4 is connected with test seat 3 through relay matrix 2, and residual voltage discharge module 5 is connected with test seat 3.
[0020] Electrostatic discharge generation module 1 is used to generate test voltage;Relay matrix 2 is used to control the on-off between test seat 3 and electrostatic discharge generation module 1, and relay matrix 2 is used to control the on-off between test seat 3 and source table 4;Test seat 3 is used to place the chip to be measured, and source table 4 is used to measure the IV curve of the chip to be measured, and residual voltage discharge module 5 is used to release the residual voltage of the chip to be measured.
[0021] Control module 6 is electrically connected with relay matrix 2 and residual voltage discharge module 5, and control module 6 is used to control the on-off of each relay in relay matrix 2 and residual voltage discharge module 5.
[0022] Host computer 7 is communicatedly connected with electrostatic discharge generation module 1 and source table 4 through LAN switch 8. Host computer 7 can also be communicatedly connected with control module 6 through LAN switch 8.
[0023] In an optional embodiment, the static electricity discharge generation module 1 can be selected as an HBM static electricity discharge generator, so that the host computer 7 can control the static electricity discharge generation module 1 through the LAN switch 8. When the test seat 3 is connected to the static electricity discharge generation module 1 through the relay matrix 2, the static electricity discharge generation module 1 can apply a test pulse from low to high to the chip to be tested, and the voltage level, pulse width, rise time, polarity and other parameters of the pulse can be configured.
[0024] In an optional embodiment, the host computer 7 can control the source table 4 through the LAN switch 8. When the test seat 3 is connected to the source table 4 through the relay matrix 2, the source table can collect transient operating voltage and current, and draw an IV characteristic curve of the chip to be tested according to the collected transient operating voltage and current. The host computer can determine whether the chip to be tested is failed according to the IV characteristic curve of the chip to be tested and feed back to the host computer 7.
[0025] In an optional embodiment, the relay matrix 2 can include a relay S1, a relay S2 and a plurality of relay branches. The static contact of the relay S1 is connected to the negative terminal of the source table 4 and the common terminal of the static electricity discharge generation module 1, respectively. The static contact of the relay S2 is connected to the positive terminal of the source table 4 and the output terminal of the static electricity discharge generation module 1, respectively. Each relay branch includes a first branch relay and a second branch relay connected in series. The static contact of the first branch relay is connected to the moving contact of the relay S1 and the moving contact of the relay S2, respectively. The moving contact of the first branch relay is connected to the moving / static contact of the second branch relay. The static / moving contact of the second branch relay is connected to the pin of the test seat 3.
[0026] Taking the first relay branch as an example, the first relay branch includes a first branch relay S3 and a second branch relay S4 connected in series. The static contact of the first branch relay S3 is connected to the moving contact of the relay S1 and the moving contact of the relay S2, respectively. The moving contact of the first branch relay S3 is connected to the moving / static contact of the second branch relay S4. The static / moving contact of the second branch relay S4 is connected to the pin of the test seat 3.
[0027] Therefore, through the relay S1, the relay S2, the first branch relay and the second branch relay in each relay branch, the continuity between the pin of the chip to be tested connected to the test seat 3 and the source table 4, and the continuity between the pin of the chip to be tested connected to the test seat 3 and the static electricity discharge generation module 1 can be controlled. The first branch relay is used to control whether the pin of the chip to be tested is connected to the common terminal or the output terminal of the static electricity discharge generation module 1. The second branch relay is used to control whether the pin of the chip to be tested is connected to the static electricity discharge generation module 1 for static electricity discharge test.
[0028] In an optional embodiment, the residual voltage discharging module 5 comprises a relay S5 and a resistor R1, one end of the resistor R1 is connected with the movable contact of the relay S2, and the other end of the resistor R1 is grounded through the relay S5. Thus, the residual charge of the pin of the chip under test can be discharged through the relay S5 after each electrostatic discharge test is completed, so as to prevent the residual voltage of the pin of the chip under test from damaging the source table 4 and improve the service life of the system.
[0029] In an optional embodiment, the relay S5 can be provided with a delay time, that is, the relay S5 is automatically disconnected after a preset delay time after being closed, so as to effectively ensure the discharging effect of the residual voltage discharging module 5, and the automatic disconnection can avoid forgetting to operate to always ground, which affects the test effect and accuracy.
[0030] In an optional embodiment, the delay time of the relay S5 can be 20 ms.
[0031] In an optional embodiment, the test seat 3 is provided with 32 pins, which are respectively marked as pin1, pin2, …, pin32, and the number of relay branches of the relay matrix 2 is correspondingly set to 32. Thus, the test seat 3 can simultaneously test up to 8 chips under test.
[0032] In an optional embodiment, the distance from each pin in the test seat 3 to the output end of the electrostatic discharge generation module 1 can be equal. Thus, the stability of the electrostatic discharge pulse is ensured, and the test precision and reliability are improved.
[0033] In an optional embodiment, the upper computer 7 can generate a test report according to the measurement result of the source table 4 and the configuration information of the electrostatic discharge generation module 1.
[0034] In an optional embodiment, the control module 6 can control the on-off of each relay branch according to the actual connection condition of the test seat 3 and the chip under test.
[0035] The electrostatic discharge test system provided by the utility model, when electrostatic discharge test is carried out on the chip under test, first make relay S1 and relay S2 respectively communicate with the common end and the output end of electrostatic discharge generation module 1, the movable contact of the first branch relay is connected with relay S1 or relay S2 according to the pulse output condition of electrostatic discharge generation module 1, the second branch relay is closed, at this time, test seat 3 is communicated with electrostatic discharge generation module 1, and electrostatic discharge test can be carried out, after the test is completed, relay S5 is closed, and the residual voltage of the pin of the chip under test connected with test seat 3 is discharged, relay S5 is automatically disconnected after a delay, at this time, control module 6 controls the action of relay S1 and relay S2, relay S1 and relay S2 are respectively communicated with the positive terminal and the negative terminal of source table 4, source table 4 measures the IV curve of the test chip, and whether the test chip is damaged is judged.
[0036] The electrostatic discharge test system provided by the utility model can realize the HBM test function defined in the JS-001-2010 standard; a test socket is connected to an electrostatic discharge generation module and a source meter via a relay matrix, the relay matrix replaces manual switching, and the source meter is used to take points on the IV curve of the chip to be tested in real time to determine whether the chip to be tested is damaged after the electrostatic discharge test, thereby simplifying the electrostatic discharge test process, improving test reliability and efficiency, and ensuring test quality.
[0037] The above is only an optional implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. Electrostatic discharge test system, characterized in that, include Electrostatic discharge generation module (1), relay matrix (2), test socket (3), source meter (4) and residual voltage discharge module (5), The electrostatic discharge generating module (1) is connected to the test socket (3) via the relay matrix (2). The source meter (4) is connected to the test socket (3) via the relay matrix (2). The residual pressure discharge module (5) is connected to the test socket (3), The electrostatic discharge generating module (1) is used to generate a test voltage; The relay matrix (2) is used to control the on / off between the test socket (3) and the electrostatic discharge generating module (1), and the relay matrix (2) is used to control the on / off between the test socket (3) and the source meter (4); The test seat (3) is used to place the chip to be tested. The source meter (4) is used to measure the IV curve of the chip to be tested. The residual voltage discharge module (5) is used for releasing the residual voltage of the chip to be tested.
2. The electrostatic discharge testing system according to claim 1, wherein: The relay matrix (2) includes a relay S1, a relay S2 and a plurality of relay branches. The static contacts of the relay S1 are respectively connected to the negative terminal of the source meter (4) and the common terminal of the electrostatic discharge generating module (1). The static contacts of the relay S2 are respectively connected to the positive terminal of the source meter (4) and the output end of the electrostatic discharge generating module (1), Each of the relay branches includes a first branch relay and a second branch relay connected in series, wherein the static contact of the first branch relay is connected to the moving contact of the relay S1 and the moving contact of the relay S2 respectively. The moving contact of the first branch relay is connected to the moving / static contact of the second branch relay, The static / dynamic contacts of the second branch relay are connected to the pins of the test socket (3).
3. The electrostatic discharge testing system according to claim 2, wherein: The residual pressure discharge module (5) includes a relay S5 and a resistor R1. One end of the resistor R1 is connected to the movable contact of the relay S2 , and the other end of the resistor R1 is grounded via the relay S5 .
4. The electrostatic discharge testing system according to claim 1, wherein: The test socket (3) is provided with 32 pins, and the number of relay branches of the relay matrix (2) is 32.
5. The electrostatic discharge testing system according to claim 1, wherein: It also includes a control module (6), which is electrically connected to the relay matrix (2) and the residual voltage discharge module (5), and is used to control the on and off of each relay in the relay matrix (2) and the residual voltage discharge module (5).
6. The electrostatic discharge testing system according to claim 1, wherein: It also includes a host computer (7), which is communicatively connected to the electrostatic discharge generating module (1) and the source meter (4) via a LAN switch (8).