Output transient response control circuit
By monitoring output current and voltage changes through an output transient response control circuit, the problem of large output voltage undershoot in LDOs when the input voltage changes is solved, achieving the effects of fast response and small output undershoot.
Patent Information
- Application Number
- CN202520100476.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2035-01-16
AI Technical Summary
Existing low-dropout linear regulators (LDOs) suffer from excessive output voltage undershoot when only detecting changes in output bias current and when the input voltage changes and approaches the power transistor threshold voltage.
An output transient response control circuit is adopted, including an error amplifier, a power transistor, a capacitor impedance circuit, an output current detection control circuit, an output voltage detection control circuit, and an output undershoot detection control circuit. By simultaneously monitoring changes in output current and voltage, the rapid discharge of the gate voltage is controlled, thereby improving the transient response speed.
Within a wide input and output voltage range, the gate voltage can be effectively adjusted to reduce output undershoot, improve transient load capacity, and enhance the transient response speed and reliability of the LDO.
Smart Images
Figure CN223450364U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to power management technical field, concretely relates to an output transient response control circuit. BACKGROUND
[0002] Low dropout linear regulator (LDO) is an important power management chip, has small noise, low power consumption, simple structure and the like advantages, is widely used in various electronic products, and its working characteristic is directly related to the performance and reliability of electronic products. With the rapid development of digital economy, the structure of various industrial instruments, automobile electronics, intelligent household appliances, portable intelligent devices and the like electronic products is increasingly complex, the function is increasingly powerful, the precision is gradually improved, thereby the precision, transient response ability, reliability and the like performance indexes of the LDO chip used are also improved.
[0003] Figure 1 It is a single-pole error amplifier (core amplifier) that works in non-inverted unit gain structure cooperates with slew rate enhancement technology (Slew Rate Enhanced, SRE), changes the charge-discharge current of the gate current of the adjusting tube by detecting the dynamic change current of the core amplifier, to improve the transient response speed of the LDO loop. SRE circuit only generates a dynamic compensation current, and if the load current is constant, SRE circuit only has a static leakage current. Complete the rapid discharge of the gate capacitance of the adjusting tube without increasing the static power consumption of the system. The disadvantage is that only the output bias current change is detected, and when the input voltage changes and the input voltage and the output voltage are close to less than a threshold voltage of a power tube, the gate voltage adjustment is insufficient, resulting in a large output voltage undershoot amplitude. UTILITARIAN CONTENT
[0004] In view of the defects of the prior art, the utility model provides an output transient response control circuit, which aims at solving the problem of only detecting the output bias current change, and when the input voltage changes and the input voltage and the output voltage are close to less than a threshold voltage of a power tube, the gate voltage adjustment is insufficient, resulting in a large output voltage undershoot amplitude.
[0005] To achieve the above object, the utility model adopts the following technical scheme:
[0006] An output transient response control circuit, comprising: an error amplifier, a power tube M P , a capacitor impedance circuit, an output current detection control circuit, an output voltage detection control circuit and an output undershoot detection control circuit;The noninverting input and inverting input of the error amplifier are connected with reference voltage V OUT_SET And output voltage V OUT , the output end of the error amplifier is connected with the power tube M PThe gate of the power tube M P The source connection input voltage V IN , the power tube M P The drain connection output voltage V OUT ; The capacitor impedance circuit is connected to the output voltage V OUT The input end of the output current detection control circuit is connected to the power tube M P The output terminal of the output current detection control circuit is connected to the current input terminal of the output undershoot detection control circuit, and the output current detection control circuit is used to detect the output current of the LDO circuit; the input terminal of the output voltage detection control circuit is connected to the output voltage V OUT The output end of the output voltage detection control circuit is connected to the voltage input end of the output undershoot detection control circuit, and the output voltage detection control circuit is used to detect the output voltage of the LDO circuit; the output end of the output undershoot detection control circuit is connected to the power tube M P The output undershoot detection control circuit is used to control the power tube M according to the changes of the output current and the output voltage. P The gate voltage quickly discharges and turns on the power tube M P .
[0007] Furthermore, the output current detection control circuit includes: a power tube M D , MOS tube M9, MOS tube M10, MOS tube M17 and MOS tube M18; the power tube M D The gate of the power tube M P The gate connection of the power tube M D The source and input voltage V IN Connect the power tube M D The drain of the MOS transistor M9 is connected to the drain of the MOS transistor M9, the drain of the MOS transistor M9 is short-circuited with the gate of the MOS transistor M9, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the source of the MOS transistor M9 and the source of the MOS transistor M10 are grounded, the drain of the MOS transistor M10 is connected to the gate of the MOS transistor M17, the drain of the MOS transistor M17 is short-circuited with the gate of the MOS transistor M17, the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M18, the drain of the MOS transistor M18 is connected to the current input end of the output undershoot detection control circuit, and the source of the MOS transistor M17 and the source of the MOS transistor M18 are connected to the input voltage V IN .
[0008] Furthermore, the MOS transistor M17 and the MOS transistor M18 are PMOS transistors, and the MOS transistor M9 and the MOS transistor M10 are NMOS transistors.
[0009] Further, the output voltage detection control circuit comprises a resistor R1 and a capacitor C1, a first end of the resistor R1 is connected with an output voltage V OUT , a second end of the resistor R1 is connected with a first end of the capacitor C1, and a second end of the capacitor is grounded, wherein the first end of the resistor R1 is connected with a first voltage input end of the output undershoot detection control circuit as a first detection point, and the second end of the resistor is connected with a second voltage input end of the output undershoot detection control circuit as a second detection point.
[0010] Further, the output undershoot detection control circuit comprises a current source IREF, a comparator VNin, a comparator VPin, a current source I1, a current source I2, a current comparison module, MOS tubes M1, M2, M3, M4, M5, M6, M7, M8, M11, M12, M13, M14, M15, M16, M19, M20, M21, M22, M23, M31 and M41;
[0011] An input end of the current source IREF is connected with an input voltage V IN , an output end of the current source IREF is connected with a drain of the MOS tube M19, an output end of the output current detection control circuit is connected with the drain of the MOS tube M19, the drain of the MOS tube M19 is short-circuited with a gate of the MOS tube M19, and a source of the MOS tube M19 is grounded;
[0012] An inverting input end of the comparator VNin is connected with the first end of the resistor R1, a non-inverting input end of the comparator VNin is connected with the second end of the resistor R1, a positive power supply end of the comparator VNin is connected with an input voltage V IN , a negative power supply end of the comparator VNin is grounded, a drain of the MOS tube M20 is connected with a bias current input end of the comparator VNin, a gate of the MOS tube M20 is connected with a gate of the MOS tube M19, a source of the MOS tube M20 is grounded, and an output end of the comparator VNin is connected with an input end of the current source I1; an inverting input end of the comparator VPin is connected with the first end of the resistor R1, a non-inverting input end of the comparator VPin is connected with the second end of the resistor R1, a positive power supply end of the comparator VPin is connected with an input voltage V INThe connection, the negative side power terminal of the comparator VPin is connected to ground, the drain of the MOS tube M21 is connected to the bias current input terminal of the comparator VPin, the gate of the M21 is connected with the gate of the M19, the source of the M21 is connected to ground, the output terminal of the comparator VPin is connected with the input terminal of the current source I2;
[0013] The gate of the MOS tube M22 is connected with the gate of the M19, the source of the MOS tube M22 is connected to ground, the drain of the MOS tube M22 is connected with the output terminal of the current source II; the drain of the MOS tube Ml is connected with the gate of the MOS tube Ml, the drain of the MOS tube Ml is connected with the output terminal of the current source II, the source of the MOS tube Ml is connected to ground, the gate of the MOS tube M31 is connected with the gate of the MOS tube Ml, the source of the MOS tube M31 is connected to ground, the drain of the MOS tube M31 is connected with the drain of the MOS tube Ml l, the gate of the MOS tube Ml l is connected with the current comparison module, the source of the MOS tube Ml l is connected with the drain of the MOS tube M13, the drain of the MOS tube M13 is connected with the gate of the MOS tube M13, the gate of the MOS tube M13 is connected with the gate of the MOS tube M14, the source of the MOS tube M13 is connected with the source of the MOS tube M14, the input voltage V IN , the drain of the MOS tube M14 is connected with the drain of the MOS tube M7, the drain of the MOS tube M7 is connected with the gate of the MOS tube M7, the gate of the MOS tube M7 is connected with the gate of the MOS tube M8, the drain of the MOS tube M8 is connected with the gate of the power tube M P , the source of the MOS tube M7 is connected with the source of the MOS tube M8, the gate of the MOS tube M3 is connected with the gate of the MOS tube Ml, the source of the MOS tube M3 is connected to ground, the drain of the MOS tube M3 is connected with the drain of the MOS tube M5, the drain of the MOS tube M5 is connected with the gate of the MOS tube M5, the gate of the MOS tube M5 is connected with the gate of the MOS tube M6, the drain of the MOS tube M6 is connected with the drain of the MOS tube M7, the source of the MOS tube M5 is connected with the source of the MOS tube M6, the input voltage V IN ;
[0014] The gate of the MOS transistor M23 is connected with the gate of the M19, the source of the MOS transistor M23 is grounded, and the drain of the MOS transistor M23 is connected with the output end of the current source I2; the drain of the MOS transistor M2 is short-circuited with the gate of the MOS transistor M2, the drain of the MOS transistor M2 is connected with the output end of the current source I2, the source of the MOS transistor M2 is grounded, the gate of the MOS transistor M41 is connected with the gate of the MOS transistor M2, the source of the MOS transistor M41 is grounded, the drain of the MOS transistor M41 is connected with the drain of the MOS transistor M12, the gate of the MOS transistor M12 is connected with the current comparison module, the source of the MOS transistor M12 is connected with the drain of the MOS transistor M15, the drain of the MOS transistor M15 is short-circuited with the gate of the MOS transistor M15, the gate of the MOS transistor M15 is connected with the gate of the MOS transistor M16, the source of the MOS transistor M15 is connected with the source of the MOS transistor M16, and the drain of the MOS transistor M16 is connected with the drain of the MOS transistor M7. IN The gate of the MOS transistor M4 is connected with the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, and the drain of the MOS transistor M4 is connected with the drain of the MOS transistor M5.
[0015] Further, the MOS transistor M5, the MOS transistor M6, the MOS transistor M11, the MOS transistor M12, the MOS transistor M13, the MOS transistor M14, the MOS transistor M15 and the MOS transistor M16 are PMOS transistors; the MOS transistor M1, the MOS transistor M2, the MOS transistor M3, the MOS transistor M4, the MOS transistor M7, the MOS transistor M8, the MOS transistor M19, the MOS transistor M20, the MOS transistor M21, the MOS transistor M22, the MOS transistor M23, the MOS transistor M31 and the MOS transistor M41 are NMOS transistors.
[0016] Further, the capacitor impedance circuit comprises a resistor R ESR and a capacitor C LOAD , a first end of the resistor R ESR is connected with an output voltage V OUT , a second end of the resistor R ESR is connected with a first end of the capacitor C LOAD , and a second end of the capacitor C LOAD is grounded.
[0017] The output transient response control circuit has the advantages that:
[0018] The output current detection control circuit and the output voltage detection control circuit monitor the output current load and the voltage amplitude change at the same time, and the output sag detection control circuit can effectively adjust the gate voltage and control the rapid discharge of the gate voltage charge in the case that the input voltage and the output voltage are close to a MOS conduction threshold value, improve the transient response speed, rapidly improve the transient load capacity, and achieve the purpose of small output sag. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 is a circuit structure schematic diagram of a prior art gate drive circuit for detecting bias current change and swing rate enhancement;
[0020] Figure 2 is a circuit structure block diagram of an output transient response control circuit of an embodiment of the present application;
[0021] Figure 3 is a circuit structure schematic diagram of an output transient response control circuit of an embodiment of the present application. DETAILED DESCRIPTION
[0022] The present application will be further described below in combination with the drawings and specific embodiments.
[0023] As Figure 2 shown, the present application provides an output transient response control circuit, comprising: an error amplifier, a power tube M P , a capacitor impedance circuit, an output current detection control circuit, an output voltage detection control circuit and an output sag detection control circuit; the noninverting input terminal and the inverting input terminal of the error amplifier are respectively connected with a reference voltage V OUT_SET and an output voltage V OUT , the output terminal of the error amplifier is connected with the gate of the power tube M P ; the source of the power tube M P is connected with an input voltage V IN , and the drain of the power tube M P is connected with an output voltage V OUT ; the capacitor impedance circuit is connected with the output voltage V OUT ; the input terminal of the output current detection control circuit is connected with the gate of the power tube M P , the output terminal of the output current detection control circuit is connected with the current input terminal of the output sag detection control circuit, and the output current detection control circuit is used for detecting the output current of an LDO circuit; the input terminal of the output voltage detection control circuit is connected with the output voltage V OUT , the output terminal of the output voltage detection control circuit is connected with the voltage input terminal of the output sag detection control circuit, and the output voltage detection control circuit is used for detecting the output voltage of the LDO circuit; the output terminal of the output sag detection control circuit is connected with the gate of the power tube MP The gate of the power tube M P is connected with the output undershoot detection control circuit, and the output undershoot detection control circuit is used for controlling the power tube M P .
[0024] The output current detection control circuit and the output voltage detection control circuit monitor the output current load and the voltage amplitude change at the same time, and the output undershoot detection control circuit can effectively adjust the gate voltage when the input voltage and the output voltage are close to the MOS conduction threshold value in a wide input-output voltage range, control the rapid discharge of the gate voltage charge, improve the transient response speed, and achieve the purpose of small output undershoot.
[0025] As shown in Figure 3 , in some embodiments, the output current detection control circuit comprises: a power tube M D , a MOS tube M9, a MOS tube M10, a MOS tube M17 and a MOS tube M18; the gate of the power tube M D is connected with the gate of the power tube M P , the source of the power tube M D is connected with the input voltage V IN , the drain of the power tube M D is connected with the drain of the MOS tube M9, the drain of the MOS tube M9 is short-circuited with the gate of the MOS tube M9, the gate of the MOS tube M9 is connected with the gate of the MOS tube M10, the source of the MOS tube M9 is grounded with the source of the MOS tube M10, the drain of the MOS tube M10 is connected with the gate of the MOS tube M17, the drain of the MOS tube M17 is short-circuited with the gate of the MOS tube M17, the gate of the MOS tube M17 is connected with the gate of the MOS tube M18, the drain of the MOS tube M18 is connected with the current input end of the output undershoot detection control circuit, and the source of the MOS tube M17 is connected with the source of the MOS tube M18. IN .
[0026] I B , the bias current of the comparator VPin comprises two parts: a fixed bias current IREF and I C . The part I C utilizes the current of the power tube M D mirror power tube M P to monitor the change of the output current, and is a part of the bias current of the comparator VNin and the comparator VPin, which is a current feedback participating in the output overshoot. The greater the change of the output current is, the greater the proportion of I C is.
[0027] As shown in Figure 3As shown, in some embodiments, the MOS transistor M17 and the MOS transistor M18 are PMOS transistors, and the MOS transistor M9 and the MOS transistor M10 are NMOS transistors.
[0028] like Figure 3 As shown, in some embodiments, the output voltage detection control circuit includes: a resistor R1 and a capacitor C1, a first end of the resistor R1 and an output voltage V OUT The second end of the resistor R1 is connected to the first end of the capacitor C1, and the second end of the capacitor is grounded, wherein the first end of the resistor R1 is connected to the first voltage input end of the output undershoot detection control circuit as a first detection point, and the second end of the resistor is connected to the second voltage input end of the output undershoot detection control circuit as a second detection point.
[0029] When the LDO output is loaded normally and outputs smoothly, the voltages at the output voltage detection points A and B are the same, and the output currents I1 and I2 of the comparator VNin and comparator VPin are the same as I3 and I4 respectively. At this time, the current flowing through the MOS tube M1 and MOS tube M2 is close to 0, and the current mirror is mirrored to the output I DISCHG The current is close to 0, at this time the power tube M P and power tube M D The gate voltage GATE is stable and the output voltage is stable.
[0030] like Figure 3 As shown, in some embodiments, the output undershoot detection control circuit includes: a current source IREF, a comparator VNin, a comparator VPin, a current source I1, a current source I2, a current comparison module, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M19, a MOS transistor M20, a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M31, and a MOS transistor M41;
[0031] The input of the current source IREF is connected to the input voltage V IN The output end of the current source IREF is connected to the drain of the MOS tube M19, the output end of the output current detection control circuit is connected to the drain of the MOS tube M19, the drain of the MOS tube M19 is short-circuited with the gate of the MOS tube M19, and the source of the MOS tube M19 is grounded;
[0032] The inverting input terminal of the comparator VNin is connected to the first terminal of the resistor R1, the non-inverting input terminal of the comparator VNin is connected to the second terminal of the resistor R1, and the positive side power supply terminal of the comparator VNin is connected to the input voltage V INThe negative power supply terminal of the comparator VNin is grounded, the drain of the MOS tube M20 is the bias current input terminal connected to the comparator VNin, the gate of M20 is connected to the gate of M19, the source of M20 is grounded, the output terminal of the comparator VNin is connected to the input terminal of the current source I1; the inverting input terminal of the comparator VPin is connected to the first terminal of the resistor R1, the non-inverting input terminal of the comparator VPin is connected to the second terminal of the resistor R1, and the positive power supply terminal of the comparator VPin is connected to the input voltage V IN The negative power supply terminal of the comparator VPin is grounded, the drain of the MOS tube M21 is the bias current input terminal connected to the comparator VPin, the gate of M21 is connected to the gate of M19, the source of M21 is grounded, and the output terminal of the comparator VPin is connected to the input terminal of the current source I2;
[0033] The gate of the MOS transistor M22 is connected to the gate of M19, the source of the MOS transistor M22 is grounded, and the drain of the MOS transistor M22 is connected to the output end of the current source I1; the drain of the MOS transistor M1 is short-circuited with the gate of the MOS transistor M1, the drain of the MOS transistor M1 is connected to the output end of the current source I1, the source of the MOS transistor M1 is grounded, the gate of the MOS transistor M31 is connected to the gate of the MOS transistor M1, the source of the MOS transistor M31 is grounded, the drain of the MOS transistor M31 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the current comparison module, the source of the MOS transistor M11 is connected to the drain of the MOS transistor M13, the drain of the MOS transistor M13 is short-circuited with the gate of the MOS transistor M13, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M14, and the source of the MOS transistor M13 is connected to the source of the MOS transistor M14. The input voltage V IN The drain of MOS tube M14 is connected to the drain of MOS tube M7, the drain of MOS tube M7 is connected to the gate of MOS tube M7, the gate of MOS tube M7 is connected to the gate of MOS tube M8, the drain of MOS tube M8 is connected to the gate of power tube M P The gate of MOS tube M7 is connected to the source of MOS tube M8, the gate of MOS tube M3 is connected to the gate of MOS tube M1, the source of MOS tube M3 is grounded, the drain of MOS tube M3 is connected to the drain of MOS tube M5, the drain of MOS tube M5 is short-circuited to the gate of MOS tube M5, the gate of MOS tube M5 is connected to the gate of MOS tube M6, the drain of MOS tube M6 is connected to the drain of MOS tube M7, and the source of MOS tube M5 is connected to the source of MOS tube M6. The input voltage V IN ;
[0034] The gate of MOS transistor M23 is connected to the gate of M19, the source of MOS transistor M23 is grounded, and the drain of MOS transistor M23 is connected to the output end of current source I2; the drain of MOS transistor M2 is short-circuited to the gate of MOS transistor M2, the drain of MOS transistor M2 is connected to the output end of current source I2, the source of MOS transistor M2 is grounded, the gate of MOS transistor M41 is connected to the gate of MOS transistor M2, the source of MOS transistor M41 is grounded, the drain of MOS transistor M41 is connected to the drain of MOS transistor M12, the gate of MOS transistor M12 is connected to the current comparison module, the source of MOS transistor M12 is connected to the drain of MOS transistor M15, the drain of MOS transistor M15 is short-circuited to the gate of MOS transistor M15, the gate of MOS transistor M15 is connected to the gate of MOS transistor M16, and the source of MOS transistor M15 is connected to the source of MOS transistor M16. The input voltage V IN The drain of the MOS tube M16 is connected to the drain of the MOS tube M7, the gate of the MOS tube M4 is connected to the gate of the MOS tube M2, the source of the MOS tube M4 is grounded, and the drain of the MOS tube M4 is connected to the drain of the MOS tube M5.
[0035] like Figure 2 As shown, in some embodiments, MOS transistor M5, MOS transistor M6, MOS transistor M11, MOS transistor M12, MOS transistor M13, MOS transistor M14, MOS transistor M15 and MOS transistor M16 are PMOS transistors; MOS transistor M1, MOS transistor M2, MOS transistor M3, MOS transistor M4, MOS transistor M7, MOS transistor M8, MOS transistor M19, MOS transistor M20, MOS transistor M21, MOS transistor M22, MOS transistor M23, MOS transistor M31 and MOS transistor M41 are NMOS transistors.
[0036] Under normal input voltage and output voltage, when a large transient heavy load current appears in the output load of the LDO, the output capacitor of the LDO first provides current to the output load, and then the output voltage begins to drop. However, due to the influence of resistor R1 and capacitor C1, the voltage at point B decreases later than the voltage at point A. At this time, the voltage difference between A and B will cause the output current I1 of the comparator VNin output regulating current source I1 and the output current I2 of the comparator VPin regulating current source I2 to increase. When I1>I3, I2>I4, MOS tubes M1 and MOS tubes M2 begin to flow current, and the mirror current flows through MOS tubes M3 and MOS tubes M4, and the mirror current is amplified, and the gate voltage GATE is pulled down through MOS tube M8, thereby increasing the power of power tube M1. P Transient overcurrent capability to reduce output undershoot.
[0037] When the input voltage and the output voltage are both relatively low, and the voltage difference is close to a NMOS conduction threshold, a large transient overload current appears in the output load of the LDO, the current I1 decreases, the mirror current of MOS M3 decreases, the change of the part of the mirror current of MOS M4 flowing through I2 is small, at this time, MOS M12 is turned on, the current I2 is mirrored through MOS M41, I6 is generated to compensate for the decrease of I1, so that the transient current flowing through MOS M8 changes little, and the output undershoot can be reduced during the load transient;
[0038] Conversely, when the input voltage and the output voltage are both relatively high, and the voltage difference is close to a PMOS conduction threshold, a large transient overload current appears in the output load of the LDO, the current I2 decreases, the mirror current of MOS M4 decreases, the change of the part of the mirror current of MOS M3 flowing through I1 is small, at this time, MOS M11 is turned on, the current I1 is mirrored through MOS M31, I5 is generated to compensate for the decrease of I2, so that the transient current flowing through MOS M8 changes little, and the output undershoot can be reduced during the load transient.
[0039] As shown in Figure 2 In some embodiments, the capacitive impedance circuit includes a resistor R ESR and a capacitor C LOAD The first end of the resistor R ESR is connected to the output voltage V OUT The second end of the resistor R ESR is connected to the first end of the capacitor C LOAD The second end of the capacitor C LOAD is grounded.
[0040] The above is only a preferred embodiment of the present application, and does not limit the technical scope of the present application, so any slight modification, equivalent change and modification of the above embodiment according to the technical essence of the present application still belongs to the scope of the technical scheme of the present application.
Claims
1. An output transient response control circuit, characterized in that: include: Error amplifier, power tube M P , capacitor impedance circuit, output current detection control circuit, output voltage detection control circuit and output undershoot detection control circuit; the non-inverting input terminal and the inverting input terminal of the error amplifier are respectively connected to the reference voltage V OUT_SET With the output voltage V OUT The output of the error amplifier is connected to the power tube M P The gate of the power tube M P The source connection input voltage V IN , the power tube M P The drain connection output voltage V OUT ; The capacitor impedance circuit is connected to the output voltage V OUT The input end of the output current detection control circuit is connected to the power tube M P The output terminal of the output current detection control circuit is connected to the current input terminal of the output undershoot detection control circuit, and the output current detection control circuit is used to detect the output current of the LDO circuit; the input terminal of the output voltage detection control circuit is connected to the output voltage V OUT The output end of the output voltage detection control circuit is connected to the voltage input end of the output undershoot detection control circuit, and the output voltage detection control circuit is used to detect the output voltage of the LDO circuit; the output end of the output undershoot detection control circuit is connected to the power tube M P The output undershoot detection control circuit is used to control the power tube M according to the changes of the output current and output voltage. P The gate voltage quickly discharges and turns on the power tube M P .
2. The output transient response control circuit according to claim 1, characterized in that: The output current detection control circuit includes: a power tube M D , MOS tube M9, MOS tube M10, MOS tube M17 and MOS tube M18; the power tube M D The gate of the power tube M P The gate connection of the power tube M D The source and input voltage V IN Connect the power tube M D The drain of the MOS transistor M9 is connected to the drain of the MOS transistor M9, the drain of the MOS transistor M9 is short-circuited with the gate of the MOS transistor M9, the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, the source of the MOS transistor M9 and the source of the MOS transistor M10 are grounded, the drain of the MOS transistor M10 is connected to the gate of the MOS transistor M17, the drain of the MOS transistor M17 is short-circuited with the gate of the MOS transistor M17, the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M18, the drain of the MOS transistor M18 is connected to the current input end of the output undershoot detection control circuit, and the source of the MOS transistor M17 and the source of the MOS transistor M18 are connected to the input voltage V IN .
3. The output transient response control circuit according to claim 2, characterized in that: The MOS transistor M17 and the MOS transistor M18 are PMOS transistors, and the MOS transistor M9 and the MOS transistor M10 are NMOS transistors.
4. The output transient response control circuit according to claim 1, wherein: The output voltage detection control circuit includes: a resistor R1 and a capacitor C1, a first end of the resistor R1 and an output voltage V OUT The second end of the resistor R1 is connected to the first end of the capacitor C1, and the second end of the capacitor is grounded, wherein the first end of the resistor R1 is connected to the first voltage input end of the output undershoot detection control circuit as a first detection point, and the second end of the resistor is connected to the second voltage input end of the output undershoot detection control circuit as a second detection point.
5. The output transient response control circuit according to claim 4, characterized in that: The output undershoot detection control circuit includes: a current source IREF, a comparator VNin, a comparator VPin, a current source I1, a current source I2, a current comparison module, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M19, a MOS transistor M20, a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M31 and a MOS transistor M41; The input terminal of the current source IREF is connected to the input voltage V IN The output end of the current source IREF is connected to the drain of the MOS transistor M19, the output end of the output current detection control circuit is connected to the drain of the MOS transistor M19, the drain of the MOS transistor M19 is short-circuited with the gate of the MOS transistor M19, and the source of the MOS transistor M19 is grounded; The inverting input terminal of the comparator VNin is connected to the first end of the resistor R1, the non-inverting input terminal of the comparator VNin is connected to the second end of the resistor R1, and the positive side power supply terminal of the comparator VNin is connected to the input voltage V IN The negative power supply terminal of the comparator VNin is grounded, the drain of the MOS tube M20 is the bias current input terminal connected to the comparator VNin, the gate of the M20 is connected to the gate of the M19, the source of the M20 is grounded, and the output terminal of the comparator VNin is connected to the input terminal of the current source I1; the inverting input terminal of the comparator VPin is connected to the first terminal of the resistor R1, the non-inverting input terminal of the comparator VPin is connected to the second terminal of the resistor R1, and the positive power supply terminal of the comparator VPin is connected to the input voltage V IN The negative power supply terminal of the comparator VPin is grounded, the drain of the MOS tube M21 is the bias current input terminal connected to the comparator VPin, the gate of the M21 is connected to the gate of the M19, the source of the M21 is grounded, and the output terminal of the comparator VPin is connected to the input terminal of the current source I2; The gate of the MOS transistor M22 is connected to the gate of M19, the source of the MOS transistor M22 is grounded, and the drain of the MOS transistor M22 is connected to the output end of the current source I1; the drain of the MOS transistor M1 is short-circuited with the gate of the MOS transistor M1, the drain of the MOS transistor M1 is connected to the output end of the current source I1, the source of the MOS transistor M1 is grounded, the gate of the MOS transistor M31 is connected to the gate of the MOS transistor M1, the source of the MOS transistor M31 is grounded, the drain of the MOS transistor M31 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the current comparison module, the source of the MOS transistor M11 is connected to the drain of the MOS transistor M13, the drain of the MOS transistor M13 is short-circuited with the gate of the MOS transistor M13, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M14, and the source of the MOS transistor M13 is connected to the source of the MOS transistor M14 to the input voltage V IN The drain of the MOS tube M14 is connected to the drain of the MOS tube M7, the drain of the MOS tube M7 is connected to the gate of the MOS tube M7, the gate of the MOS tube M7 is connected to the gate of the MOS tube M8, the drain of the MOS tube M8 is connected to the gate of the power tube M P The gate of the MOS tube M7 is connected to the source of the MOS tube M8, the gate of the MOS tube M3 is connected to the gate of the MOS tube M1, the source of the MOS tube M3 is grounded, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M5 is short-circuited with the gate of the MOS tube M5, the gate of the MOS tube M5 is connected to the gate of the MOS tube M6, the drain of the MOS tube M6 is connected to the drain of the MOS tube M7, and the source of the MOS tube M5 is connected to the source of the MOS tube M6. The input voltage V IN ; The gate of the MOS transistor M23 is connected to the gate of M19, the source of the MOS transistor M23 is grounded, and the drain of the MOS transistor M23 is connected to the output end of the current source I2; the drain of the MOS transistor M2 is short-circuited with the gate of the MOS transistor M2, the drain of the MOS transistor M2 is connected to the output end of the current source I2, the source of the MOS transistor M2 is grounded, the gate of the MOS transistor M41 is connected to the gate of the MOS transistor M2, the source of the MOS transistor M41 is grounded, the drain of the MOS transistor M41 is connected to the drain of the MOS transistor M12, the gate of the MOS transistor M12 is connected to the current comparison module, the source of the MOS transistor M12 is connected to the drain of the MOS transistor M15, the drain of the MOS transistor M15 is short-circuited with the gate of the MOS transistor M15, the gate of the MOS transistor M15 is connected to the gate of the MOS transistor M16, and the source of the MOS transistor M15 is connected to the source of the MOS transistor M16. The input voltage V IN The drain of the MOS transistor M16 is connected to the drain of the MOS transistor M7, the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5.
6. The output transient response control circuit according to claim 5, characterized in that: The MOS transistor M5, the MOS transistor M6, the MOS transistor M11, the MOS transistor M12, the MOS transistor M13, the MOS transistor M14, the MOS transistor M15 and the MOS transistor M16 are PMOS transistors; the MOS transistor M1, the MOS transistor M2, the MOS transistor M3, the MOS transistor M4, the MOS transistor M7, the MOS transistor M8, the MOS transistor M19, the MOS transistor M20, the MOS transistor M21, the MOS transistor M22, the MOS transistor M23, the MOS transistor M31 and the MOS transistor M41 are NMOS transistors.
7. The output transient response control circuit according to claim 1, wherein: The capacitive impedance circuit includes a resistor R ESR With capacitor C LOAD , the resistor R ESR The first end is connected to the output voltage V OUT , the resistor R ESR The second end of the capacitor C LOAD The first end of the capacitor C LOAD The second end is grounded.