Chip packaging structure

Abstract

The chip packaging structure disclosed by the utility model comprises a double-chip unit, a glass substrate and a packaging body, the double-chip unit is formed by cutting two bare chips as a unit during cutting; the double-chip unit is arranged on the glass substrate; and the packaging body and the glass substrate are matched to form a sealing cavity for accommodating the double-chip unit. Two bare chips are cut as a unit to form a double-chip unit during cutting, so that no gap exists between the two bare chips in the double-chip unit, and the problem that miniaturization packaging cannot be achieved due to the fact that gaps exist between the bare chips due to the fact that the two bare chips need to be mounted separately in the prior art is solved; meanwhile, the glass substrate is used as a supporting plate, and the mechanical property of high flatness of the glass substrate is used for bearing, so that the warping problem and the stability problem of the double-bare-chip unit are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit packaging technical field, in particular to chip packaging structure. BACKGROUND

[0002] In the existing chip packaging structure, because the conventional substrate bearing capacity is poor, two bare chips are separately attached, so that the interval between the two bare chips cannot be completely eliminated, resulting in that the substrate area required by double-chip packaging is large. With the development of the storage chip industry, the demand for miniaturized chips is increasing, so that the existing double-chip packaging is difficult to meet the demand of miniaturized chips. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide a chip packaging structure to realize miniaturized double-chip unit packaging.

[0004] In order to solve the above technical problem, the utility model adopts the technical scheme that:

[0005] The chip packaging structure comprises a double-chip unit, a glass substrate and a packaging body; the double-chip unit is formed by cutting two bare chips as one unit when cutting; the double-chip unit is arranged on the glass substrate; and the packaging body and the glass substrate cooperate to form a sealed cavity accommodating the double-chip unit.

[0006] Further, the packaging body comprises a glass cover.

[0007] Further, the outer side of the glass substrate is provided with a first connecting part; the outer side of the packaging body is provided with a second connecting part; and the packaging body is connected with the first connecting part of the glass substrate through the second connecting part.

[0008] Further, the first connecting part comprises a convex step surface close to the sealed cavity and a first inclined surface connected with the convex step surface; the second connecting part comprises a concave step surface matched with the convex step surface and a second inclined surface matched with the first inclined surface; the convex step surface and the concave step surface are adhesively connected, and the first inclined surface and the second inclined surface are adhesively connected.

[0009] Further, the glass substrate is provided with a conductive channel; and the double-chip unit is connected with the conductive channel.

[0010] Further, the glass substrate comprises at least two glass layers; each glass layer is provided with the conductive channel; the glass layers are stacked, the conductive channels between adjacent glass layers are correspondingly connected to lay wires; and the double-chip unit is arranged on the glass layer of the top layer.

[0011] Furthermore, a conductive filler and a solder joint are provided in the conductive channel, the dual-chip unit is provided with a solder pad, and the conductive filler is electrically connected to the solder pad through the solder joint.

[0012] Furthermore, the size of the bottom glass layer is larger than the size of the upper glass layer.

[0013] Furthermore, it also includes solder balls; the solder balls are arranged on a side of the glass substrate away from the double-chip unit, and the solder balls are connected to the conductive channels.

[0014] Furthermore, the sealed cavity is filled with an inert gas; and / or a sealant is provided at the edge where the double-chip unit and the glass substrate are bonded.

[0015] The beneficial effects of the present invention are as follows: by cutting two bare chips into a unit to form a dual-chip unit, there is no gap between the two bare chips in the dual-chip unit, thereby solving the problem that the two bare chips need to be mounted separately, resulting in a gap between the bare chips and the inability to achieve miniaturized packaging; at the same time, a glass substrate is used as a supporting plate, and the glass substrate has the mechanical property of high flatness for bearing, thereby solving the warping problem and stability problem of the dual-bare-chip unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a cross-sectional view of a chip packaging structure in an embodiment of the present invention;

[0017] Figure 2 A top view of the chip packaging structure in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the mounting of the chip packaging structure in an embodiment of the present utility model;

[0019] Figure 4 This is a schematic diagram of the welding of the chip packaging structure in the embodiment of the present utility model;

[0020] Figure 5 for Figure 1 An enlarged view of the structure marked as part A;

[0021] Figure 6 for Figure 1 An enlarged view of the structure marked as part B.

[0022] Description of labels:

[0023] 1, dual-chip unit; 11, pad; 2, glass substrate; 21, conductive channel; 22, conductive filler; 23, solder joint; 24, first connecting part; 241, convex step surface; 242, first inclined surface; 3, package; 31, second connecting part; 311, concave step surface; 312, second inclined surface; 4, solder ball; 5, sealant. DETAILED DESCRIPTION

[0024] To make the technical contents, purposes and effects of the present application clear, the following will be described in combination with embodiments and the accompanying drawings.

[0025] In the production process of existing storage chips, due to the poor flatness and the limitation of wire bonding, the wafer is usually cut into single-die chips, and then the chips are mounted and wire-bonded. Therefore, when dual-chip packaging is performed, two die chips need to be mounted separately, which makes the distance between the die chips not completely eliminated, resulting in a large area of the substrate required for dual-chip packaging, which cannot meet the demand of miniaturized chips. In view of the above technical problems, the present application provides a chip packaging structure, which is specifically as follows:

[0026] The chip packaging structure comprises a dual-chip unit, a glass substrate and a package. The dual-chip unit is formed by cutting two die chips as one unit during cutting. The dual-chip unit is arranged on the glass substrate. The package and the glass substrate cooperate to form a sealed cavity accommodating the dual-chip unit.

[0027] As can be seen from the above description, the present application has the following beneficial effects: by cutting two die chips as one unit during cutting to form a dual-chip unit, there is no gap between the two die chips in the dual-chip unit, thereby solving the problem that the existing two die chips need to be mounted separately, resulting in a gap between the die chips, and the problem that miniaturized packaging cannot be achieved. At the same time, the glass substrate is used as a support plate, and the glass substrate is used to bear due to its high flatness mechanical properties, thereby solving the warping problem and stability problem of the dual-die chip unit.

[0028] Further, the package comprises a glass cover.

[0029] As can be seen from the above description, the glass cover is used as the package instead of the traditional plastic packaging, and the package does not need to use a mold and melt plastic packaging material for packaging, so that the package does not need to be packaged in a high-temperature environment, but only needs to be packaged in a nitrogen or inert gas environment. The heat dissipation effect of the glass cover is higher than that of plastic packaging, which can improve the heat dissipation performance of the structure. At the same time, the package and the substrate are both glass, and their coefficients of thermal expansion are close. Compared with the traditional chip packaging structure in which the package and the substrate are made of different materials, the material with close coefficients of thermal expansion is less likely to warp during temperature change, thereby improving the stability of the structure.

[0030] Further, the outer side of the glass substrate is provided with a first connecting part; the outer side of the package is provided with a second connecting part; the package is connected with the first connecting part of the glass substrate through the second connecting part.

[0031] From the above description, by providing a first connecting part on the glass substrate and a second connecting part on the package, and adapting the connection through the first connecting part and the second connecting part, the sealing property of the structure can be improved.

[0032] Further, the first connecting part comprises a convex step surface close to the sealing cavity and a first inclined surface connected with the convex step surface; the second connecting part comprises a concave step surface matched with the convex step surface and a second inclined surface matched with the first inclined surface; the convex step surface and the concave step surface are adhesively connected, and the first inclined surface and the second inclined surface are adhesively connected.

[0033] From the above description, by adopting the design of step surface matching, the convex step surface and the first inclined surface are provided on the glass substrate as the first connecting part, and the concave step surface matched with the convex step surface and the second inclined surface are provided on the package as the second connecting part, which avoids the problem that the inclined surface is easy to slide, not only can better fix and seal the package, but also makes the overall thickness of the package structure thinner.

[0034] Further, the glass substrate is provided with a conductive channel; the double-chip unit is connected with the conductive channel.

[0035] From the above description, by providing the conductive channel in the glass substrate and connecting the double-chip unit with the conductive channel, the signal of the double-chip unit can be led out to realize the connection with other circuits.

[0036] Further, the glass substrate comprises at least two glass layers; each of the glass layers is provided with the conductive channel; the glass layers are stacked, and the conductive channels between adjacent glass layers are correspondingly connected for wiring; the double-chip unit is arranged on the glass layer of the top layer.

[0037] From the above description, by composing the glass substrate with multiple glass layers, wiring can be performed on different glass layers to better assist the function of the double-chip unit.

[0038] Further, the conductive channel is provided with a conductive filler and a solder point, and the double-chip unit is provided with a solder pad; the conductive filler is electrically connected with the solder pad through the solder point.

[0039] From the above description, by providing the conductive filler and the solder point in the conductive channel, the signal of the chip can be led out through the solder point and the conductive channel.

[0040] Further, the size of the bottom glass layer is greater than the size of the upper glass layer.

[0041] As described above, the size of the bottom glass layer is set to be greater than the size of the upper glass layer, which is beneficial to set the first connecting part on the outer side of the bottom glass layer.

[0042] Further, the solder ball is arranged on the side of the glass substrate away from the dual-chip unit, and the solder ball is connected with the conductive channel.

[0043] As described above, the solder ball is arranged on the side of the glass substrate away from the dual-chip unit, so that the packaging structure can be more conveniently connected with the external structure such as a circuit substrate through the solder ball.

[0044] Further, the sealing cavity is filled with inert gas, and / or a sealant is arranged at the edge where the dual-chip unit is attached to the glass substrate.

[0045] As described above, the sealing cavity is filled with inert gas, and a sealant is arranged at the edge where the dual-chip unit is attached to the glass substrate, so as to improve the sealing performance between the dual-chip unit and the glass substrate.

[0046] The chip packaging structure provided by the utility model can be applied to the scene of dual-chip packaging, and the following is described through a specific embodiment.

[0047] Embodiment one

[0048] Please refer to Figure 1 and Figure 2 The chip packaging structure comprises a dual-chip unit 1, a glass substrate 2 and a packaging body 3; the dual-chip unit 1 is formed by cutting two bare chips as one unit when cutting, that is, when cutting a wafer, the two bare chips are not divided into single bare chips, but are divided into one unit; the dual-chip unit 1 is arranged on the glass substrate 2; the packaging body 3 is arranged on the side of the glass substrate 2 provided with the dual-chip unit 1, and the packaging body 3 seals the dual-chip unit 1, that is, the packaging body 3 and the glass substrate 2 cooperate to form a sealing cavity accommodating the dual-chip unit 1; as shown in Figure 1 and Figure 2 The length and width of the packaging body 3 are the same as the length and width of the glass substrate 2. The packaging body 3 comprises a glass cover; the glass cover replaces the traditional plastic package, and the packaging does not need to be performed by the way of melting plastic sealing material.

[0049] Please refer to Figure 2, the chip packaging structure further comprises solder balls 4, and the glass substrate 2 is provided with conductive channels 21; the dual-chip unit 1 is connected with the conductive channels 21; the solder balls 4 are arranged on the side of the glass substrate 2 away from the dual-chip unit 1, and the solder balls 4 are connected with the conductive channels 21.

[0050] In an optional embodiment, the glass substrate 2 comprises at least two glass layers; each of the glass layers is provided with the conductive channels 21, and the conductive channels 21 are realized based on a TSV (Through Glass Via) process; the glass layers are stacked, and the conductive channels 21 between adjacent glass layers are connected for wiring; the dual-chip unit 1 is arranged on the glass layer at the top; and the solder balls 4 are connected with the glass layer at the bottom. As shown in Figure 1 , the chip packaging structure comprises three glass layers in total, the adjacent glass layers are re-wired based on TGV, so as to connect the signals of the dual-chip unit 1 to the solder balls 4 at the bottom; and the size of the glass layer at the bottom is greater than that of the glass layer at the top.

[0051] Please refer to Figure 3 and Figure 4 , the conductive channels 21 are provided with conductive fillers 22 and solder joints 23; the dual-chip unit 1 is provided with pads 11, and the conductive fillers 22 are electrically connected with the pads 11 through the solder joints 23.

[0052] Please refer to Figure 5 and Figure 6 , the outer side of the glass substrate 2 is provided with a first connecting part 24; the outer side of the package 3 is provided with a second connecting part 31; and the package 3 is connected with the first connecting part 24 of the glass substrate 2 through the second connecting part 31. In an optional embodiment, the first connecting part 24 comprises a convex step surface 241 close to the sealing cavity and a first inclined surface 242 connected with the convex step surface 241; the second connecting part 31 comprises a concave step surface 311 matched with the convex step surface 241 and a second inclined surface 312 matched with the first inclined surface 242; the convex step surface 241 and the concave step surface 311 are adhesively connected, and the first inclined surface 242 and the second inclined surface 312 are adhesively connected. Meanwhile, there is a gap between the package 3 and the dual-chip unit 1; the sealing cavity is filled with inert gas; and the dual-chip unit 1 is provided with a sealant 5 at the edge adhered to the glass substrate 2.

[0053] The packaging steps of the above chip packaging structure are as follows:

[0054] A, wafer cutting adopts a hidden cutting process, and the bare chips are cut into several dual-chip units 1 two by two as a group.

[0055] B, electrical connection is made in the glass substrate 2 by TGV (TGV-Through Glass Via: Through Glass Vertical Interconnect Technology, which creates a tiny vertical channel or hole on the glass substrate for electrical connection, achieving electrical connection between multiple layers of glass without using traditional metal wires); wherein the glass layer of the top layer in the glass substrate 2 is used to preliminarily lead out the pad 11 signal on the double-chip unit 1 through the soldering point 23 and TGV; then other glass layers in the glass substrate 2 are rerouted through TGV to connect the signal to the soldering ball 4 at the bottom.

[0056] C1, a conical soldering point is reserved in the conductive channel 21 on the top of the glass substrate 2 after TGV is completed, the double-chip unit 1 is pasted downward on the glass substrate 2, and the pad 11 of the double-chip unit 1 is aligned with the soldering point 23 reserved on the glass substrate 2, as shown in Figure 3 ; then reflow soldering is performed, the conical soldering point 23 is gradually melted and collapsed by heat, and the excess solder flows into the glass hole, while the flatness of the glass substrate 2 is maintained to facilitate the control of the warping of the double-chip unit 1, as shown in Figure 4 .

[0057] Or in another alternative embodiment, step C2 is used instead of step C1, specifically:

[0058] C2, the pad 11 of the double-chip unit 1 is pasted upward on the glass substrate 2, and the pad 11 of the double-chip unit 1 is electrically interconnected with the glass substrate 2 through TGV technology.

[0059] D, the glass substrate 2 after pasting is encapsulated, which can be encapsulated by plastic packaging or glass cover packaging; wherein the glass cover packaging is airtight packaging, which is more resistant to water vapor and other erosions and has higher reliability than non-airtight plastic packaging.

[0060] E, finally, ball planting is performed at the bottom of the glass substrate 2 to form a final double-chip unit glass substrate package.

[0061] In summary, the chip packaging structure provided by the utility model divides two bare chips into a double-chip unit, minimizes the area occupied by the double bare chips, and uses the high flatness and other excellent mechanical properties of the glass substrate for bearing, thereby solving the warping and stability problems of the double bare chip unit; the innovative interconnection method saves gold wires compared with traditional wire bonding, reduces the space occupied by wire bonding, breaks through the technical bottleneck that wire bonding must be cut into a single bare chip, and thus realizes the super-small and super-thin double-chip unit glass substrate package.

[0062] The above merely illustrates the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent transformation or direct or indirect application in the related technical field based on the content of the present application specification and drawings is also included in the patent protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: including a double chip unit, a glass substrate and a package; The double chip unit is formed by cutting two bare chips into one unit during cutting; The dual-chip unit is disposed on the glass substrate; The package body and the glass substrate cooperate to form a sealed cavity for accommodating the dual-chip unit.

2. The chip packaging structure according to claim 1, wherein: The package body includes a glass cover.

3. The chip packaging structure according to claim 1, wherein: A first connecting portion is provided on the outer side of the glass substrate; A second connecting portion is provided on the outer side of the package body; The package body is connected to the first connection portion of the glass substrate through the second connection portion.

4. The chip packaging structure according to claim 3, wherein: The first connecting portion includes a convex step surface close to the sealing cavity and a first inclined surface connected to the convex step surface; The second connecting portion includes a concave step surface matched with the convex step surface and a second inclined surface matched with the first inclined surface; The convex step surface is bonded to the concave step surface, and the first inclined surface is bonded to the second inclined surface.

5. The chip packaging structure according to claim 1, wherein: A conductive channel is provided in the glass substrate; The dual-chip unit is connected to the conductive path.

6. The chip packaging structure according to claim 5, characterized in that: The glass substrate includes at least two glass layers; The conductive channel is provided in each of the glass layers; The glass layers are stacked, and the conductive paths between adjacent glass layers are connected and wired accordingly; The double-chip unit is arranged on the top glass layer.

7. The chip packaging structure according to claim 6, wherein: Conductive fillers and solder joints are provided in the conductive channels, and the dual-chip unit is provided with solder pads. The conductive fillers are electrically connected to the solder pads through the solder joints.

8. The chip packaging structure according to claim 6, wherein: The size of the bottom glass layer is larger than that of the upper glass layer.

9. The chip packaging structure according to claim 7, wherein: Also includes solder balls; The solder ball is arranged on a side of the glass substrate away from the double-chip unit, and the solder ball is connected to the conductive path.

10. The chip packaging structure according to claim 1, wherein: The sealed cavity is filled with an inert gas; and / or A sealant is provided at the edge where the double chip unit is attached to the glass substrate.

Images