Package structure
Through the stacking bonding of chip components and the electrical connection of the conductive hole redistribution layer, the problem of insufficient space in the multi-chip module packaging structure is solved, and a higher density packaging structure design is achieved.
Patent Information
- Application Number
- CN202422526391.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-10-18
AI Technical Summary
In existing multi-chip module packaging structures, multiple chips are laid out in a single layer, resulting in insufficient space for miniaturization of the packaging structure.
The chip assembly is stacked and bonded, and the first chip and the second chip are stacked and bonded, encapsulated in the first packaging layer, and electrically connected using conductive holes and redistribution layers to form a multi-layer structure, thereby increasing chip density without increasing packaging thickness.
Without increasing the thickness of the packaging structure, more chips can be packaged to improve the density and miniaturization of the packaging structure.
Smart Images
Figure CN223450899U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a packaging structure. BACKGROUND
[0002] In recent years, terminal consumer electronics products are designed to be light, thin, short and small, which leads to the development of chip packaging in the direction of thinness and high density. The packaging structure of multi-chip module (MCM) is widely used in electronic devices. The packaging structure of multi-chip module mainly includes two or more chips to improve the electrical properties and performance of the packaging structure of multi-chip module. However, the multiple chips in the packaging structure of multi-chip module are currently arranged in the form of single-layer chips in the packaging structure of multi-chip module, and the space of the packaging structure of multi-chip module is less miniaturizable. CONTENT OF THE UTILITY MODEL
[0003] The purpose of the present application is to provide a packaging structure which can solve the technical problem that multiple chips are arranged in the form of single-layer chips in the packaging structure of multi-chip module, and the space of the packaging structure of multi-chip module is less miniaturizable.
[0004] In order to solve the above problems, the present application provides a packaging structure, the packaging structure has a first direction and a second direction intersecting with each other, and the packaging structure comprises: a chip assembly comprising a first chip and a second chip stacked along the first direction, the first chip comprising a first main body portion and a first conductive portion disposed on a side of the first main body portion close to the second chip, the second chip comprising a second main body portion and a second conductive portion disposed on a side of the second main body portion close to the first chip, the first conductive portion and the second conductive portion being bonded to each other; a first packaging layer covering a side of the first main body portion close to the second main body portion and two sides of the first main body portion in the second direction; a first substrate disposed on a side of the first packaging layer away from the first main body portion, the packaging structure having a first conductive hole penetrating through the first substrate and the first packaging layer along the first direction; a first redistribution layer disposed in the first conductive hole and on a side of the first substrate away from the first packaging layer, the first redistribution layer being electrically connected to the first conductive portion; and a solder ball disposed on a side of the first redistribution layer away from the first substrate, the solder ball being electrically connected to the first redistribution layer.
[0005] In some embodiments, the surface of the side of the first packaging layer away from the first substrate is flush with the surface of the side of the first main body portion away from the first substrate.
[0006] In some embodiments, an end of the first conductive hole close to the first main body portion abuts against the surface of the side of the first conductive portion away from the first main body portion.
[0007] In some embodiments, the first conductive via is formed through the first substrate and the first encapsulation layer in the first direction by a laser process.
[0008] In some embodiments, the package structure further comprises at least one sub-package structure disposed between the first redistribution layer and the solder ball; each sub-package structure comprises a sub-encapsulation layer disposed on a side of the first substrate distal to the first encapsulation layer, the sub-encapsulation layer covering the first redistribution layer; a sub-substrate disposed on a side of the sub-encapsulation layer distal to the first substrate, the sub-package structure having a first sub-conductive via penetrating through the sub-substrate and the sub-encapsulation layer in the first direction; a sub-redistribution layer disposed in the first sub-conductive via and on a side of the sub-substrate distal to the first substrate; wherein the sub-redistribution layer farthest to the first substrate is electrically connected to the solder ball, and the sub-redistribution layer closest to the first substrate is electrically connected to the first redistribution layer.
[0009] In some embodiments, the package structure comprises three sub-package structures, the three sub-package structures being a first sub-package structure, a second sub-package structure, and a third sub-package structure in turn distal to the first substrate in the first direction; an end of the first sub-conductive via of the first sub-package structure proximal to the first substrate abuts a surface of a side of the first redistribution layer distal to the first substrate; an end of the first sub-conductive via of the second sub-package structure proximal to the first substrate abuts a surface of a side of the sub-redistribution layer of the first sub-package structure distal to the first substrate; an end of the first sub-conductive via of the third sub-package structure proximal to the first substrate abuts a surface of a side of the sub-redistribution layer of the second sub-package structure distal to the first substrate; and the solder ball is electrically connected to the sub-redistribution layer of the third sub-package structure.
[0010] In some embodiments, at least one sub-package structure is provided with a chip assembly.
[0011] In some embodiments, the sub-package structure provided with the chip assembly has a second sub-conductive via penetrating through the sub-substrate and the sub-encapsulation layer in the first direction, and the sub-redistribution layer is further disposed in the second sub-conductive via, and the sub-redistribution layer is further electrically connected to a first conductive part of the chip assembly in the sub-package structure.
[0012] In some embodiments, in the sub-package structure provided with the chip assembly, an end of the second sub-conductive via proximal to the first conductive part abuts a surface of a side of the first conductive part distal to the first main body part.
[0013] In some embodiments, the first conductive part and the second conductive part are bonded to each other by one of thermal compression bonding, ultrasonic bonding, laser bonding, conductive adhesive bonding, and micro bonding.
[0014] The chip assembly of the packaging structure of the application comprises a first chip and a second chip stacked in a first direction, and a first main body part of the first chip and a second conductive part of the second chip are bonded to each other; after the chip assembly is formed by stacking and bonding the first chip and the second chip, the chip assembly is encapsulated in a first packaging layer, and the first packaging layer is used to cover the chip assembly, so that more chips can be encapsulated without affecting the thickness of the first packaging layer, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is realized. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.
[0016] Figure 1 is a schematic view of the packaging structure of the embodiment 1 of the application;
[0017] Figure 2 is a schematic view of the chip assembly of the embodiment 1 of the application;
[0018] Figure 3 is a schematic view of the packaging structure of the embodiment 2 of the application;
[0019] Figure 4 is a schematic view of the packaging structure of the embodiment 3 of the application;
[0020] Figure 5 is a schematic view of the packaging structure of the embodiment 4 of the application;
[0021] Figure 6 is a schematic view of the packaging structure of the embodiment 5 of the application.
[0022] Explanation of reference signs:
[0023] 1, chip assembly; 2, first packaging layer; 3, first substrate; 4, first conductive hole; 5, first redistribution layer; 6, solder ball; 7, sub-packaging structure;
[0024] 110, first chip; 111, first main body part; 112, first conductive part;
[0025] 120, second chip; 121, second main body part; 122, second conductive part;
[0026] 710, sub-packaging layer; 720, sub-substrate; 730, first sub-conductive hole; 740, sub-redistribution layer; 750, second sub-conductive hole; 701, first sub-packaging structure; 702, second sub-packaging structure; 703, third sub-packaging structure. DETAILED DESCRIPTION
[0027] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings, in order to provide a person skilled in the art with a complete understanding of the technical content of the present application, to demonstrate that the present application can be implemented by way of example, to make the technical content disclosed by the present application more clear, and to make it easier for a person skilled in the art to understand how to implement the present application. However, the scope of protection of the present application is not limited to the embodiments described herein, and the description of the embodiments below is not intended to limit the scope of the present application.
[0028] The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "lateral", etc., are only the directions in the drawings, and the directional terms used herein are used to explain and describe the present application, but are not used to limit the scope of protection of the present application.
[0029] In the drawings, the same components have the same reference numerals, and components having similar structures or functions are denoted by similar reference numerals. In addition, in order to facilitate understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present application does not limit the size and thickness of each component.
[0030] Embodiment 1
[0031] Referring to Figure 1 , Figure 1 is a schematic view of a packaging structure according to an embodiment of the present application. The packaging structure has a first direction M and a second direction N intersecting each other. In the present embodiment, the first direction M and the second direction N are perpendicular to each other, but in other embodiments, the first direction M and the second direction N can also be non-perpendicular.
[0032] Referring to Figure 1 , the packaging structure includes a chip assembly 1, a first packaging layer 2, a first substrate 3, a first conductive hole 4, a first redistribution layer 5, and a solder ball 6.
[0033] Referring to Figure 1 and Figure 2 , Figure 2 is a schematic view of a chip assembly according to Embodiment 1 of the present application. The chip assembly 1 includes a first chip 110 and a second chip 120 stacked along a first direction M. In the present embodiment, the second chip 120 is located above the first chip 110. In other embodiments, the first chip 110 can also be disposed above the second chip 120.
[0034] The first chip 110 includes a first main body portion 111 and a first conductive portion 112 disposed on a side of the first main body portion 111 close to the second chip 120.
[0035] The second chip 120 includes a second main body part 121 and a second conductive part 122 disposed on a side of the second main body part 121 close to the first chip 110. The first conductive part 112 and the second conductive part 122 are bonded to each other. In some embodiments, the first conductive part 112 and the second conductive part 122 can be bonded by one of thermal compression bonding, ultrasonic bonding, laser bonding, conductive adhesive bonding, and micro bonding.
[0036] Referring to Figure 1 In the embodiment, the first encapsulation layer 2 covers a side of the first main body part 111 close to the second main body part 121 and two sides of the first main body part 111 in the second direction N. A surface of the side of the first encapsulation layer 2 away from the first substrate 3 is flush with a surface of the side of the first main body part 111 away from the first substrate 3. In other embodiments, the first encapsulation layer 2 covers not only the side of the first main body part 111 close to the second main body part 121, but also the side of the first main body part 111 close to the second main body part 121 and the two sides of the first main body part 111 in the second direction N, and also covers a side of the first main body part 111 away from the second main body part 121.
[0037] Referring to Figure 1 The first substrate 3 is disposed on the side of the first encapsulation layer 2 away from the first main body part 111. In the embodiment, the material of the first substrate 3 is polyimide (PI).
[0038] Referring to Figure 1 The first conductive hole 4 penetrates the first substrate 3 and the first encapsulation layer 2 along the first direction M. In some embodiments, an end of the first conductive hole 4 close to the first main body part 111 abuts against a surface of the side of the first conductive part 112 away from the first main body part 111. Thus, the first redistribution layer 5 in the first conductive hole 4 is electrically connected to the first conductive part 112. In some embodiments, the first substrate 3 and the first encapsulation layer 2 are patterned by a laser process to form the first conductive hole 4 penetrating the first substrate 3 and the first encapsulation layer 2 along the first direction M.
[0039] Referring to Figure 1 The first redistribution layer 5 is disposed in the first conductive hole 4 and on the side of the first substrate 3 away from the first encapsulation layer 2, and the first redistribution layer 5 is electrically connected to the first conductive part 112. In other words, the first redistribution layer 5 in the first conductive hole 4 and the first redistribution layer 5 on the side of the first substrate 3 away from the first encapsulation layer 2 are integrally formed in the embodiment. In other embodiments, the first redistribution layer 5 in the first conductive hole 4 can be prepared first, and then the first redistribution layer 5 on the side of the first substrate 3 away from the first encapsulation layer 2 can be prepared according to actual needs.
[0040] Referring to Figure 1The soldering ball 6 is arranged on the side of the first redistribution layer 5 away from the first substrate 3, and is electrically connected to the first redistribution layer 5. In this embodiment, the end of the soldering ball 6 close to the first substrate 3 abuts against the surface of the side of the first redistribution layer 5 away from the first substrate 3.
[0041] Through the above scheme, the first chip 110 and the second chip 120 are laminated and bonded to form the chip assembly 1, which is then encapsulated in the first packaging layer 2, so that more chips can be packaged without affecting the thickness of the packaging structure, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is realized.
[0042] Embodiment 2
[0043] Please refer to Figure 3 , Figure 3 is a schematic diagram of the packaging structure of Embodiment 2 of the present application. This embodiment includes most of the technical features of Embodiment 1. The difference between this embodiment and Embodiment 1 is that the packaging structure of this embodiment further includes a sub-packaging structure 7. The sub-packaging structure 7 is arranged between the first redistribution layer 5 and the soldering ball 6. The sub-packaging structure 7 includes a sub-packaging layer 710, a sub-substrate 720, a first sub-conductive hole 730, and a sub-redistribution layer 740.
[0044] Please refer to Figure 3 , the sub-packaging layer 710 is arranged on the side of the first substrate 3 away from the first packaging layer 2. The sub-packaging layer 710 covers the first redistribution layer 5.
[0045] Please refer to Figure 3 , the sub-substrate 720 is arranged on the side of the sub-packaging layer 710 away from the first substrate 3. In this embodiment, the material of the sub-substrate 720 is polyimide (PI).
[0046] Please refer to Figure 3 , the first sub-conductive hole 730 penetrates the sub-substrate 720 and the sub-packaging layer 710 along the first direction M. In this embodiment, the end of the first sub-conductive hole 730 close to the first substrate 3 abuts against the surface of the side of the first redistribution layer 5 away from the first substrate 3.
[0047] Please refer to Figure 3 , the sub-redistribution layer 740 is arranged in the first sub-conductive hole 730 and on the side of the sub-substrate 720 away from the first substrate 3. In this embodiment, one end of the sub-redistribution layer 740 is electrically connected to the soldering ball 6, and the other end is electrically connected to the first redistribution layer 5.
[0048] Through the above scheme, the first chip 110 and the second chip 120 are laminated and bonded to form the chip assembly 1, and then the chip assembly 1 is packaged in the first packaging layer 2, so that more chips can be packaged without affecting the thickness of the packaging structure, the density of the packaging structure is improved, and the miniaturization of the packaging structure is realized.
[0049] Embodiment 3
[0050] Please refer to Figure 4 , Figure 4 is a schematic view of the packaging structure of embodiment 3 of the present application. This embodiment includes most of the technical features of embodiment 2. The difference between this embodiment and embodiment 2 is that the sub-packaging structure 7 in this embodiment further comprises a chip assembly 1.
[0051] The sub-packaging structure 7 of this embodiment has a second sub-conductive hole 750 penetrating the sub-substrate 720 and the sub-packaging layer 710 along the first direction M, and a sub-redistribution layer 740 is further arranged in the second sub-conductive hole 750. The sub-redistribution layer 740 is further electrically connected to the first conductive part 112 of the chip assembly 1 in the sub-packaging structure 7.
[0052] In the sub-packaging structure 7 of this embodiment, the chip assembly 1 is arranged on the surface of the first substrate 3 away from the first packaging layer 2. The second sub-conductive hole 750 penetrates the sub-substrate 720 and the sub-packaging layer 710 along the first direction M. The end of the second sub-conductive hole 750 close to the first substrate 3 abuts against the surface of the first conductive part 112 of the chip assembly 1 in the sub-packaging structure 7 away from the first main part 111. Therefore, the sub-redistribution layer 740 in the second sub-conductive hole 750 in the sub-packaging structure 7 is electrically connected to the first conductive part 112 in the sub-packaging structure 7.
[0053] Through the above scheme, the first chip 110 and the second chip 120 are laminated and bonded to form the chip assembly 1, and then the chip assembly 1 is packaged in the first packaging layer 2, so that more chips can be packaged without affecting the thickness of the packaging structure, the density of the packaging structure is improved, and the miniaturization of the packaging structure is realized.
[0054] Embodiment 4
[0055] Please refer to Figure 5 , Figure 5 is a schematic view of the packaging structure of embodiment 4 of the present application. This embodiment includes most of the technical features of embodiment 1. The difference between this embodiment and embodiment 1 is that the packaging structure comprises at least one sub-packaging structure 7. The sub-packaging structure 7 is arranged between the first redistribution layer 5 and the solder ball 6. The packaging structure of this embodiment comprises three sub-packaging structures 7. The three sub-packaging structures 7 are a first sub-packaging structure 701, a second sub-packaging structure 702 and a third sub-packaging structure 703, which are sequentially away from the first substrate 3 along the first direction M.
[0056] See also Figure 5 Each sub-package structure 7 includes: a sub-package layer 710 , a sub-substrate 720 , a first sub-conductive via 730 and a sub-redistribution layer 740 .
[0057] See also Figure 5 The sub-encapsulation layer 710 is disposed on a side of the first substrate 3 away from the first encapsulation layer 2 . The sub-encapsulation layer 710 covers the first redistribution layer 5 .
[0058] See also Figure 5 The sub-substrate 720 is disposed on a side of the sub-encapsulation layer 710 away from the first substrate 3. In this embodiment, the sub-substrate 720 is made of polyimide (PI).
[0059] See also Figure 5 The first sub-conductive via 730 penetrates the sub-substrate 720 and the sub-encapsulation layer 710 along the first direction M.
[0060] See also Figure 5 The sub-redistribution layer 740 is disposed in the first sub-conductive via 730 and on a side of the sub-substrate 720 away from the first substrate 3 .
[0061] The first sub-conductive via 730 of the sub-package structure 7 closest to the first substrate 3, at its end near the first substrate 3, abuts against the surface of the first redistribution layer 5 on the side away from the first substrate 3; the first sub-conductive vias 730 of the remaining sub-package structures 7, at their ends near the first substrate 3, abut against the surface of the sub-redistribution layer 740 of the underlying sub-package structure 7 on the side away from the first substrate 3. In this embodiment, the first sub-conductive via 730 of the bottommost sub-package structure 7, at its end near the first substrate 3, abuts against the surface of the first redistribution layer 5 on the side away from the first substrate 3; the first sub-conductive vias 730 of the remaining sub-package structures 7, at their ends near the first substrate 3, abut against the surface of the sub-redistribution layer 740 of the underlying sub-package structure 7 on the side away from the first substrate 3.
[0062] The sub-redistribution layer 740 farthest from the first substrate 3 is electrically connected to the solder balls 6, and the sub-redistribution layer 740 closest to the first substrate 3 is electrically connected to the first redistribution layer 5. In this embodiment, the sub-redistribution layer 740 of the topmost sub-package structure 7 is electrically connected to the solder balls 6, and the sub-redistribution layer 740 of the bottommost sub-package structure 7 is electrically connected to the first redistribution layer 5.
[0063] In this embodiment, the first sub-conductive hole 730 of the first sub-packaging structure 701 is in abutment with the surface of the first redistribution layer 5 away from the first substrate 3 at the end close to the first substrate 3; the first sub-conductive hole 730 of the second sub-packaging structure 702 is in abutment with the surface of the sub-redistribution layer 740 of the first sub-packaging structure 701 away from the first substrate 3 at the end close to the first substrate 3; the first sub-conductive hole 730 of the third sub-packaging structure 703 is in abutment with the surface of the sub-redistribution layer 740 of the second sub-packaging structure 702 away from the first substrate 3 at the end close to the first substrate 3; and the solder ball 6 is electrically connected to the surface of the sub-redistribution layer 740 of the third sub-packaging structure 703 away from the first substrate 3.
[0064] Through the above scheme, the first chip 110 and the second chip 120 are laminated and bonded to form the chip assembly 1, which is then encapsulated in the first packaging layer 2, so that more chips can be encapsulated without affecting the thickness of the packaging structure, the density of the packaging structure is improved, and the miniaturization of the packaging structure is realized.
[0065] Embodiment 5
[0066] Please refer to Figure 6 , Figure 6 is a schematic view of the packaging structure of embodiment 5 of the present application. This embodiment includes most of the technical features of embodiment 4. The difference between this embodiment and embodiment 4 is that at least one sub-packaging structure 7 is provided with a chip assembly 1. In this embodiment, the first sub-packaging structure 701, the second sub-packaging structure 702 and the third sub-packaging structure 703 are all provided with a chip assembly 1. In other embodiments, chip assemblies 1 can be provided in part of the sub-packaging structures 7 according to actual conditions and requirements, or no chip assembly 1 is provided in any sub-packaging structure 7.
[0067] Please refer to Figure 6 , the sub-packaging structure 7 provided with a chip assembly 1 has a second sub-conductive hole 750 penetrating the sub-substrate 720 and the sub-packaging layer 710 along the first direction M, and the sub-redistribution layer 740 is further provided in the second sub-conductive hole 750, and the sub-redistribution layer 740 is further electrically connected to the first conductive part 112 of the chip assembly 1 in the sub-packaging structure 7. In the sub-packaging structure 7 provided with a chip assembly 1, the end of the second sub-conductive hole 750 close to the first conductive part 112 is in abutment with the surface of the first conductive part 112 away from the first main part 111.
[0068] Please refer to Figure 6The embodiment is exemplified by the chip assembly 1 arranged in the first sub-packaging structure 701. In the first sub-packaging structure 701, the chip assembly 1 is arranged on the surface of the first substrate 3 away from the first packaging layer 2. The second sub-conductive hole 750 penetrates the sub-substrate 720 and the sub-packaging layer 710 along the first direction M, and the end of the second sub-conductive hole 750 close to the first substrate 3 abuts against the surface of the first conductive part 112 of the chip assembly 1 in the first sub-packaging structure 701 away from the first main part 111. Thus, the sub-redistribution layer 740 in the second sub-conductive hole 750 in the first sub-packaging structure 701 is electrically connected to the first conductive part 112 in the first sub-packaging structure 701.
[0069] Through the above scheme, the first chip 110 and the second chip 120 are laminated and bonded to form the chip assembly 1, which is then packaged in the first packaging layer 2. More chips can be packaged without affecting the thickness of the packaging structure, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is realized.
[0070] The above describes in detail the packaging structure provided by the present application. The principles and implementation modes of the present application are described by applying specific examples. The above examples are only used to help understand the core idea of the present application. For those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.
Claims
1. A packaging structure, characterized in that: The package structure has a first direction (M) and a second direction (N) intersecting each other, and the package structure includes: A chip assembly (1) comprises a first chip (110) and a second chip (120) stacked along the first direction (M), wherein the first chip (110) comprises a first main body (111) and a first conductive portion (112) arranged on a side of the first main body (111) close to the second chip (120), and the second chip (120) comprises a second main body (121) and a second conductive portion (122) arranged on a side of the second main body (121) close to the first chip (110), and the first conductive portion (112) and the second conductive portion (122) are bonded to each other; a first encapsulation layer (2) covering a side of the first main body (111) close to the second main body (121) and two sides of the first main body (111) in the second direction (N); a first substrate (3) disposed on a side of the first packaging layer (2) away from the first main body (111), the packaging structure having a first conductive hole (4) penetrating the first substrate (3) and the first packaging layer (2) along the first direction (M); a first redistribution layer (5) disposed in the first conductive hole (4) and on a side of the first substrate (3) away from the first packaging layer (2), the first redistribution layer (5) being electrically connected to the first conductive portion (112); A solder ball (6) is arranged on a side of the first redistribution layer (5) away from the first substrate (3), and the solder ball (6) is electrically connected to the first redistribution layer (5).
2. The packaging structure according to claim 1, wherein: The surface of the first encapsulation layer (2) on a side away from the first substrate (3) is flush with the surface of the first main body (111) on a side away from the first substrate (3).
3. The packaging structure according to claim 1, wherein: One end of the first conductive hole (4) close to the first main body (111) abuts against a surface of the first conductive part (112) on a side away from the first main body (111).
4. The packaging structure according to claim 1, wherein: A first conductive hole (4) is formed through a laser process and passes through the first substrate (3) and the first packaging layer (2) along the first direction (M).
5. The packaging structure according to claim 1, wherein: Also includes: At least one sub-package structure (7) is arranged between the first redistribution layer (5) and the solder ball (6); Each of the sub-package structures (7) comprises: a sub-encapsulation layer (710) disposed on a side of the first substrate (3) away from the first encapsulation layer (2), the sub-encapsulation layer (710) covering the first redistribution layer (5); a sub-substrate (720) disposed on a side of the sub-encapsulation layer (710) away from the first substrate (3), the sub-encapsulation structure (7) having a first sub-conductive hole (730) penetrating the sub-substrate (720) and the sub-encapsulation layer (710) along the first direction (M); a sub-rewiring layer (740) disposed in the first sub-conductive hole (730) and on a side of the sub-substrate (720) away from the first substrate (3); The sub-redistribution layer (740) farthest from the first substrate (3) is electrically connected to the solder ball (6), and the sub-redistribution layer (740) closest to the first substrate (3) is electrically connected to the first redistribution layer (5).
6. The packaging structure according to claim 5, wherein: The packaging structure comprises three sub-packaging structures (7), and the three sub-packaging structures (7) are respectively a first sub-packaging structure (701), a second sub-packaging structure (702), and a third sub-packaging structure (703) which are sequentially away from the first substrate (3) along the first direction (M); One end of the first sub-conductive hole (730) of the first sub-packaging structure (701) close to the first substrate (3) abuts against a surface of the first redistribution layer (5) on a side away from the first substrate (3); One end of the first sub-conductive hole (730) of the second sub-package structure (702) close to the first substrate (3) abuts against a surface of the sub-redistribution layer (740) of the first sub-package structure (701) on a side away from the first substrate (3); One end of the first sub-conductive hole (730) of the third sub-package structure (703) close to the first substrate (3) abuts against the surface of the sub-redistribution layer (740) of the second sub-package structure (702) on a side away from the first substrate (3); The solder ball (6) is electrically connected to the sub-redistribution layer (740) of the third sub-package structure (703).
7. The packaging structure according to claim 5, wherein: The chip assembly (1) is provided in at least one of the sub-package structures (7).
8. The packaging structure according to claim 7, wherein: The sub-package structure (7) provided with the chip component (1) has a second sub-conductive hole (750) penetrating the sub-substrate (720) and the sub-package layer (710) along the first direction (M); the sub-redistribution layer (740) is also arranged in the second sub-conductive hole (750); and the sub-redistribution layer (740) is also electrically connected to the first conductive portion (112) of the chip component (1) in the sub-package structure (7).
9. The packaging structure according to claim 8, wherein: In the sub-package structure (7) provided with the chip assembly (1), one end of the second sub-conductive hole (750) close to the first conductive part (112) abuts against a surface of the first conductive part (112) on a side away from the first main body part (111).
10. The packaging structure according to claim 1, wherein: The first conductive part (112) and the second conductive part (122) are bonded to each other by using one of hot pressing welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding.