Pulse circuit
By performing two voltage boosts through capacitors and diodes and combining them with a signal amplification circuit, the problem of insufficient output voltage of the main control chip is solved, and low-cost high-voltage pulse signal output is achieved, which is suitable for communication and power supply.
Patent Information
- Application Number
- CN202422525642.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-10-18
AI Technical Summary
Since the output voltage of the main control chip of the traditional pulse circuit is low, a boost chip and its peripheral circuits need to be added, which increases the cost and makes maintenance complicated.
Capacitors and diodes are used for double boosting, and the pull-up switch is controlled by the signal amplification circuit to output a high-voltage pulse signal. The boost chip is omitted, and the signal amplification circuit composed of the main control chip, NMOS tube and transistor is used to achieve high voltage output.
It reduces circuit costs, simplifies the maintenance process, can output high-voltage pulse signals, and is suitable for fields such as communications and power supply.
Smart Images
Figure CN223451951U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic technical field especially relates to a pulse circuit. BACKGROUND
[0002] The traditional pulse circuit adopts the main control chip to control the transistor output higher voltage pulse signal, because the voltage that the main control chip can output is lower, cannot directly control the transistor output higher voltage pulse signal, therefore needs to increase the step -up chip and its peripheral circuit between the main control chip and the transistor, so as to facilitate the main control chip to control the transistor output higher voltage pulse signal.
[0003] But, increase the step -up chip and its peripheral circuit can make the circuit cost increase accordingly, and when the step -up chip internal fault, then needs to replace the whole chip and maintain, makes the pulse circuit overhaul cost also increases accordingly. UTILITY MODEL CONTENT
[0004] The utility model discloses a kind of pulse circuits, first by capacitor and diode to the first power supply voltage boosting, then by signal amplification circuit the first power supply after voltage boosting is enabled, output to pull-up switch, control pull-up switch output higher voltage pulse signal, to solve the technical problem existing in prior art.
[0005] To solve the above technical problems, the utility model adopts the following technical solutions:
[0006] One aspect of the utility model embodiment provides a kind of pulse circuits, the pulse circuit includes: boost circuit, the boost circuit includes boost control circuit, first diode and first capacitor, the first end of the boost control circuit is connected one end of the first capacitor, the other end of the first capacitor connects the negative pole of the first diode, the positive pole of the first diode connects first power supply;Signal amplification circuit, the first end of the signal amplification circuit is connected the negative pole of the first diode and the other end of the first capacitor;Pull-up switch and pull-down switch, the second end of the signal amplification circuit is connected control the on-off of the pull-up switch, the first end of the pull-up switch connects second power supply, the first end of the pull-down switch is grounded, the second end of the pull-up switch and the second end of the pull-down switch are connected, to cooperate output pulse signal;Main control chip, the main control chip is connected control the boost control circuit, the signal amplification circuit and the pull-down switch respectively.
[0007] In some embodiments, the pull-up switch comprises an NMOS tube and a first resistor, the pull-down switch comprises a first NPN transistor, a second resistor and a third resistor, the drain of the NMOS tube is connected to a second power supply, the gate of the NMOS tube is connected to a second end of the signal amplification circuit and one end of the first resistor, the base of the first NPN transistor is connected to the master control chip through the second resistor, the emitter of the first NPN transistor is grounded through the third resistor, the source of the NMOS tube is connected to the collector of the first NPN transistor and the other end of the first resistor, and the NMOS tube and the first NPN transistor cooperate to output a pulse signal.
[0008] In some embodiments, the boost circuit further comprises a second diode and a second capacitor, the anode of the second diode is connected to the cathode of the first diode and the other end of the first capacitor, the cathode of the second diode is connected to one end of the second capacitor and the first end of the signal amplification circuit, and the other end of the second capacitor is connected to the source of the NMOS tube and the collector of the first NPN transistor.
[0009] In some embodiments, the boost control circuit comprises a second NPN transistor, a fourth resistor and a charging switch, the base of the second NPN transistor is connected to the master control chip through the fourth resistor, the charging switch is connected to the master control chip, the emitter of the second NPN transistor is grounded, and the collector of the second NPN transistor and the charging switch are connected to one end of the first capacitor, and the charging switch and the second NPN transistor sequentially charge and discharge one end of the first capacitor.
[0010] In some embodiments, the charging switch comprises a third NPN transistor, a fourth NPN transistor, a fifth resistor and a sixth resistor, the collector of the third NPN transistor and one end of the fifth resistor are connected to the source of the NMOS tube and the collector of the first NPN transistor, the emitter of the third NPN transistor is connected to one end of the first capacitor, the base of the third NPN transistor is connected to the other end of the fifth resistor and the collector of the fourth NPN transistor, the base of the fourth NPN transistor is connected to the master control chip, and the emitter of the fourth NPN transistor is grounded.
[0011] In some embodiments, the signal amplification circuit comprises a fifth NPN transistor, a seventh resistor and an eighth resistor, the collector of the fifth NPN transistor and one end of the eighth resistor are connected to the cathode of the second diode and one end of the second capacitor, the other end of the eighth resistor is connected to the base of the fifth NPN transistor and the master control chip, and the emitter of the fifth NPN transistor is connected to the gate of the NMOS tube through the seventh resistor.
[0012] In some embodiments, the signal amplification circuit further comprises a PNP transistor, a ninth resistor and a tenth resistor, the emitter of the PNP transistor is connected to the gate of the NMOS transistor through the tenth resistor, the base of the PNP transistor is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to the base of the fifth NPN transistor and the master control chip, and the collector of the PNP transistor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
[0013] In some embodiments, the signal amplification circuit further comprises a sixth NPN transistor and an eleventh resistor, the collector of the sixth NPN transistor is connected to the other end of the ninth resistor and the base of the fifth NPN transistor, the base of the sixth NPN transistor is connected to the master control chip through the eleventh resistor, and the emitter of the sixth NPN transistor is grounded.
[0014] In some embodiments, the signal amplification circuit further comprises a third capacitor, and the third capacitor is connected in parallel with the eleventh resistor.
[0015] The pulse circuit according to the embodiment of the present application has at least the following beneficial effects: the first diode and the first capacitor are arranged to perform first voltage boosting, the second diode and the second capacitor are arranged to perform second voltage boosting, the first power supply after the second voltage boosting is used to control the NMOS transistor to output a pulse signal with a higher voltage, and the first NPN transistor is used for pull-down of the pulse signal. The master control chip performs first signal amplification control through the sixth NPN transistor, and then performs second signal amplification control through the fifth NPN transistor and the PNP transistor, so that the master control chip can control the first power supply after the second voltage boosting to start the NMOS transistor to output the pulse signal. The pulse circuit has low production cost, can output a pulse signal with a higher voltage, can be used for communication and power supply, and has strong practicability.
[0016] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0018] Figure 1 The pulse circuit schematic diagram according to the embodiment. DETAILED DESCRIPTION
[0019] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.
[0020] The terms "first", "second", "third" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.
[0021] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood in a broad sense, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0022] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects of the example implementations to those skilled in the art. The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings are not intended to be restrictive in any way. Throughout the drawings, like references numerals denote like features, and thus repeated description is omitted.
[0023] The technical solutions of the embodiments of the present application will be briefly described below:
[0024] According to some embodiments, the present application provides a pulse circuit, the pulse circuit comprising:
[0025] The boost circuit comprises a boost control circuit, a first diode D1 and a first capacitor C1. The first end of the boost control circuit is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the negative electrode of the first diode D1. The positive electrode of the first diode D1 is connected to the first power supply V1.
[0026] The first end of the signal amplification circuit is connected with the negative electrode of the first diode D1 and the other end of the first capacitor C1.
[0027] The second end of the signal amplification circuit is connected with the on-off control of the pull-up switch, the first end of the pull-up switch is connected with the second power supply V2, the first end of the pull-down switch is connected with the ground, and the second end of the pull-up switch and the second end of the pull-down switch are connected to cooperate to output the pulse signal VOUT.
[0028] The main control chip is connected with the boost control circuit, the signal amplification circuit and the pull-down switch.
[0029] Based on the working principle of the above embodiment, the main control chip controls the first diode D1 and the first capacitor C1 to work in the boost mode through the boost control circuit, so as to boost the first power supply V1, and then the boosted first power supply V1 is transmitted to the pull-up switch as an enable signal through the signal amplification circuit, so as to control the pull-up switch to work and output the pulse signal VOUT with a higher voltage.
[0030] Specifically, as shown in Figure 1 The pull-up switch includes an NMOS tube MN and a first resistor R1, the pull-down switch includes a first NPN transistor QN1, a second resistor R2 and a third resistor R3, the drain of the NMOS tube MN is connected with the second power supply V2, the gate of the NMOS tube MN is connected with the second end of the signal amplification circuit and one end of the first resistor R1, the base of the first NPN transistor QN1 is connected with the main control chip through the second resistor R2, the emitter of the first NPN transistor QN1 is connected with the ground through the third resistor R3, the source of the NMOS tube MN is connected with the collector of the first NPN transistor QN1 and the other end of the first resistor R1, and the NMOS tube MN and the first NPN transistor QN1 cooperate to output the pulse signal VOUT.
[0031] In other embodiments, the first NPN transistor QN1 can be replaced by an NMOS tube or other transistors with switching function. The application does not make any limitation. The pull-up switch of the application preferably adopts the NMOS tube MN, and the output power of the NMOS tube MN is higher than that of the NPN transistor, and the performance-price ratio of the NMOS tube MN is higher than that of the PMOS tube.
[0032] Further, as shown in Figure 1 The boost circuit further includes a second diode D2 and a second capacitor C2, the positive electrode of the second diode D2 is connected with the negative electrode of the first diode D1 and the other end of the first capacitor C1, the negative electrode of the second diode D2 is connected with one end of the second capacitor C2 and the first end of the signal amplification circuit, and the other end of the second capacitor C2 is connected with the source of the NMOS tube MN and the collector of the first NPN transistor QN1.
[0033] Further, such as Figure 1 As shown, the boost control circuit includes a second NPN transistor QN2, a fourth resistor R4 and a charging switch. The base of the second NPN transistor QN2 is connected to the main control chip through the fourth resistor R4, the charging switch is connected to the main control chip, the emitter of the second NPN transistor QN2 is grounded, the collector of the second NPN transistor QN2 and the charging switch are connected to one end of the first capacitor C1, and the charging switch and the second NPN transistor QN2 charge and discharge one end of the first capacitor C1 in sequence.
[0034] Further, such as Figure 1 As shown, the charging switch includes a third NPN transistor QN3, a fourth NPN transistor QN4, a fifth resistor R5 and a sixth resistor R6. The collector of the third NPN transistor QN3 and one end of the fifth resistor R5 are connected to the source of the NMOS transistor MN and the collector of the first NPN transistor QN1. The emitter of the third NPN transistor QN3 is connected to one end of the first capacitor C1. The base of the third NPN transistor QN3 is connected to the other end of the fifth resistor R5 and the collector of the fourth NPN transistor QN4. The base of the fourth NPN transistor QN4 is connected to the main control chip, and the emitter of the fourth NPN transistor QN4 is grounded.
[0035] According to some embodiments, Figure 1 As shown, the signal amplification circuit includes a fifth NPN transistor QN5, a seventh resistor R7 and an eighth resistor R8. The collector of the fifth NPN transistor QN5 and one end of the eighth resistor R8 are connected to the cathode of the second diode D2 and one end of the second capacitor C2. The other end of the eighth resistor R8 is connected to the base of the fifth NPN transistor QN5 and the main control chip. The emitter of the fifth NPN transistor QN5 is connected to the gate of the NMOS transistor MN through the seventh resistor R7.
[0036] Further, such as Figure 1 As shown, the signal amplification circuit also includes a PNP transistor QP, a ninth resistor R9, and a tenth resistor R10. The emitter of the PNP transistor QP is connected to the gate of the NMOS transistor MN through the tenth resistor R10. The base of the PNP transistor QP is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the base of the fifth NPN transistor QN5 and the main control chip. The collector of the PNP transistor QP is connected to the source of the NMOS transistor MN and the collector of the first NPN transistor QN1.
[0037] Further, such as Figure 1As shown, the signal amplification circuit also includes a sixth NPN transistor QN6 and an eleventh resistor R11. The collector of the sixth NPN transistor QN6 is connected to the other end of the ninth resistor R9 and the base of the fifth NPN transistor QN5. The base of the sixth NPN transistor QN6 is connected to the main control chip through the eleventh resistor R11. The emitter of the sixth NPN transistor QN6 is grounded.
[0038] Further, such as Figure 1 As shown, the signal amplifying circuit further includes a third capacitor C3, and the third capacitor C3 is connected in parallel with the eleventh resistor R11.
[0039] The working principle of the present application is as follows: the main control chip outputs a PWM signal to the base of the second NPN transistor QN2 and the base of the fourth NPN transistor QN4 to control the first power supply V1 to perform the first boosting operation in the first diode D1 and the first capacitor C1, and then enter the second diode D2 and the second capacitor C2 for the second boosting operation. After the first power supply V1 is boosted twice, the main control chip outputs a low-level L_CTL_H signal to the base of the sixth NPN transistor QN6, the sixth NPN transistor QN6 is turned off, and the fifth NPN transistor QN5 is turned on. At the same time, the main control chip also outputs a low-level L_CTL_L signal to the base of the first NPN transistor QN1, the first NPN transistor QN1 is turned off. The fifth NPN transistor QN5 outputs the first power supply V1 after the double boosting to the gate of the NMOS transistor MN, so that the NMOS transistor MN can be turned on, and the pulse signal VOUT outputs a high-level signal. If the first voltage is not boosted and the first power source V1 is directly output to the gate of the NMOS transistor MN, the NMOS transistor MN cannot be turned on for output. The main control chip then outputs a high-level L_CTL_H signal to the base of the sixth NPN transistor QN6 and a high-level L_CTL_L signal to the base of the first NPN transistor QN1. The sixth NPN transistor QN6 is turned on, the fifth NPN transistor QN5 is turned off, the PNP transistor QP is turned on, the NMOS transistor MN is turned off, and the first NPN transistor QN1 is turned on, resulting in the pulse signal VOUT outputting a low-level signal.
[0040] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0041] While the disclosure has been described with reference to several exemplary embodiments, it is understood that the words that have been used are words of description and illustration, rather than words of limitation. As previously mentioned, changes and modifications can be made to the above-described embodiments without departing from the spirit or scope of the disclosure, and it is understood that the above-described embodiments are to be considered exemplary only, and the scope of the disclosure is to be determined by the following claims, and equivalents thereto.
Claims
1. A pulse circuit, characterized in that: The pulse circuit comprises: a boost circuit, the boost circuit comprising a boost control circuit, a first diode, and a first capacitor, wherein a first end of the boost control circuit is connected to one end of the first capacitor, the other end of the first capacitor is connected to the cathode of the first diode, and the anode of the first diode is connected to a first power supply; a signal amplifying circuit, wherein a first end of the signal amplifying circuit is connected to the cathode of the first diode and the other end of the first capacitor; A pull-up switch and a pull-down switch, wherein the second end of the signal amplifying circuit is connected to control the on / off of the pull-up switch, the first end of the pull-up switch is connected to a second power supply, the first end of the pull-down switch is grounded, and the second end of the pull-up switch is connected to the second end of the pull-down switch to coordinately output a pulse signal; A main control chip is connected to control the boost control circuit, the signal amplifying circuit and the pull-down switch respectively.
2. The pulse circuit according to claim 1, characterized in that The pull-up switch includes an NMOS tube and a first resistor, and the pull-down switch includes a first NPN transistor, a second resistor and a third resistor. The drain of the NMOS tube is connected to the second power supply, the gate of the NMOS tube is connected to the second end of the signal amplification circuit and one end of the first resistor, the base of the first NPN transistor is connected to the main control chip through the second resistor, the emitter of the first NPN transistor is grounded through the third resistor, the source of the NMOS tube is connected to the collector of the first NPN transistor and the other end of the first resistor, and the NMOS tube and the first NPN transistor cooperate to output a pulse signal.
3. The pulse circuit according to claim 2, characterized in that The boost circuit also includes a second diode and a second capacitor, the anode of the second diode is connected to the cathode of the first diode and the other end of the first capacitor, the cathode of the second diode is connected to one end of the second capacitor and the first end of the signal amplification circuit, and the other end of the second capacitor is connected to the source of the NMOS tube and the collector of the first NPN transistor.
4. The pulse circuit according to claim 3, characterized in that: The boost control circuit includes a second NPN transistor, a fourth resistor and a charging switch, the base of the second NPN transistor is connected to the main control chip through the fourth resistor, the charging switch is connected to the main control chip, the emitter of the second NPN transistor is grounded, the collector of the second NPN transistor and the charging switch are connected to one end of the first capacitor, and the charging switch and the second NPN transistor charge and discharge one end of the first capacitor in turn.
5. The pulse circuit according to claim 4, characterized in that: The charging switch includes a third NPN transistor, a fourth NPN transistor, a fifth resistor and a sixth resistor. The collector of the third NPN transistor and one end of the fifth resistor are connected to the source of the NMOS transistor and the collector of the first NPN transistor. The emitter of the third NPN transistor is connected to one end of the first capacitor. The base of the third NPN transistor is connected to the other end of the fifth resistor and the collector of the fourth NPN transistor. The base of the fourth NPN transistor is connected to the main control chip, and the emitter of the fourth NPN transistor is grounded.
6. The pulse circuit according to claim 3, characterized in that: The signal amplification circuit includes a fifth NPN transistor, a seventh resistor and an eighth resistor. The collector of the fifth NPN transistor and one end of the eighth resistor are connected to the negative electrode of the second diode and one end of the second capacitor. The other end of the eighth resistor is connected to the base of the fifth NPN transistor and the main control chip. The emitter of the fifth NPN transistor is connected to the gate of the NMOS tube through the seventh resistor.
7. The pulse circuit according to claim 6, characterized in that: The signal amplification circuit also includes a PNP transistor, a ninth resistor and a tenth resistor. The emitter of the PNP transistor is connected to the gate of the NMOS transistor through the tenth resistor. The base of the PNP transistor is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the base of the fifth NPN transistor and the main control chip. The collector of the PNP transistor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
8. The pulse circuit according to claim 7, characterized in that: The signal amplification circuit also includes a sixth NPN transistor and an eleventh resistor, the collector of the sixth NPN transistor is connected to the other end of the ninth resistor and the base of the fifth NPN transistor, the base of the sixth NPN transistor is connected to the main control chip through the eleventh resistor, and the emitter of the sixth NPN transistor is grounded.
9. The pulse circuit according to claim 8, characterized in that: The signal amplifying circuit further includes a third capacitor, and the third capacitor is connected in parallel with the eleventh resistor.