Circuit for reducing delay dissipation of flight time measurement system

Abstract

The utility model provides a circuit for reducing delay dissipation of a flight time measuring system, which comprises a digital signal processing unit, a comparator, a control unit, a PGA circuit and a peak value detection unit, and the comparator, the PGA circuit and the peak value detection unit form a signal processing circuit. And the signal processing circuit is respectively connected with the digital signal processing unit and the control unit. The peak value detection unit is used for sampling signal intensity, and circuit cost and power consumption are reduced. And meanwhile, the comparator is optimized, so that the signal processing circuit can keep relatively small delay change in a relatively large signal amplitude change range, the requirement on the PGA gain stage is relatively low, and the chip area is reduced.

Description

Technical Field

[0001] The utility model relates to the field of time measurement, in particular to a circuit for reducing delay dissipation of a time-of-flight measurement system. Background Art

[0002] In the process of using a time-to-digital converter to measure time, a signal processing circuit is often required to process the system's analog signal into a digital signal. Therefore, the time measured by the time-to-digital converter includes not only the time of the target link of the time measurement, but also the delay of each signal processing circuit, such as Figure 1 As shown in Figure 1. If the signal processing circuit delay is fixed, compensation is easy. However, the delay of the processing circuit often varies with the input signal, making compensation difficult or expensive, and errors in the time measurement results are difficult to avoid. Therefore, reducing the spread of the signal processing circuit delay is crucial to minimizing the system's time measurement errors.

[0003] In the traditional solution, the signal processing circuit only includes a comparator, such as Figure 2 As shown in Figure 1, the propagation delay of this circuit is large when the input signal amplitude changes.

[0004] There is a solution to reduce the delay spread of signal processing circuits. Figure 3 As shown, this solution uses an ADC chip to sample signal amplitude and digitally controls the gain of a programmable gain amplifier (PGA) to maintain the transducer's signal amplitude at a certain level. This solution reduces the signal processing circuit's processing delay for input signals of varying amplitudes, and can also reduce the delay spread of the signal processing circuit to a certain extent, but it still falls short of requirements. Furthermore, this solution uses an ADC chip to sample signal strength, which increases circuit cost and power consumption. It requires a fine PGA gain step size, resulting in a large number of stages and a large chip area. Furthermore, the ADC's internal comparator is not optimized, requiring the PGA to be constantly open, significantly increasing power consumption. Utility Model Content

[0005] The purpose of the utility model is to address the problems existing in the prior art and provide a circuit with small delay variation and low power consumption for reducing the delay dissipation of a time-of-flight measurement system.

[0006] The utility model object of the utility model is achieved through the following technical solutions:

[0007] A circuit for reducing delay dissipation in a time-of-flight measurement system includes a digital signal processing unit, a comparator, a control unit, and a PGA circuit. The circuit is characterized in that the circuit also includes a peak detection unit. The comparator, PGA circuit, and peak detection unit constitute a signal processing circuit, which is connected to the digital signal processing unit and the control unit respectively.

[0008] As a further technical solution, the comparator is a low-delay dissipative comparator.

[0009] As a further technical solution, the low-delay dissipative comparator comprises a comparator body and a current adjusting circuit, and the current adjusting circuit is connected with a differential amplifier of the comparator body.

[0010] As a further technical solution, the current adjusting circuit comprises transistors M9 and M 10 , the gate and the drain of the transistor M9 are connected with the drain of the transistor M2 and the drain of the transistor M4 of the differential amplifier, the source of the transistor M9 is connected with a power supply ground GND of the circuit, the gate and the drain of the transistor M 10 are connected with the drain of the transistor M1 and the drain of the transistor M3 of the differential amplifier, and the source of the transistor M 10 is connected with the power supply ground GND of the circuit.

[0011] As a further technical solution, the peak detection unit is connected between the control unit and the PGA circuit.

[0012] Compared with the prior art, the utility model has the following advantages:

[0013] 1、 the utility model discloses peak detection unit to sample signal intensity, reduce circuit cost and power consumption;

[0014] 2、 because optimizing comparator, signal processing circuit can keep smaller delay change in larger signal amplitude variation range, and the requirement of PGA gain series is lower, and chip area reduces;

[0015] 3、 because optimizing comparator, signal processing circuit can keep smaller delay change in larger signal amplitude variation range, and PGA circuit can be closed in certain signal variation range, and circuit power consumption is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is time - digital converter time measurement error analysis diagram;

[0017] Figure 2 It is a kind of signal processing circuit of tradition;

[0018] Figure 3 It is a kind of circuit diagram of reducing circuit delay dispersion of existing;

[0019] Figure 4 It is the circuit schematic diagram of the utility model;

[0020] Figure 5 It is PGA and peak detection module in Figure 4 Detailed circuit diagram of module;

[0021] Figure 6 for Figure 4 Circuit diagram of a low to medium delay dissipation comparator. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Example 1

[0024] The overall design scheme of the present invention is as follows: The peak detection unit of the present invention detects the signal amplitude after amplification by the PGA circuit (PGA for short), and dynamically adjusts the PGA gain based on the deviation between the detection result and the ideal signal to maintain signal stability. The present invention also optimizes the design of the comparator portion, significantly reducing its delay dispersion under different input signals. The entire echo signal processing circuit maintains extremely small delay fluctuations within a large range of input signal amplitude variations, thereby improving the accuracy of the time measurement system when the input signal amplitude varies. The PGA circuit is only turned on when the signal fluctuates significantly and is turned off in other situations (the vast majority of the time), significantly reducing circuit power consumption.

[0025] Specifically, this embodiment provides a circuit for reducing the delay dissipation of a time-of-flight measurement system. Figure 4 As shown in Figure 1, the circuit includes a digital signal processing unit, a comparator, a control unit, a PGA circuit, and a peak detection unit. The comparator, PGA circuit, and peak detection unit constitute the signal processing circuit, which is connected to the digital signal processing unit and the control unit, respectively. The peak detection unit detects the amplitude of the signal amplified by the PGA circuit and dynamically adjusts the PGA circuit's gain based on the deviation between the detection result and the ideal signal.

[0026] Example 2

[0027] This embodiment uses a low-latency dissipation comparator as the comparator. The low-latency dissipation comparator includes a comparator body and a current regulation circuit. The current regulation circuit is connected to the differential amplifier of the comparator body to regulate the charging or discharging current of the differential amplifier.

[0028] The rest of this embodiment is the same as that of embodiment 1.

[0029] Example 3

[0030] like Figure 6 As shown, this embodiment provides a specific low-delay dissipation comparator, which includes a comparator body and a current regulation circuit, the current regulation circuit includes transistors M9 and M 10The gate and drain of transistor M9 are connected to the drain of transistor M2 and the drain of transistor M4 of the differential amplifier, the source of transistor M9 is connected to the power ground GND of the circuit, and transistor M 10 The gate and drain of the differential amplifier are connected to the drain of transistor M1 and the drain of transistor M3. 10 The source is connected to the circuit's power ground GND.

[0031] for Figure 6 Comparator in (no M9 and M 10 ), the first stage is the differential amplifier, which contributes the most to the delay variation. The delay spread caused by overdrive is mainly due to the parasitic load capacitance (C Load If the input signal amplitude is high, the charging or discharging current (I charge ) is large, so the secondary circuit output will flip quickly, and vice versa. Delay time (T pd ) can be approximated as Where α is the DC operating point correlation coefficient. ΔV It is proportional to the input overdrive voltage. Obviously, in order to maintain a relatively constant T under different input overdrive voltages, pd , can be achieved through ΔV Dynamic Adjustment I charge In order to adjust I charge , designed the current regulation circuit (M9 and M 10 ),like Figure 6 As shown in Figure 2, the current regulation circuit's current sink adaptively increases or decreases. As a result, the small propagation delay associated with high-amplitude inputs increases. Since the load impedance on the differential amplifier decreases, the propagation delay associated with low-amplitude inputs decreases as the comparator bandwidth increases. Consequently, delay spread is minimized.

[0032] The rest of this embodiment is the same as that of embodiment 2.

[0033] Example 4

[0034] like Figure 5 As shown, the peak detection unit is connected between the control unit and the PGA circuit. PGA gain control is achieved by adaptively adjusting the negative feedback resistor of the folded cascode Class AB amplifier based on the peak detection unit's output. When the peak detection unit's output is lower than the user-set value, the PGA circuit's gain increases from its minimum level until the peak detection unit's output exceeds the user-set value or the PGA circuit reaches its maximum gain level. If the original signal is strong enough, the PGA circuit is turned on only when the signal fluctuates significantly; it is turned off otherwise, enabling low-power applications.

[0035] The rest of this example is the same as example 1.

[0036] The above merely describes the preferred embodiments of the present application and is not used to limit the present application, and it should be pointed out that any modification, equivalent replacement and improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A circuit for reducing delay dissipation in a time-of-flight measurement system, comprising a digital signal processing unit, a comparator, a control unit, and a PGA circuit, characterized in that: The circuit also includes a peak detection unit. The comparator, the PGA circuit and the peak detection unit constitute a signal processing circuit, which is connected to the digital signal processing unit and the control unit respectively.

2. The circuit for reducing delay dissipation in a time-of-flight measurement system according to claim 1, characterized in that: The comparator is a low-latency dissipation comparator.

3. The circuit for reducing delay dissipation in a time-of-flight measurement system according to claim 2, characterized in that: The low-delay dissipation comparator includes a comparator body and a current regulating circuit, wherein the current regulating circuit is connected to the differential amplifier of the comparator body.

4. The circuit for reducing delay dissipation in a time-of-flight measurement system according to claim 3, characterized in that: The current regulating circuit includes transistors M9 and M 10 The gate and drain of transistor M9 are connected to the drain of transistor M2 and the drain of transistor M4 of the differential amplifier, the source of transistor M9 is connected to the power ground GND of the circuit, and transistor M 10 The gate and drain of the transistor M1 are connected to the drain of the transistor M3 of the differential amplifier. 10 The source is connected to the circuit's power ground GND.

5. The circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 1, characterized in that: The peak detection unit is connected between the control unit and the PGA circuit.

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