Display panel and display device

Abstract

The utility model provides a display panel, which comprises a gate layer, an insulating layer, a source and drain electrode layer, a first protective layer, a reference electrode layer, a second protective layer and a pixel electrode layer, and is characterized in that the gate layer is provided with a first surface and a second surface which are oppositely arranged; the insulating layer is arranged on the first surface; the source and drain electrode layer is arranged on one side, far away from the grid electrode layer, of the insulating layer; the first protection layer is arranged on one side, far away from the insulating layer, of the source and drain electrode layer; the reference electrode layer is arranged on one side, far away from the source and drain electrode layer, of the first protection layer; the second protection layer is arranged on one side, far away from the first protection layer, of the reference electrode layer; the pixel electrode layer is arranged on one side, far away from the reference electrode layer, of the second protection layer; wherein the pixel electrode layer is connected with at least two of the grid electrode layer, the source and drain electrode layer and the reference electrode layer to form at least two capacitors. The reliability of the GIP circuit is improved, so that the display of the display panel is more reliable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of society and the progress of technology, LCD liquid crystal display screens have been widely used in our life, and are widely applied to televisions, cars, cash registers, order-taking machines, traffic stations, road signs, aerospace equipment and the like.

[0003] From the early CRT (Cathode Ray Tube) display technology to the current mainstream LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) and emerging Mini LED display technologies. Among them, LCD controls the rotation of liquid crystal molecules to refract the light of the backlight module to produce a picture, has the advantages of thin body, power saving, no radiation, and the like, and the active switch display TFT-LCD occupies the dominant position in the display field due to low power consumption, excellent picture quality and high production yield.

[0004] In the existing display panel structure, a GIP (Gate in Panel) circuit is usually used to provide signal control. This technology can save scanning chips, reduce material costs, reduce process steps and shorten process time, thereby reducing the cost of the panel and realizing a narrower frame. However, the existing GIP circuit has low reliability, which affects the display quality of the display panel and cannot meet the market needs.

[0005] Therefore, it is a technical problem to be solved by those skilled in the art to provide a display panel and a display device that improve the display quality of the display panel. Invention content

[0006] The present application provides a display panel and a display device.

[0007] The present application provides a display panel, which comprises a gate layer, an insulating layer, a source-drain layer, a first protective layer, a reference electrode layer, a second protective layer and a pixel electrode layer. The gate layer has a first surface and a second surface arranged opposite to each other. The insulating layer is arranged on the first surface. The source-drain layer is arranged on a side of the insulating layer away from the gate layer. The first protective layer is arranged on a side of the source-drain layer away from the insulating layer. The reference electrode layer is arranged on a side of the first protective layer away from the source-drain layer. The second protective layer is arranged on a side of the reference electrode layer away from the first protective layer. The pixel electrode layer is arranged on a side of the second protective layer away from the reference electrode layer. The pixel electrode layer is connected to at least two of the gate layer, the source-drain layer and the reference electrode layer to form at least two capacitors.

[0008] In some embodiments, the pixel electrode layer is connected with the gate layer to form a first capacitor, and the pixel electrode layer is connected with the reference electrode layer to form a second capacitor.

[0009] In some embodiments, a first via and a second via are included, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer, and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form a first capacitor, the second via passes through the second protective layer, and the pixel electrode layer is connected with the reference electrode layer through the second via to form a second capacitor.

[0010] In some embodiments, the pixel electrode layer is connected with the gate layer to form a first capacitor, and the pixel electrode layer is connected with the source-drain layer to form a third capacitor.

[0011] In some embodiments, a first via and a third via are included, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer, and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form a first capacitor, the third via passes through the second protective layer, the reference electrode layer, and the first protective layer, and the pixel electrode layer is connected with the source-drain layer through the third via to form a third capacitor.

[0012] In some embodiments, the pixel electrode layer is connected with the gate layer to form a first capacitor, the pixel electrode layer is connected with the reference electrode layer to form a second capacitor, and the pixel electrode layer is connected with the source-drain layer to form a third capacitor.

[0013] In some embodiments, a first via, a second via, and a third via are included, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer, and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form a first capacitor, the second via passes through the second protective layer, the pixel electrode layer is connected with the reference electrode layer through the second via to form a second capacitor, the third via passes through the second protective layer, the reference electrode layer, and the first protective layer, and the pixel electrode layer is connected with the source-drain layer through the third via to form a third capacitor.

[0014] In some embodiments, an opening of the first via gradually decreases from a side of the second protective layer to a side of the gate layer, and an opening of the third via gradually decreases from a side of the second protective layer to a side of the first protective layer.

[0015] In some embodiments, a glass substrate is further included, and the glass substrate is located at a second side of the gate layer.

[0016] The display device provided by another embodiment of the present application also includes the display panel described in the above embodiments.

[0017] The display panel provided by the embodiments of the present application includes a gate layer, an insulating layer, a source-drain layer, a first protective layer, a reference electrode layer, a second protective layer, and a pixel electrode layer. The gate layer has a first surface and a second surface arranged oppositely. The insulating layer is arranged on the first surface. The source-drain layer is arranged on a side of the insulating layer away from the gate layer. The first protective layer is arranged on a side of the source-drain layer away from the insulating layer. The reference electrode layer is arranged on a side of the first protective layer away from the source-drain layer. The second protective layer is arranged on a side of the reference electrode layer away from the first protective layer. The pixel electrode layer is arranged on a side of the second protective layer away from the reference electrode layer. The pixel electrode layer is connected with at least two of the gate layer, the source-drain layer, and the reference electrode layer to form at least two capacitors. The at least two capacitors are arranged to increase the capacitance, so that the voltage output of the display panel is larger, the reliability of the GIP circuit is improved, and the display of the display panel is more reliable. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 The structure schematic diagram of the display panel provided by the embodiments of the present application is shown.

[0020] Figure 2 Another structure schematic diagram of the display panel provided by the embodiments of the present application is shown.

[0021] Figure 3 The structure schematic diagram of the display device provided by the embodiments of the present application is shown.

[0022] Figure 4 The schematic diagram of the GIP circuit provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0024] In the description of the application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0025] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication or interaction relationship of two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0026] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or the contact of the first and second features through another feature between them. Moreover, the "upper", "upper" and "upper" of the first feature to the second feature include the first feature above and obliquely above the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature to the second feature include the first feature below and obliquely below the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0027] The disclosure below provides many different embodiments or examples for implementing different structures of the application. For the purpose of simplicity, the description below for a particular embodiment refers only to certain examples and specific configurations. Purposely, this is only in the interest of clarity and marking and is not meant to limit the application. Moreover, the application can repeat reference numerals and / or letters in various examples and this repetition is for the purpose of simplicity and clarity and is not meant to indicate common or related features between the various embodiments and / or uses discussed. Also, the terms "first", "second", and the like, do not denote any order, quantity, combination, or importance, but rather are used to nomenclature different elements. In addition, the application provides examples of various specific processes and materials, but one of ordinary skill in the art can readily recognize that other processes and / or materials can be used.

[0028] The embodiments of the present application provide a display panel and a display device.

[0029] Please refer to Figure 1 The embodiments of the present application provide a display panel 100, comprising: a gate layer 10, an insulation layer 20, a source / drain layer 30, a first protective layer 40, a reference electrode layer 50, a second protective layer 60, and a pixel electrode layer 70. The gate layer 10 has a first surface 10a and a second surface 10b arranged oppositely; the insulation layer 20 is arranged on the first surface 10a; the source / drain layer 30 is arranged on a side of the insulation layer 20 away from the gate layer 10; the first protective layer 40 is arranged on a side of the source / drain layer 30 away from the insulation layer 20; the reference electrode layer 50 is arranged on a side of the first protective layer 40 away from the source / drain layer 30; the second protective layer 60 is arranged on a side of the reference electrode layer 50 away from the first protective layer 40; and the pixel electrode layer 70 is arranged on a side of the second protective layer 60 away from the reference electrode layer 50; wherein the pixel electrode layer 70 is connected with at least two of the gate layer 10, the source / drain layer 30, and the reference electrode layer 50 to form at least two capacitors.

[0030] The gate layer 10 (Gate Layer): The gate layer 10 is a part of the TFT-LCD panel that controls the on-off state of each pixel. It is composed of a metal layer, usually located at the bottom layer of the panel, and controls the opening and closing of the TFT by changing the gate voltage.

[0031] The insulation layer 20 (Insulation Layer): The insulation layer 20 is arranged on the gate layer 10, and its main function is to prevent current leakage from the gate layer 10 to other layers, ensuring the stability of the gate voltage.

[0032] The source / drain layer 30 (Source / Drain Layer): The source / drain layer 30 is located on the insulation layer 20 and is the two main electrodes of the TFT, responsible for the inflow and outflow of current. They are usually composed of doped semiconductor materials, used to form the source and drain of the TFT.

[0033] First Protective Layer 40: The first protective layer 40 is disposed on the side of the source-drain layer 30 away from the insulating layer 20, and its function is to protect the underlying layers from physical damage and chemical corrosion.

[0034] Reference Electrode Layer 50: The reference electrode layer 50 is disposed on the side of the first protective layer 40 away from the source-drain layer 30, and it is used in some display technologies to provide a stable potential reference to ensure the uniformity and stability of the display panel 100.

[0035] Second Protective Layer 60: The second protective layer 60 is disposed on the side of the reference electrode layer 50 away from the first protective layer 40, further protecting the internal structure from the influence of the external environment on the performance of the panel.

[0036] Pixel Electrode Layer 70: The pixel electrode layer 70 is disposed on the side of the second protective layer 60 away from the reference electrode layer 50, and it is the electrode that directly contacts the liquid crystal, responsible for controlling the arrangement of liquid crystal molecules under the action of an electric field, thereby affecting the transmission of light and the display state of the pixel.

[0037] It should be noted that the pixel electrode layer 70 is connected to at least two of the gate layer 10, source-drain layer 30, and reference electrode layer 50 to form at least two capacitors. For example, the pixel electrode layer 70 forms a capacitor with the gate layer 10, and the pixel electrode layer 70 forms a capacitor with the source-drain layer 30, forming a double capacitor. For example, the pixel electrode layer 70 forms a capacitor with the gate layer 10, and the pixel electrode layer 70 forms a capacitor with the reference electrode layer 50, forming a double capacitor. For example, the pixel electrode layer 70 forms a capacitor with the gate layer 10, and the pixel electrode layer 70 forms a capacitor with the reference electrode layer 50, forming a double capacitor. For example, the pixel electrode layer 70 forms a capacitor with the gate layer 10, the pixel electrode layer 70 forms a capacitor with the source-drain layer 30, and the pixel electrode layer 70 forms a capacitor with the reference electrode layer 50, forming a triple capacitor.

[0038] In this application, the pixel electrode layer 70 is connected to different conductive parts to form a parallel capacitor structure, thereby increasing the Cb capacitance of the GIP circuit, allowing the display panel 100 to have a larger voltage output, improving the reliability of the GIP circuit, and thus making the display of the display panel 100 more reliable.

[0039] In some embodiments, the pixel electrode layer 70 is connected with the gate layer 10 to form a first capacitor, and the pixel electrode layer 70 is connected with the reference electrode layer 50 to form a second capacitor.

[0040] In some embodiments, a first via 101 and a second via 102 are included, the first via 101 passes through the second protective layer 60, the reference electrode layer 50, the first protective layer 40, the source-drain layer 30, and the insulating layer 20, the pixel electrode layer 70 is connected with the gate layer 10 through the first via 101 to form a first capacitor, and the second via 102 passes through the second protective layer 60, the pixel electrode layer 70 is connected with the reference electrode layer 50 through the second via 102 to form a second capacitor.

[0041] It should be noted that the first via 101 passes through the second protective layer 60, the reference electrode layer 50, the first protective layer 40, the source-drain layer 30, and the insulating layer 20, and connects the pixel electrode layer 70 with the gate layer 10 to form a first capacitor. This via realizes the vertical electrical connection between the pixel electrode layer 70 and the gate layer 10, allowing current and signals to pass between the two layers. This connection is crucial for controlling the arrangement of liquid crystal molecules and the refresh rate of the display panel 100, as it involves the formation of a capacitor (the first capacitor) between the pixel electrode and the gate.

[0042] The second via 102 passes through the second protective layer 60, and the pixel electrode layer 70 is connected with the reference electrode layer 50 through this via to form a second capacitor. This via also realizes the vertical electrical connection between the pixel electrode layer 70 and the reference electrode layer 50, which is very important for maintaining the stability and uniformity of the display panel 100, as it involves the formation of a capacitor (the second capacitor) between the pixel electrode and the reference electrode.

[0043] These two vias and the corresponding capacitors are crucial for the functionality of the display panel 100. The first capacitor involves the storage of electric charge between the gate and the pixel electrode, which directly affects the switching state of each pixel and the display quality. The second capacitor involves the reference electrode, which can be used to maintain a stable reference potential to ensure the uniformity and stability of the display panel 100. In this way, the vias not only provide electrical connections, but also participate in the formation of capacitors in the display panel 100, which have a positive effect on controlling the dynamic and static characteristics of liquid crystal display.

[0044] In some embodiments, the pixel electrode layer 70 is connected with the gate layer 10 to form a first capacitor, and the pixel electrode layer 70 is connected with the source-drain layer 30 to form a third capacitor.

[0045] In some embodiments, the first via 101 passes through the second protective layer 60, the reference electrode layer 50, the first protective layer 40, the source-drain electrode layer 30, and the insulating layer 20, and the pixel electrode layer 70 is connected to the gate electrode layer 10 through the first via 101 to form a first capacitor. The third via 103 passes through the second protective layer 60, the reference electrode layer 50, and the first protective layer 40, and the pixel electrode layer 70 is connected to the source-drain electrode layer 30 through the third via 103 to form a third capacitor.

[0046] It should be noted that the third via 103 passes through the second protective layer 60, the reference electrode layer 50, and the first protective layer 40 to connect the pixel electrode layer 70 and the source-drain electrode layer 30. This structure allows vertical electrical connection between the pixel electrode layer 70 and the source-drain electrode layer 30, thereby forming a third capacitor. This capacitor is crucial for controlling the arrangement of liquid crystal molecules and the refresh rate of the display panel 100, as it involves charge storage between the pixel electrode and the source-drain electrode. The double capacitor composed of the first capacitor and the third capacitor can make the GIP circuit more stable, making the display effect of the display panel 100 more stable.

[0047] In some embodiments, the pixel electrode layer 70 is connected to the gate electrode layer 10 to form a first capacitor, the pixel electrode layer 70 is connected to the reference electrode layer 50 to form a second capacitor, and the pixel electrode layer 70 is connected to the source-drain electrode layer 30 to form a third capacitor.

[0048] In some embodiments, the first via 101 passes through the second protective layer 60, the reference electrode layer 50, the first protective layer 40, the source-drain electrode layer 30, and the insulating layer 20, and the pixel electrode layer 70 is connected to the gate electrode layer 10 through the first via 101 to form a first capacitor. The second via 102 passes through the second protective layer 60, and the pixel electrode layer 70 is connected to the reference electrode layer 50 through the second via 102 to form a second capacitor. The third via 103 passes through the second protective layer 60, the reference electrode layer 50, and the first protective layer 40, and the pixel electrode layer 70 is connected to the source-drain electrode layer 30 through the third via 103 to form a third capacitor.

[0049] It should be noted that the three-capacitor circuit formed by the first capacitor, the second capacitor, and the third capacitor further increases the capacitance, allowing the display panel 100 to output a larger voltage and improve the reliability of the GIP circuit, thereby making the display of the display panel 100 more reliable.

[0050] In some embodiments, the opening of the first via 101 gradually decreases from the side of the second protective layer 60 to the side of the gate layer 10, and the opening of the third via 103 gradually decreases from the side of the second protective layer 60 to the side of the first protective layer 40.

[0051] It should be noted that the opening of the first via 101 gradually decreases from the side of the second protective layer 60 to the side of the gate layer 10. This design can reduce the physical size of the via while maintaining electrical connection, thereby saving space and adapting to the trend of narrow frame design. In addition, this gradually decreasing opening design can also improve the electrical characteristics of the via, such as reducing the unevenness of capacitance and improving the stability of signal transmission.

[0052] The opening of the third via 103 gradually decreases from the side of the second protective layer 60 to the side of the first protective layer 40. This design also helps to reduce the physical size of the via, optimize space utilization, and improve the yield of the product. At the same time, this design can also improve the electrical characteristics of the via, such as reducing the resistance of the via and improving the efficiency of signal transmission.

[0053] Please refer to Figure 2 In some embodiments, a glass substrate 80 is also included, which is located on the second side 10b of the gate layer 10.

[0054] The application provides a display panel 100, which comprises a gate layer 10, an insulating layer 20, a source-drain layer 30, a first protective layer 40, a reference electrode layer 50, a second protective layer 60, the gate layer 10 has a first side 10a and a second side 10b arranged opposite to each other; the insulating layer 20 is arranged on the first side 10a; the source-drain layer 30 is arranged on the side of the insulating layer 20 away from the gate layer 10; the first protective layer 40 is arranged on the side of the source-drain layer 30 away from the insulating layer 20; the reference electrode layer 50 is arranged on the side of the first protective layer 40 away from the source-drain layer 30; the second protective layer 60 is arranged on the side of the reference electrode layer 50 away from the first protective layer 40; and a pixel electrode layer 70 is arranged on the side of the second protective layer 60 away from the reference electrode layer 50; wherein the pixel electrode layer 70 is connected with at least two of the gate layer 10, the source-drain layer 30 and the reference electrode layer 50 to form at least two capacitors. The application increases the capacitance by arranging at least two capacitors, so that the voltage output of the display panel 100 is larger, and the reliability of the GIP circuit is improved, thereby making the display of the display panel 100 more reliable.

[0055] Please refer to Figure 3In another embodiment of the present application, a display device 1000 is provided, which comprises the display panel 100 described in the above embodiments. Since the display panel 100 has been described in detail in the above embodiments, the display panel 100 in the embodiments of the present application will not be described in detail.

[0056] In order to match the display device of the embodiments of the present application, a corresponding GIP circuit is provided in the embodiments of the present application. For the specific GIP circuit, please refer to Figure 4 The circuit has a signal output line, which is connected to a first thin film transistor, the first thin film transistor is connected to a second thin film transistor through a first signal line and connected to a fourth thin film transistor through a second signal line, the second thin film transistor is connected to a gate driving signal line and a third thin film transistor, a negative ground line is connected to the third thin film transistor and the fourth thin film transistor, and the gate signal line is connected to the first signal line through a first capacitor, a second capacitor and a third capacitor. The first capacitor, the second capacitor and the third capacitor in the embodiments of the present application correspond to the first capacitor, the second capacitor and the third capacitor in the above embodiments.

[0057] Therefore, the three-capacitor circuit formed by the first capacitor, the second capacitor and the third capacitor further increases the capacitance, so that the voltage output of the display panel is larger, the reliability of the GIP circuit is improved, and the display of the display panel is more reliable.

[0058] The display panel and the display device provided in the embodiments of the present application have been described in detail, and specific examples are applied to explain the principles and implementation modes of the present application. The above embodiments are only used to help understand the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a gate layer having a first side and a second side arranged oppositely; an insulating layer arranged on the first side; a source-drain layer arranged on a side of the insulating layer away from the gate layer; a first protective layer arranged on a side of the source-drain layer away from the insulating layer; a reference electrode layer arranged on a side of the first protective layer away from the source-drain layer; a second protective layer arranged on a side of the reference electrode layer away from the first protective layer; a pixel electrode layer arranged on a side of the second protective layer away from the reference electrode layer; wherein the pixel electrode layer is connected with at least two of the gate layer, the source-drain layer and the reference electrode layer to form at least two capacitors.

2. The display panel of claim 1, wherein, The pixel electrode layer is connected with the gate layer to form a first capacitor, and the pixel electrode layer is connected with the reference electrode layer to form a second capacitor.

3. The display panel of claim 2, wherein, The display panel further comprises a first via and a second via, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form the first capacitor, the second via passes through the second protective layer, and the pixel electrode layer is connected with the reference electrode layer through the second via to form the second capacitor.

4. The display panel of claim 1, wherein, The pixel electrode layer is connected with the gate layer to form a first capacitor, and the pixel electrode layer is connected with the source-drain layer to form a third capacitor.

5. The display panel of claim 4, wherein, The display panel further comprises a first via and a third via, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form the first capacitor, the third via passes through the second protective layer, the reference electrode layer and the first protective layer, and the pixel electrode layer is connected with the source-drain layer through the third via to form the third capacitor.

6. The display panel of claim 1, wherein, The pixel electrode layer is connected with the gate layer to form a first capacitor, the pixel electrode layer is connected with the reference electrode layer to form a second capacitor, and the pixel electrode layer is connected with the source-drain layer to form a third capacitor.

7. The display panel of claim 6, wherein, The display panel further comprises a first via, a second via and a third via, the first via passes through the second protective layer, the reference electrode layer, the first protective layer, the source-drain layer and the insulating layer, the pixel electrode layer is connected with the gate layer through the first via to form the first capacitor, the second via passes through the second protective layer, and the pixel electrode layer is connected with the reference electrode layer through the second via to form the second capacitor, the third via passes through the second protective layer, the reference electrode layer and the first protective layer, and the pixel electrode layer is connected with the source-drain layer through the third via to form the third capacitor.

8. The display panel of claim 7, wherein, An opening of the first via gradually decreases from the side of the second protective layer to the side of the gate layer, and an opening of the third via gradually decreases from the side of the second protective layer to the side of the first protective layer.

9. The display panel of claim 1, wherein, The display panel further comprises a glass substrate arranged on the second side of the gate layer.

10. A display device, characterized by comprising: The display panel comprises the display panel according to any one of claims 1 to 9. The display panel comprises the display panel according to any one of claims 1 to 9.

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