Multi-channel flying probe data acquisition system based on ARM + FPGA architecture

Abstract

The utility model belongs to the technical field of electronic circuits, and particularly relates to a multichannel flying probe data acquisition system based on an ARM + FPGA (Field Programmable Gate Array) architecture, which sends instructions through an upper computer system, controls an ARM to reset, initialize and analyze the instructions, and sends analyzed test instructions to an FPGA through PCIE (Peripheral Component Interface Express) communication. And the FPGA switches a resistance method test mode or a capacitance method test mode according to an instruction, configures a test gear or a DDS signal frequency, and outputs a signal source to a corresponding probe channel through a GPIO control circuit matrix switch. The FPGA also controls the ADC data acquisition module through SPI communication to obtain a probe access voltage signal, uploads test data to the ARM for classification, calculation processing and caching, and finally forwards the test data to an upper computer system for storage, analysis and display. The system combines the real-time performance of the ARM and the parallel processing advantages of the FPGA, realizes multi-channel fast switching and efficient parallel data processing, and has the characteristics of fast response speed, low time delay, fast data acquisition and transmission, high expandability and the like.

Description

TECHNICAL FIELD

[0001] The utility model belongs to electronic circuit technical field, concretely relates to a multi -channel flying probe data acquisition system based on ARM + FPGA architecture. BACKGROUND

[0002] At present, the flying probe test data acquisition system mainly adopts MCU as the core processor, and communicates with the data acquisition board through the serial port or SPI interface. Under this architecture, the MCU is responsible for receiving the instructions of the host computer, and controls the data acquisition board to perform the corresponding test operation after analyzing the instructions. The data acquisition board is responsible for collecting test data, and returns the data to the MCU, which is then uploaded to the host computer for subsequent processing.

[0003] However, the existing flying probe test data acquisition system has many deficiencies. First, due to the limited processing capacity of MCU, the system response time is long, which cannot meet the demand of high-speed testing. Second, the data transmission rate of serial port or SPI communication mode is low, resulting in low test efficiency. In addition, the existing system has poor scalability and is difficult to adapt to the changes of future testing needs. Therefore, there is an urgent need for a new type of flying probe data acquisition system to solve the problems existing in the prior art. UTILITY MODEL CONTENT

[0004] The purpose of the utility model is to provide a multi-channel flying probe data acquisition system based on ARM + FPGA architecture to solve the problems of long response time, low test efficiency and low data communication rate of the existing flying probe test data acquisition system.

[0005] The utility model realizes the above-mentioned purpose through the following technical scheme:

[0006] The utility model provides a multi-channel flying probe data acquisition system based on ARM + FPGA architecture, which comprises:

[0007] A host computer system for generating control instructions;

[0008] An ARM embedded system connected with the host computer system through Ethernet for receiving and analyzing the control instructions;

[0009] An FPGA connected with the ARM embedded system through PCIE communication for switching the resistance method test mode or the capacitance method test mode according to the analyzed control instructions;

[0010] A resistance method test circuit integrated in the FPGA for generating a voltage signal in the resistance method test mode;

[0011] A capacitance method test circuit integrated in the FPGA for generating a DDS signal in the capacitance method test mode;

[0012] The ADC data acquisition module is connected with the FPGA through SPI communication, and is used for collecting voltage signals or DDS signals transmitted through the probe channel, and uploading the collected test data to the upper computer system.

[0013] Further, the system further comprises a circuit matrix switch connected with the GPIO control circuit of the FPGA, and used for switching the voltage source, the current source or the DDS signal source to the corresponding probe channel according to the control signal of the FPGA.

[0014] Further, the resistance method test circuit comprises circuit elements for voltage insulation and circuit conduction test, and a voltage signal channel output to the ADC data acquisition module.

[0015] Further, the capacitance method test circuit comprises a DDS signal generator, and a circuit for switching the DDS signal source to the probe channel through the switch.

[0016] Further, the ADC data acquisition module has a plurality of channels, each channel corresponding to a probe channel, and used for collecting waveform data on the probe channel.

[0017] Further, the circuit matrix switch is specifically a programmable switch matrix, and used for dynamically switching the voltage source, the current source or the DDS signal source to any one of the probe channels according to the control signal of the FPGA.

[0018] The beneficial effects of the utility model lie in:

[0019] The application combines the real-time performance of the embedded CPU ARM and the parallel processing advantage of the FPGA, implements the signal generation and collection part on the FPGA, and processes the functional logic on the ARM, so that the multi-channel fast switching and efficient parallel data processing of the flying probe system are realized. This design not only significantly improves the response speed and test efficiency of the system, but also greatly improves the data collection and transmission speed. In addition, the scalability of the system is also significantly improved, and the system can better adapt to the changes of future test requirements. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is the overall structure schematic diagram of the multi-channel flying probe data acquisition system based on ARM+FPGA architecture provided by the utility model. DETAILED DESCRIPTION

[0021] The present application is described in further detail below in conjunction with the accompanying drawings. It is necessary to point out that the following specific implementation methods are only used to further illustrate the present application and cannot be understood as limiting the scope of protection of the present application. Technicians in this field can make some non-essential improvements and adjustments to the present application based on the above application content.

[0022] Example 1

[0023] like Figure 1 As shown, this embodiment proposes a multi-channel flying probe data acquisition system based on ARM+FPGA architecture, which includes a host computer system, an ARM embedded system, an FPGA (field programmable gate array), a resistance method test circuit, a capacitance method test circuit, an ADC (analog-to-digital converter) data acquisition module and a circuit matrix switch.

[0024] Among them, the host computer system is used to generate control instructions; the ARM embedded system is connected to the host computer system via Ethernet to receive and parse control instructions; the FPGA is connected to the ARM embedded system via PCIE communication to switch between the resistance method test mode and the capacitance method test mode according to the parsed control instructions; the resistance method test circuit is integrated in the FPGA to generate a voltage signal in the resistance method test mode; the capacitance method test circuit is integrated in the FPGA to generate a DDS signal in the capacitance method test mode; the ADC data acquisition module is connected to the FPGA via SPI communication to collect the voltage signal or DDS signal transmitted through the probe channel, and upload the collected test data to the host computer system through the FPGA communication terminal; the circuit matrix switch is connected to the GPIO control circuit of the FPGA to switch the voltage source, current source or DDS signal source to the corresponding probe channel according to the control signal of the FPGA.

[0025] In this embodiment, the host computer system serves as the control center of the entire test system, and the host computer system establishes communication with the ARM embedded system via Ethernet. Users can send test instructions, including test type, test parameters, etc. through the host computer interface.

[0026] After receiving the command from the host computer, the ARM embedded system first performs reset and initialization operations, and then parses the test requirements in the command. After parsing, the ARM sends the test command to the FPGA through the PCIE communication interface.

[0027] FPGA, as one of the core processing units of the system, receives the test instruction issued by ARM, and switches the resistance method or the capacitance method test mode according to the instruction requirement. In the resistance method test mode, FPGA configures the corresponding test gear; in the capacitance method test mode, FPGA configures the frequency of the DDS (Direct Digital Synthesis) signal source. After the configuration is completed, FPGA converts the test instruction into a serial-parallel conversion, and generates a plurality of parallel channel control signals. These signals control the circuit matrix switch through the GPIO (General-Purpose Input / Output) interface, and output the voltage source, current source or DDS signal source to the corresponding probe channel.

[0028] In the embodiment, the real-time performance of ARM ensures that the system can quickly respond to the instructions of the host computer; the parallel processing capability of FPGA greatly improves the speed of collecting and processing test data; at the same time, due to the programmability of FPGA, the system is easy to expand and upgrade to adapt to the changes of future test requirements.

[0029] More specifically, the resistance method test circuit and the capacitance method test circuit in the embodiment are respectively used for the voltage insulation and circuit conduction test of the flying probe and the generation of the DDS signal source. In the resistance method test, the circuit outputs a specific voltage signal to the ADC data acquisition module; in the capacitance method test, the DDS signal source is switched and output to the corresponding probe channel through the switch.

[0030] In addition, the ADC data acquisition module is responsible for collecting the waveform data of the corresponding channel of the flying probe probe. After receiving the control signal of FPGA, the ADC module starts collecting data, and uploads the collected test data to FPGA through SPI (Serial Peripheral Interface) communication.

[0031] Further preferably, the resistance method test circuit includes circuit elements for voltage insulation and circuit conduction test, and a voltage signal channel output to the ADC data acquisition module.

[0032] Further preferably, the capacitance method test circuit includes a DDS signal generator (DDS signal source) and a circuit for switching and outputting the DDS signal source to the probe channel through the switch.

[0033] Further preferably, the ADC data acquisition module has a plurality of channels, each channel corresponding to a probe channel, for collecting waveform data on the probe channel.

[0034] Further preferably, the circuit matrix switch is specifically a programmable switch matrix, used for dynamically switching the voltage source, the current source or the DDS signal source to any one probe channel according to the control signal of the FPGA.

[0035] Working principle: After the host computer sends a test instruction, the ARM embedded system is responsible for parsing the instruction and controlling the FPGA to perform corresponding test configuration. The FPGA switches the test mode according to the test requirements and configures the related parameters, and then controls the circuit matrix switch through the GPIO interface to output the signal source to the specified probe channel. The ADC data acquisition module acquires test data under the control of the FPGA and uploads the data to the FPGA. After the FPGA receives the data, it forwards the data to the ARM embedded system through the PCIE interface. The ARM system classifies, calculates and processes the data, and then uploads the data to the host computer system through Ethernet for storage, analysis and display.

[0036] Although the embodiments of the present application have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and modifications can be made to these embodiments without departing from the principles and spirits of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A multi-channel flying probe data acquisition system based on ARM+FPGA architecture, characterized in that, The system comprises: a host computer system for generating control instructions; an ARM embedded system connected with the host computer system through Ethernet for receiving and analyzing the control instructions; an FPGA connected with the ARM embedded system through PCIE communication for switching resistance method test mode or capacitance method test mode according to the analyzed control instructions; a resistance method test circuit integrated in the FPGA for generating a voltage signal in the resistance method test mode; a capacitance method test circuit integrated in the FPGA for generating a DDS signal in the capacitance method test mode; an ADC data acquisition module connected with the FPGA through SPI communication for collecting the voltage signal or the DDS signal transmitted through a probe channel and uploading the collected test data to the host computer system.

2. The multi-channel flying probe data acquisition system based on ARM+FPGA architecture according to claim 1, characterized in that, The system further comprises a circuit matrix switch connected with a GPIO control circuit of the FPGA for switching a voltage source, a current source or a DDS signal source to a corresponding probe channel according to a control signal of the FPGA.

3. The multi-channel flying probe data acquisition system based on ARM+FPGA architecture according to claim 1, characterized in that, The resistance method test circuit comprises circuit elements for voltage insulation and circuit conduction test, and a voltage signal channel output to the ADC data acquisition module.

4. The multi-channel flying probe data acquisition system based on ARM+FPGA architecture according to claim 1, characterized in that, The capacitance method test circuit comprises a DDS signal generator and a circuit for switching the DDS signal source to the probe channel through a switch.

5. The multi-channel flying probe data acquisition system based on ARM+FPGA architecture according to claim 4, characterized in that, The ADC data acquisition module has multiple channels, each corresponding to a probe channel, for collecting waveform data on the probe channel.

6. The multi-channel flying probe data acquisition system based on ARM+FPGA architecture according to claim 2, characterized in that, The circuit matrix switch is specifically a programmable switch matrix for dynamically switching the voltage source, the current source or the DDS signal source to any one of the probe channels according to the control signal of the FPGA.

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