Miniaturized PCIe bridging module based on XMC interface

Abstract

The utility model discloses a miniaturized PCIe bridging module based on an XMC interface, which comprises an XMC plate type back plate, a PEX8717 bridge piece unit, a power supply conversion unit, a clock signal unit, an FPGA unit and an XMC connector, the power supply conversion unit, the PEX8717 bridge piece unit, the clock signal unit and the FPGA unit are all integrated on the standard XMC plate type back plate, and the XMC connector is connected with the standard XMC plate type back plate. And the power supply conversion unit, the clock signal unit and the FPGA unit are arranged on the XMC connector and are connected with the PEX8717 bridge sheet unit through the XMC connector. According to the scheme of the utility model, the internal and external butt joint of the module is realized based on the XMC interface, the structure is simple, the realization is easy, the signal transmission efficiency and precision are high, the vibration resistance of the XMC connector is good, the pinhole connection mode of the XMC connector is firmer and firmer than that of PCIE interface connectors such as golden fingers, and the use requirements of military electronic equipment in severe environments can be met.

Description

TECHNICAL FIELD

[0001] The utility model belongs to PCIe bridging field, concretely relates to a miniaturized PCIe bridging module based on XMC interface. BACKGROUND

[0002] As an important method of server or system upgrade, horizontal expansion is becoming more and more popular, and more and more manufacturers use this method to upgrade products. Traditional network, InfiniBand and PCIE can be used to help realize horizontal expansion. As an expansion bus in traditional computer systems, the ecology and technical foundation of PCIe bus are very rich, and with the continuous development of its switching technology, it has gradually become a powerful means of inter-system communication.

[0003] Various computer centers in the commercial field use a variety of interconnection architectures and technologies. Typical foreign technologies include Intel's CXL high-speed interface, OpenCAPI launched by the Power Alliance, and GEN-Z launched by AMD, which have good features such as flexible expansion of multiple high-speed buses and software configuration. Typical technologies at home and abroad include products launched by public cloud manufacturers such as Alibaba and Huawei, which all use the concept of high-speed PCIe heterogeneous computing.

[0004] In the military field, electronic information systems mainly use Ethernet to establish an interconnection architecture. However, with the demand for more efficient, lower latency, and more powerful communication between computing and storage function nodes in weapon equipment, simple Ethernet switching cannot meet the application requirements of certain specific scenarios, and there is an urgent need to use PCIe bus for upgrade.

[0005] In addition to advantages in speed bandwidth, latency and other indicators, PCIe-based switching buses can achieve flexible resource allocation and combination, providing more flexible resource management and performance enhancement. With the continuous improvement and development of PCIe switching chip-level and system-level solutions at home and abroad, it can serve as a powerful supplement to military equipment information system infrastructure.

[0006] However, existing PCIe bridges are mostly commercial or industrial modules, which do not meet the requirements of military electronic equipment used in harsh environments. At the same time, in view of the demand for high-speed transmission, low latency, and functional cross-fusion of existing electronic information systems, research on miniaturized PCIe bridging modules based on XMC interface is needed. SUMMARY

[0007] To solve the above technical defects in the prior art, the utility model provides a miniaturized PCIe bridging module based on XMC interface.

[0008] The technical solution for achieving the purpose of the utility model is:

[0009] The application discloses a miniaturized PCIe bridge module based on an XMC interface, which comprises an XMC board type backboard, a PEX8717 bridge piece unit, a power conversion unit, a clock signal unit and an FPGA unit.

[0010] The power conversion unit, the PEX8717 bridge piece unit, the clock signal unit and the FPGA unit are integrated on the standard XMC board type backboard.

[0011] Further, the XMC connector is further included.

[0012] The power conversion unit, the clock signal unit and the FPGA unit are arranged on the XMC connector and connected with the PEX8717 bridge piece unit through the XMC connector.

[0013] Further, the XMC connector receives external +5V and +3.3V voltages as power supply and transmits the voltages to the power conversion unit.

[0014] The power conversion unit is unidirectionally connected with the PEX8717 bridge piece unit and provides +5V and +3.3V power supply for the PEX8717 bridge piece unit.

[0015] The clock signal unit is unidirectionally connected with the PEX8717 bridge piece unit and provides clock signals for the PEX8717 bridge piece unit.

[0016] The FPGA unit is connected with the PEX8717 bridge piece unit and is used for completing configuration loading of the PEX8717 bridge piece unit.

[0017] Further, the PEX8717 bridge piece unit, the power conversion unit, the clock signal unit and the FPGA unit are bridged through the XMC connector and an external host.

[0018] Further, the XMC connector is an XMC plug and an XMC socket, the XMC socket is of an XMC-0619-03Z type and the XMC plug is of an XMC-0619-07T type.

[0019] Further, the power conversion unit comprises two DC / DC converters and an LDO power supply SM74401RGW.

[0020] The two DC / DC converters are connected in parallel, and one of the DC / DC converters is connected in series with the LDO power supply SM74401RGW.

[0021] Further, the clock signal unit comprises a first capacitor, a second capacitor and a first inductor.

[0022] The first capacitor and the second capacitor are connected in parallel, one end of the first capacitor is connected with the first inductor and inputs a clock signal, the other end of the first inductor is connected with a 3.3V voltage, and the other end of the first capacitor is grounded.

[0023] Compared with the prior art, the utility model has the beneficial effects that:

[0024] The utility model discloses a scheme based on XMC interface realizes the internal and external butt joint of module, simple structure, easy to realize, signal transmission efficiency and precision are higher, and XMC connector is good in vibration resistance, and compared with the pinhole connection mode connection of PCIE interface connector such as golden finger, is more solid and reliable, can satisfy the use requirement of military electronic equipment under the bad environment.

[0025] The utility model will be described in further detail below in combination with the drawings and specific embodiments. DRAWINGS

[0026] Figure 1 It is the miniaturization PCIe bridging module architecture schematic drawing of the utility model based on XMC interface.

[0027] Figure 2 It is the power conversion unit circuit topology drawing of the utility model.

[0028] Figure 3 It is the HCE4622 chip typical application circuit diagram of the power conversion unit of the utility model.

[0029] Figure 4 It is the SM74401RGW chip typical application circuit diagram of the power conversion unit of the utility model.

[0030] Figure 5 It is the clock circuit power supply schematic drawing of the utility model.

[0031] Figure 6 It is the bridging module board card structure size drawing of the utility model. EMBODIMENT

[0032] It is easy to understand that according to the technical scheme of the utility model, the general technical personnel of the art can imagine the multiple embodiments of the utility model without changing the essential spirit of the utility model. Therefore, the following specific embodiments and drawings are only the exemplary description of the technical scheme of the application, and should not be regarded as the whole or the limitation or the definition of the technical scheme of the utility model. On the contrary, the purpose of providing these embodiments is to make the technical personnel of the art more thoroughly understand the utility model. The preferred embodiments of the utility model are described in detail below in combination with the drawings, wherein the drawings constitute a part of the application and are used together with the embodiments of the utility model to explain the innovative concept of the application.

[0033] Embodiment

[0034] The miniaturized PCIe bridge module provides an NTB bridging function, and the core significance of the NTB bridge is to solve the problem of different device resource allocation, thereby causing the problem that a data packet with the address cannot be correctly routed. The NTB bridge can completely translate data of the data packet when the data packet is transmitted in different systems.

[0035] In combination Figure 1 The miniaturized PCIe bridge module based on an XMC interface comprises an XMC board backboard, a PEX8717 bridge unit, a power conversion unit, a clock signal unit, an FPGA unit and an XMC connector.

[0036] The power conversion unit, the PEX8717 bridge unit, the clock signal unit and the FPGA unit are integrated on the standard XMC board backboard.

[0037] The power conversion unit, the clock signal unit and the FPGA unit are arranged on the XMC connector and connected with the PEX8717 bridge unit through the XMC connector.

[0038] The scheme of the utility model integrates the PCIe chip into the host through the XMC connector, realizes multi-host interconnection, has the multi-host PCI Express switching function, has the advantages of high throughput, low delay, multi-host architecture, high data rate propagation, device borrowing and the like.

[0039] The PEX8717 bridge unit is the core of the bridge module and provides the multi-host interconnection function. The PEX8717 bridge chip in the embodiment supports 16 channels, 10 ports and PCIe3.0, integrates 8.0GT / s SerDes, has a typical power consumption of 4.9W, supports access control services and dynamic link width control. The chip integrates a DMA engine, supports multi-host and failover, the 8717 chip architecture supports data packet pass-through, and the maximum delay is 138ns (x4 to x4). The 10 ports of the PEX 8717 can be configured as channel widths of x1, x2, x4 or x8, flexible buffer allocation and flexible data packet flow control of the device, and the throughput of the application program can be maximized.

[0040] The XMC connector receives external +5V and +3.3V voltages as power supply voltages and transmits the voltages to the power conversion unit.

[0041] The power conversion unit is unidirectionally connected with the PEX8717 bridge unit and provides +5V and +3.3V power supplies for the PEX8717 bridge unit.

[0042] The clock signal unit is unidirectionally connected with the PEX8717 bridge unit, and provides a clock signal for the PEX8717 bridge unit.

[0043] The FPGA unit is connected with the PEX8717 bridge unit, and is used for completing configuration loading of the PEX8717 bridge unit.

[0044] In combination Figure 2 , the PEX8717 bridge unit, the power conversion unit, the clock signal unit and the FPGA unit are bridged through an XMC connector and an external host. In the embodiment, the XMC connector is in the form of an XMC daughter card and is connected with the HOST host, the bridging device is an XMC socket, the HOST host module is an XMC plug, the XMC connector has a contact spacing of 1.27mm, the XMC connector is the XMC plug and the XMC socket, the XMC socket is of the model XMC-0619-03Z, and the XMC plug is of the model XMC-0619-07T.

[0045] In combination Figure 3 , the power conversion unit includes two DC / DC converters, a DC / DC converter HCE4622MB of Qianxing Huachuang and an LDO power supply SM74401RGW of Shenzhen Guowei Electronics;

[0046] The two DC / DC converters are connected in parallel, and one of the DC / DC converters is connected in series with the LDO power supply SM74401RGW.

[0047] The HCE4622MB is a dual-channel 2.5A output DC / DC converter, adopts BGA packaging, and has a built-in switching controller, power FET, inductor and all supporting elements in the package. The input voltage range of the HCE4622MB is 3.6V-20V, each channel can output a voltage of 0.6V-5.5V, the voltage adjustment range is ±1.5%, the high-efficiency design of the device enables each channel to provide a continuous output current of 2.5A and a peak output current of 3A, and only a large-capacity capacitor needs to be externally connected at the input and output. The HCE4622MB supports selectable burst mode operation and continuous output voltage follow-up function. The high-frequency switching and current control mode function can quickly respond when the load changes linearly or otherwise without affecting stability. The typical application circuit of the HCE4622MB is as shown in Figure 4

[0048] ​SM74401RGW is a LDO voltage regulator, which can adjust the output voltage range to 0.8V-3.6V, the maximum output current is 3A, and the maximum leakage voltage is 300mV when the output current is 3A. The chip mainly consists of a reference voltage module, a soft start module, an error amplifier module, a power tube, a temperature protection module and a current limiting module. The reference voltage module provides a reference voltage and a bias current for the chip, the error amplifier, the power tube and the voltage dividing resistor constitute the feedback loop of the LDO, the temperature protection module provides over-temperature protection and recovery voltage for the chip, the current limiting module provides over-current protection, and the soft start module can realize the adjustment of the start time through an external capacitor. Its typical application circuit is shown in Figure 5

[0049] The clock circuit of the scheme includes PCIe chip, FPGA configuration loading interface, and the electromagnetic compatibility is considered in the design, the clock power supply is filtered and designed, the output adopts resistance for impedance matching, and the use requirements in complex electromagnetic environment can be met.

[0050] In combination Figure 6 , the clock signal unit power supply topology of the embodiment includes a first capacitor C1, a second capacitor C2 and a first inductor L1;

[0051] The first capacitor C1 and the second capacitor C2 are connected in parallel, one end of the first capacitor C1 is connected with the first inductor L1 and inputs the clock signal, the other end of the first inductor L1 is connected with a 3.3V voltage, and the other end of the first capacitor C1 is grounded.

[0052] The topology can guarantee that the clock output is stable and reliable. For a single-ended clock, the clock is directly input to an FPGA or a PCIe chip after being output by a crystal oscillator or being divided into multiple clocks by a clock driver, including a loading circuit clock, and a series resistance is used to reduce signal reflection and improve signal quality.

[0053] The FPGA unit of the scheme provides a PCIe chip unit configuration function, and the FPGA unit adopts an XCZU7EV chip of xilinx company.

[0054] In addition, in terms of thermal design, a heat-conducting rubber pad is pasted between a heat dissipation device and a shell in the module, so that heat is transmitted to the shell as soon as possible, and a heat dissipation fin is arranged on the outer heat dissipation surface of the module to increase the heat dissipation area of the module.

[0055] The above embodiments show and describe the basic principles and main features of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the utility model, and various changes and improvements can be made to the utility model without departing from the spirit and scope of the invention, and these changes and improvements all fall within the scope of the claimed invention.​

Claims

1. A miniaturized PCIe bridge module based on XMC interface, characterized in that, The XMC board type backboard, the PEX8717 bridge piece unit, the power conversion unit, the clock signal unit and the FPGA unit are integrated on the standard XMC board type backboard. The XMC connector is further included.

2. The XMC interface based miniaturized PCIe bridge module according to claim 1, characterized in that, The power conversion unit, the clock signal unit and the FPGA unit are arranged on the XMC connector and connected with the PEX8717 bridge piece unit through the XMC connector. The XMC connector receives external +5V and +3.3V voltages as power supply and transmits them to the power conversion unit.

3. The XMC interface based miniaturized PCIe bridge module according to claim 2, characterized in that, The power conversion unit is unidirectionally connected with the PEX8717 bridge piece unit and provides +5V and +3.3V power supply for the PEX8717 bridge piece unit. The clock signal unit is unidirectionally connected with the PEX8717 bridge piece unit and provides clock signal for the PEX8717 bridge piece unit. The FPGA unit is connected with the PEX8717 bridge piece unit and is used for completing configuration loading of the PEX8717 bridge piece unit. The PEX8717 bridge piece unit, the power conversion unit, the clock signal unit and the FPGA unit are bridged through the XMC connector and an external host.

4. The XMC interface based miniaturized PCIe bridge module of claim 2, wherein, The XMC connector is an XMC plug and an XMC socket, the XMC socket is of the XMC-0619-03Z type and the XMC plug is of the XMC-0619-07T type.

5. The XMC interface based miniaturized PCIe bridge module according to claim 4, characterized in that, The power conversion unit includes two DC / DC converters and an LDO power supply SM74401RGW.

6. The XMC interface based miniaturized PCIe bridge module of claim 1, wherein, The two DC / DC converters are connected in parallel, and one of the DC / DC converters is connected in series with the LDO power supply SM74401RGW. The clock signal unit includes a first capacitor (C1), a second capacitor (C2) and a first inductor (L1).

7. The XMC interface based miniaturized PCIe bridge module of claim 1, wherein, The first capacitor (C1) and the second capacitor (C2) are connected in parallel, one end of the first capacitor (C1) is connected with the first inductor (L1) and inputs clock signal, the other end of the first inductor (L1) is connected with a 3.3V voltage, and the other end of the first capacitor (C1) is grounded. ​

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