Packaging structure suitable for multiple types of MOS chips

Abstract

The utility model discloses a packaging structure suitable for multiple types of MOS chips, the packaging structure comprises a chip packaging frame, one side of the top end of the chip packaging frame is provided with an insulating cushion block, and the other side of the top end of the chip packaging frame is provided with a chip packaging assembly. A copper sheet matched with the chip packaging assembly is arranged at the top end of the insulating cushion block; the structure is simple, the design is reasonable, the problem of uneven tin thickness between the copper sheet and the MOS tube bare chip is solved, the defect that stress concentration points are easy to form due to the fact that tin drawn below the grid bus is too thin is avoided, the defect of tin drawn cavities below the copper sheet is overcome due to the kidney-shaped through hole design of the copper sheet, and the reliability of the structure is improved. The half-waist-shaped molding compound exhaust hole at the chip connecting part of the copper sheet can solve the hole defect of EMC; in addition, the copper sheet adopts a non-bending plane design structure, so that the stress condition is simplified, the manufacturing cost input of the packaging structure is greatly reduced, automation and batch integration are facilitated, the production cost is saved, and the product competitiveness is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor packaging, specifically to a multi-MOS chip packaging structure. BACKGROUND

[0002] With the rapid development of automotive electronics, industrial control, new energy and other fields, the performance requirements of power devices are increasingly improved, especially in the vehicle-grade application, the reliability of MOS tube packaging is put forward more strict requirements. In the development process of power device packaging technology, the design of packaging structure not only meets the needs of electrical performance and heat dissipation performance, but also ensures the controllable cost; among them, the lead frame as the carrier packaging form, because it has larger heat dissipation area and good electrical characteristics, occupies an important position in the field of power device packaging; at the same time, with the development of electronic products to miniaturization, light and thin, the packaging size is continuously reduced, which puts forward higher requirements on packaging process, especially in the thickness control and uniformity of chip tin layer, lower tin layer, these factors directly affect the reliability and performance of the product.

[0003] Disadvantages of prior art:

[0004] At present, the power device packaging generally adopts the packaging form of lead frame combined with copper sheet, which improves the heat dissipation efficiency by reserving a large area of heat dissipation area at the bottom of the lead frame, and realizes electrical connection and heat conduction by using copper sheet; this packaging structure has significant advantages in performance, size and price, and can better balance the heat dissipation performance and cost control requirements. In actual production, due to the diversification of MOS chip size and the complex and variable pattern layout of chip gate bus, the industry generally adopts the solution of preparing concave points on the copper sheet, which avoids the stress concentration point of gate bus through concave point design to reduce the stress damage of gate bus in the packaging process; this scheme solves the problem of gate bus stress concentration to a certain extent through one-to-one customized design, that is, a single copper sheet corresponds to a single chip packaging route, which solves the problem of gate bus stress concentration to a certain extent.

[0005] However, the existing packaging technical solutions have multiple limitations. First, with the continuous reduction of the packaging size, the product reliability faces severe challenges, especially in the humidity sensitivity test, most products are difficult to meet the MSL-3 level requirements, not to mention the higher MSL-1 standard; second, the one-to-one customized packaging solution can solve the gate bus stress concentration problem, but this way causes each chip to develop a corresponding special copper sheet and mold, not only greatly increases the mold investment cost, but also causes the production management to be complicated and the manufacturing efficiency to be low; in addition, since each chip needs independent packaging process flow and quality control standard, this way also brings problems such as frequent production line switching and difficult inventory management, which seriously restricts the reduction of product cost and the improvement of production efficiency, and it is difficult to meet the growing demand of the market for high-performance, low-cost packaged devices. Practical new type content

[0006] The utility model discloses a kind of applicable multiple MOS chip packaging structures, to solve the problems raised in the above background art.

[0007] To achieve the above object, the utility model provides the following technical scheme: a kind of applicable multiple MOS chip packaging structures, the packaging structure includes chip packaging frame, the top one side of the chip packaging frame is provided with insulating pad, the top other side of the chip packaging frame is provided with chip packaging component, and the top of the insulating pad is provided with the copper sheet that cooperates with the chip packaging component.

[0008] Preferably, the top outside of the copper sheet is provided with epoxy plastic sealing material matched with the chip packaging frame, and a third tin layer is arranged between one side of the bottom end of the copper sheet and the chip packaging frame.

[0009] Preferably, the chip packaging component includes a MOS tube bare chip arranged at the top one side of the chip packaging frame, a first tin layer is arranged between the MOS tube bare chip and the chip packaging frame, and a second tin layer is arranged between the MOS tube bare chip and the copper sheet.

[0010] Preferably, the chip packaging frame includes a base island arranged at the bottom end of the insulating pad, the base island is connected to the middle of the bottom end of the copper sheet through the chip packaging component at the top end, and a pin is arranged at one side of the base island.

[0011] Preferably, the insulating pad and the base island are fixedly connected through red glue, the base island and the MOS tube bare chip are fixedly connected through the first tin layer, and the pin is fixedly connected with the copper sheet through the third tin layer.

[0012] Preferably, the copper sheet comprises a chip connecting portion arranged at the top end of the insulating pad, the chip connecting portion is arranged in a planar structure, and one side of the chip connecting portion is provided with a pin connecting portion.

[0013] Preferably, a plurality of first waist-shaped through holes are arranged at one side of the top end of the chip connecting portion, a plurality of second waist-shaped through holes are arranged at the other side of the top end of the chip connecting portion, and a half waist-shaped through hole is arranged at one side of the pin connecting portion.

[0014] Preferably, a first contact plane matched with the MOS tube bare chip is arranged at the bottom end of the chip connecting portion, a flow groove is arranged at one side of the first contact plane, and a second contact plane matched with the third tin drawing layer is arranged at one side of the bottom end of the pin connecting portion.

[0015] Preferably, the distances between the two ends of the first waist-shaped through hole and the flow groove are equal, and the horizontal distance between the half waist-shaped through hole and the pin is greater than a first preset distance.

[0016] Preferably, the height of the insulating pad is equal to the sum of the heights of the first tin drawing layer, the MOS tube bare chip and the second tin drawing layer, and the horizontal distance between the insulating pad and the MOS tube bare chip is greater than a second preset distance.

[0017] Compared with the prior art, the utility model has the beneficial effects that:

[0018] The MOS chip packaging structure is suitable for multiple MOS chips, solves the problem of uneven tin thickness between the copper sheet and the MOS tube bare chip, avoids the defect that the tin drawing under the gate bus is too thin and stress concentration points are easily formed, the waist-shaped through hole of the copper sheet solves the tin drawing hollow defect under the copper sheet, the half waist-shaped plastic sealing material exhaust hole of the chip connecting portion of the copper sheet can solve the EMC hollow defect, in addition, the copper sheet adopts a bending-free planar design structure, the stress condition is simplified, through the simple and reliable copper sheet design, the manufacturing cost investment of the packaging structure can be greatly reduced, automation and batch integration are facilitated, production cost is saved, and product competitiveness is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a structure schematic view of a MOS chip packaging structure suitable for multiple MOS chips.

[0020] Figure 2 It is a local structure schematic view of a MOS chip packaging structure suitable for multiple MOS chips.

[0021] Figure 3 It is a structure schematic view of a MOS chip packaging structure and a jig.

[0022] Figure 4It is a structural schematic view of a chip packaging frame suitable for a plurality of MOS chip packaging structures.

[0023] Figure 5 It is another angle structural schematic view of a chip packaging frame suitable for a plurality of MOS chip packaging structures.

[0024] Figure 6 It is another angle partial structural schematic view of a chip packaging frame suitable for a plurality of MOS chip packaging structures.

[0025] Figure 7 It is a structural schematic view of a copper sheet suitable for a plurality of MOS chip packaging structures.

[0026] Figure 8 It is another angle structural schematic view of a copper sheet suitable for a plurality of MOS chip packaging structures.

[0027] In the figure: 1, chip packaging frame; 101, base island; 102, pin; 2, insulating pad; 3, copper sheet; 301, chip connecting part; 3011, first contact plane; 3012, overflow groove; 3013, second contact plane; 302, pin connecting part; 303, first waist-shaped through hole; 304, second waist-shaped through hole; 305, half waist-shaped through hole; 4, second tin drawing layer; 5, MOS tube bare chip; 6, first tin drawing layer; 7, epoxy plastic sealing material; 8, third tin drawing layer; 9, first jig; 10, second jig. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0030] In the description of the patent, it is necessary to explain that, unless otherwise expressly specified and limited, the terms "mounting", "connecting", "setting" should be understood broadly, for example, it can be fixedly connected, set, or detachably connected, set, or integrally connected, set. For ordinary skilled in the art, the specific meaning of the above terms in the patent can be understood according to the specific circumstances.

[0031] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the utility model, the meaning of "several" is two or more than two, unless otherwise expressly specified and limited.

[0032] Embodiment

[0033] Please refer to Figures 1-8 As shown in the utility model provides a kind of applicable multiple MOS chip packaging structure technical scheme: packaging structure includes chip packaging frame 1, the top one side of chip packaging frame 1 is provided with insulating pad 2, the top other side of chip packaging frame 1 is provided with chip packaging assembly, and the top of insulating pad 2 is provided with copper sheet 3 matched with chip packaging assembly, the top outside of copper sheet 3 is provided with epoxy plastic encapsulation material 7 matched with chip packaging frame 1, third tin layer 8 is arranged between the side of copper sheet 3 bottom and chip packaging frame 1, chip packaging assembly includes the MOS tube bare chip 5 of being arranged in the top one side of chip packaging frame 1, and first tin layer 6 is arranged between MOS tube bare chip 5 and chip packaging frame 1, second tin layer 4 is arranged between MOS tube bare chip 5 and copper sheet 3.

[0034] Further, the chip packaging frame 1 comprises a base island 101 arranged at the bottom end of the insulating pad 2, the top end of the base island 101 is connected with the middle part of the bottom end of the copper sheet 3 through the chip packaging assembly, one side of the base island 101 is provided with a pin 102, the insulating pad 2 is fixedly connected with the base island 101 through red glue, the base island 101 is fixedly connected with the MOS tube bare chip 5 through the first tin drawing layer 6, and the pin 102 is fixedly connected with the copper sheet 3 through the third tin drawing layer 8; in order to solve the problem of uneven tin drawing thickness between the copper sheet 3 and the MOS tube bare chip 5 in the prior art, the insulating pad 2 is first fixed on the chip packaging frame 1 by red glue, the surface of the chip packaging frame 1 is loaded with the MOS tube bare chip 5 by forming the second tin drawing layer 6 through tin drawing; the surface of the MOS tube bare chip 5 is loaded with the copper sheet 3 by forming the first tin drawing layer 4 through tin drawing; then the first jig 9 and the second jig 10 are used to press the two ends of the copper sheet 3, the right side second jig 10 provides height limitation to ensure that the tin drawing thickness of the upper surface of the MOS tube bare chip 5 is uniform; finally, vacuum reflow soldering solidification and annealing are carried out, and the preparation of the packaging structure is completed. The red glue has excellent thixotropy and air-free state, can be used for bonding SMD components on the printed circuit board before wave soldering, and is especially suitable for occasions requiring high-speed dispensing, high glue point shape, high wet strength, and good electrical performance; the shear strength of the red glue after solidification is 12-18 MPa, which is much smaller than the stress after solder solidification, so that delamination failure is not caused.

[0035] Further, the copper sheet 3 comprises a chip connecting part 301 arranged at the top end of the insulating pad 2, the chip connecting part 301 is arranged in a plane structure, and a pin connecting part 302 is arranged at one side of the chip connecting part 301; by canceling the dimple design, there is no dimple pressure gate bus phenomenon, and the solder thickness between the MOS tube bare chip and the copper sheet 3 can be ensured to be uniform, and the Die electrical performance breakdown failure phenomenon caused by gate bus stress concentration is avoided.

[0036] Further, the top end of the chip connecting part 301 is provided with a plurality of first waist-shaped through holes 303 arranged at equal intervals, the other side of the top end of the chip connecting part 301 is provided with a plurality of second waist-shaped through holes 304 arranged at equal intervals, one side of the pin connecting part 302 is provided with a half waist-shaped through hole 305, the bottom end of the chip connecting part 301 is provided with a first contact plane 3011 matched with the MOS tube bare chip 5, one side of the first contact plane 3011 is provided with an overflow groove 3012, one side of the bottom end of the pin connecting part 302 is provided with a second contact plane 3013 matched with the third tin drawing layer 8, the distance between the two ends of the first waist-shaped through hole 303 and the overflow groove 3012 is equal, the horizontal distance between the half waist-shaped through hole 305 and the pin 102 is greater than the first preset distance, the height of the insulating pad 2 is equal to the sum of the heights of the first tin drawing layer 6, the MOS tube bare chip 5 and the second tin drawing layer 4, and the horizontal distance between the insulating pad 2 and the MOS tube bare chip 5 is greater than the second preset distance; in the process of tin drawing, part of the tin drawing is too thick and too much, and the excess solder and air can be discharged from the bottom of the hole to the upper part in the tin drawing, so that the large particle void (Void) is avoided to be formed between the copper sheet 3 and the MOS tube bare chip 5, and the on-resistance (Rdson) caused by the excessive thermal resistance of the chip packaging structure is avoided to be too large, so that the product performance is degraded.

[0037] Further, the half waist-shaped plastic sealing material exhaust hole 304 is arranged on the copper sheet 3 in the application, the half waist-shaped plastic sealing material exhaust hole 304 needs to be at least partially opposite to the distance between the leadFrame base island and the pin paddle, so that the material defects such as lack of material and void can be easily guided to the overflow area outside the packaging, and the defects generated in the product Moulding process are avoided.

[0038] Further, the exhaust hole in the application ensures that the left and right sides are located in the middle position of the glue inlet, so that the water vapor and air bubbles at the joint of the parting line are gathered and discharged upward through the hole, the EMC is avoided to generate the material defects and void defects, and the distance greater than 0.11 ensures that the leadframe is opposite to the area of the exhaust hole, the air is discharged with the shortest distance, and the exhaust resistance is the smallest.

[0039] Further, the Clip adopts a bending plane-free design structure, which can greatly decompose and optimize the influence of thermal expansion stress on the Die during the work of the Clip.

[0040] Further, the size of the excess tin overflow hole 302, 303 of the copper sheet 3 is 0.2*1, and the pinch is 1.12; the size of the insulating pad 2 is 4*0.9*0.16 (the thickness is controlled according to the thickness of the MOS tube bare chip 5 and the tin thickness); the size of the half waist-shaped plastic sealing material exhaust hole 304 of the copper sheet 3 is 0.5*0.2, and the distance opposite to the chip packaging frame 1 base island and the pin paddle is greater than 0.11; the distance between the insulating pad 2 and the MOS tube bare chip 5 is greater than 0.12.

[0041] The basic principle, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only preferred examples of the present application and are not intended to limit the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A packaging structure applicable to multiple MOS chips, characterized by: The packaging structure comprises a chip packaging frame (1), the top end of the chip packaging frame (1) is provided with an insulating pad (2), the other side of the top end of the chip packaging frame (1) is provided with a chip packaging assembly, and the top end of the insulating pad (2) is provided with a copper sheet (3) matched with the chip packaging assembly.

2. The packaging structure of claim 1, wherein: The top end of the copper sheet (3) is provided with an epoxy plastic sealing material (7) matched with the chip packaging frame (1), and a third tin drawing layer (8) is arranged between the bottom end of the copper sheet (3) and the chip packaging frame (1).

3. The packaging structure of claim 2, wherein: The chip packaging assembly comprises an MOS tube bare chip (5) arranged on one side of the top end of the chip packaging frame (1), a first tin drawing layer (6) is arranged between the MOS tube bare chip (5) and the chip packaging frame (1), and a second tin drawing layer (4) is arranged between the MOS tube bare chip (5) and the copper sheet (3).

4. The packaging structure of claim 3, wherein: The chip packaging frame (1) comprises a base island (101) arranged at the bottom end of the insulating pad (2), the top end of the base island (101) is connected to the middle of the bottom end of the copper sheet (3) through the chip packaging assembly, and one side of the base island (101) is provided with a pin (102).

5. The packaging structure of claim 4, wherein: The insulating pad (2) and the base island (101) are fixedly connected through red glue, the base island (101) and the MOS tube bare chip (5) are fixedly connected through the first tin drawing layer (6), and the pin (102) is fixedly connected with the copper sheet (3) through the third tin drawing layer (8).

6. The packaging structure of claim 4, wherein: The copper sheet (3) comprises a chip connecting portion (301) arranged at the top end of the insulating pad (2), the chip connecting portion (301) is arranged in a plane structure, and one side of the chip connecting portion (301) is provided with a pin connecting portion (302).

7. The packaging structure of claim 6, wherein: A plurality of first waist-shaped through holes (303) are arranged at the top end of the chip connecting portion (301), a plurality of second waist-shaped through holes (304) are arranged at the other top end of the chip connecting portion (301), and a half waist-shaped through hole (305) is arranged at one side of the pin connecting portion (302).

8. The packaging structure of claim 7, wherein: The bottom end of the chip connecting portion (301) is provided with a first contact plane (3011) matched with the MOS tube bare chip (5), one side of the first contact plane (3011) is provided with an overflow groove (3012), and the bottom end of the pin connecting portion (302) is provided with a second contact plane (3013) matched with the third tin drawing layer (8).

9. The packaging structure of claim 8, wherein: The distance between the two ends of the first waist-shaped through hole (303) and the overflow groove (3012) is equal, and the horizontal distance between the half waist-shaped through hole (305) and the pin (102) is greater than a first preset distance.

10. The MOS chip packaging structure applicable to multiple types according to claim 4, characterized in that: The height of the insulating pad (2) is equal to the sum of the heights of the first tin drawing layer (6), the MOS tube bare chip (5) and the second tin drawing layer (4), and the horizontal distance between the insulating pad (2) and the MOS tube bare chip (5) is greater than a second preset distance.

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