Battery pack equalization circuit controlled by PWM (Pulse-Width Modulation)

Abstract

The utility model discloses a battery pack equalization circuit controlled by PWM (Pulse Width Modulation). The battery pack equalization circuit comprises a triode Q1, a capacitor C1, a diode D1, a capacitor C3, a trigger U1, an MOS (Metal Oxide Semiconductor) tube Q2 and a relay RL1, a collector electrode is connected to the capacitor C1, and a base electrode receives a PWM signal; the capacitor C1 is connected to the diode D1, the diode D1 is connected to the capacitor C3 and an input end A of the trigger U1, a fifth pin of the trigger U1 is an output end Y, the output end Y is connected to a grid electrode of the MOS tube Q2, a source electrode of the MOS tube Q2 is grounded, a drain electrode of the MOS tube Q2 is connected with a first pin of the relay RL1, a third pin of the relay RL1 is connected with a positive electrode of the equalization resistor, and a fifth pin of the relay RL1 is connected with a positive electrode of the battery pack. The cathode of the battery pack is connected with the cathode of the equalization resistor. Balanced switching of the battery modules is controlled through PWM dynamic signals, and the emptying risk of the battery modules is reduced to a great extent by means of the capacitance coupling effect.

Description

TECHNICAL FIELD

[0001] The utility model relates to a battery pack, concretely is a battery pack equalizing circuit controlled by PWM. BACKGROUND

[0002] With the rapid development of energy storage field in recent years, higher requirements are put forward for the capacity of energy storage system, and the battery pack cannot be designed too large due to transportation and storage and other factors, so the formation of multiple battery pack combination system is imperative. Because the battery pack is a single individual, randomness occurs in the combination and maintenance process, resulting in inconsistent voltage between the battery packs. If the battery pack single cell is balanced, the efficiency is too low. In order to improve the efficiency, the battery pack needs to be balanced. In the balancing process, the whole battery pack is often over-discharged due to the loss of control system, which reduces the service life of the battery pack or causes the battery pack to be scrapped, or even causes the battery pack to catch fire. SUMMARY

[0003] In order to solve the defects of the prior art, the utility model provides a battery pack equalizing circuit controlled by PWM, and the utility model is a kind of inter-package passive equalization execution method of battery management system, and circuit control unit can effectively prevent battery over-discharge caused by circuit device damage or single-chip microcomputer downtime, even empty.

[0004] To achieve the above technical purpose, the utility model adopts the following technical scheme: a battery pack equalizing circuit controlled by PWM, including triode Q1, capacitor C1, diode D1, capacitor C3, trigger U1, MOS tube Q2, relay RL1;The collector is connected to capacitor C1, and the base receives PWM signal;Capacitor C1 is connected to diode D1, diode D1 is connected to capacitor C3 and the input end A of trigger U1, the 5 pin of trigger U1 is output end Y, output end Y is connected to the gate of MOS tube Q2, the source electrode of MOS tube Q2 is grounded, and the drain electrode is connected to the 1 pin of relay RL1, the 3 pin of relay RL1 is connected to the positive pole of equalizing resistance, the positive pole of battery pack is connected to the 5 pin of relay RL1, and the negative pole of battery pack is connected to the negative pole of equalizing resistance.

[0005] Further, one way of the base of triode Q1 is connected to resistance R2 for receiving PWM signal, and the other way is connected to resistance R3, and resistance R3 is grounded;The collector of triode Q1 is also connected with resistance R1, and resistance R1 is connected with +5V power supply;The emitter of triode Q1 is grounded.

[0006] Further, capacitor C1 is also connected to diode D3, diode D3 is connected to resistance R4, and resistance R4 is grounded.

[0007] Further, diode D1 is also connected with resistance R5, resistance R5 is connected with capacitor C3 in parallel, and resistance R5 is grounded.

[0008] Further, the 3-pin ground of the flip-flop U1 is connected with the 5-pin in one way and with the capacitor C2 in another way, and the capacitor C2 is grounded.

[0009] Further, the gate of the MOS tube Q2 is connected with the resistor R6, and the resistor R6 is grounded.

[0010] In conclusion, the utility model has achieved the following technical effects:

[0011] The utility model discloses a PWM dynamic signal is used to control the switch of battery module equalization, and utilizes the capacitor coupling effect to reduce the risk of battery module emptying to a great extent.

[0012] The traditional control signal is only controlled by high or low static signal, and the circuit is simple and low in cost, but for the battery module equalization control, the risk is very high, and the utility model discloses a PWM dynamic signal is used to control the switch of battery module equalization, which effectively prevents the damage or misoperation of the hardware control unit from causing the battery module to be emptied. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 It is the circuit schematic diagram provided by the utility model embodiment. DETAILED DESCRIPTION

[0014] The utility model will be further described in detail in combination with the drawings.

[0015] The specific embodiment is only the explanation of the utility model, and it is not the limitation of the utility model, and the person skilled in the art can make the modification without the creative contribution according to the need after reading the specification, but as long as it is within the scope of the claims of the utility model, it is protected by the patent law.

[0016] In the description of the utility model, it is understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the utility model.

[0017] In addition, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" are only used for descriptive purpose and cannot be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" can explicitly or implicitly include one or more of the features. In the description of the utility model, the meaning of "multiple" is two or more than two, unless otherwise specifically limited.

[0018] In the utility model, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the communication inside two elements or the interaction relationship of two elements. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.

[0019] In the utility model, unless otherwise specifically defined and limited, the first feature is "on" or "under" the second feature, which can be direct contact of the first and second features, or indirect contact of the first and second features through intermediate medium. Moreover, the first feature "above", "upper" and "upper surface" of the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under surface" of the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0020] Embodiment:

[0021] As shown in Figure 1 A battery pack equalization circuit controlled by PWM, as shown in the figure, 3 battery groups are shown, and each battery group is configured with a battery pack equalization circuit, which can equalize the respective battery group.

[0022] It includes triode Q1, capacitor C1, diode D1, capacitor C3, flip-flop U1, MOS tube Q2 and relay RL1; the collector is connected to capacitor C1, and the base receives PWM signal; capacitor C1 is connected to diode D1, diode D1 is connected to capacitor C3 and the input end A of flip-flop U1, the 5th pin of flip-flop U1 is output end Y, output end Y is connected to the gate of MOS tube Q2, the source of MOS tube Q2 is grounded, and the drain is connected to the 1st pin of relay RL1, the 3rd pin of relay RL1 is connected to the positive pole of equalization resistor, the 5th pin of relay RL1 is connected to the positive pole of battery group, and the negative pole of battery group is connected to the negative pole of equalization resistor.

[0023] The base of the triode Q1 is connected with the resistor R2 for receiving the PWM signal, and is connected with the resistor R3 which is grounded; the collector of the triode Q1 is also connected with the resistor R1 which is connected with the +5V power supply; and the emitter of the triode Q1 is grounded.

[0024] The capacitor C1 is also connected with the diode D3 which is connected with the resistor R4 which is grounded. The diode D1 is also connected with the resistor R5 which is connected with the capacitor C3 in parallel and is grounded. The 3 pin of the flip-flop U1 is grounded, the 5 pin is connected with the +5V power supply in one way and is connected with the capacitor C2 in another way, and the capacitor C2 is grounded. The gate of Q2 is connected with the resistor R6 which is grounded. The resistor R4 in series with the freewheeling D3 can effectively prevent the triode Q1 from being damaged due to too large freewheeling current; the R5 and R6 are both used as pull-down resistors to provide a low level for the default state and timely discharge the crosstalk signal; the D2 is used for releasing the stored magnetic energy of the coil of the relay RL1 at the moment of turning off the relay RL1 to prevent the MOS tube Q2 from being damaged by superimposed voltage; the flip-flop U1 can also be replaced by a comparator, and the flip-flop in the embodiment is a Schmitt trigger.

[0025] Working principle:

[0026] The utility model discloses a PWM control equalizing switch, when the single-chip microcomputer is dead or produces hardware failure, the I / O control output can only be two states of high or low, at this time, the flip-flop input end is low level, and the output is also low level, and the MOS drive of the control equalizing relay is also low, at this time, the battery pack can not be discharged equalizing.

[0027] When the BMU sends the equalizing request, the single-chip microcomputer gives the PACK_BALANCE1 pulsating direct current PWM signal, and the triode Q1 will not stop high-frequency switching, at this time, the potential of the left end of C1 also stops high-low switching, and the potential of the right end of C1 also stops high-low switching, at this time, the potential will be transmitted to the capacitor C3 through the diode D1, and the input end A of the flip-flop U1 is a relatively stable high level after filtering of the capacitor C3, and the output end Y is also high (+5V), the gate of the MOS tube Q2 is driven, at this time, the MOS tube Q2 is opened, the relay RL1 is attracted, the positive and negative poles of the battery pack 1 are discharged through the equalizing resistor, and the battery pack module equalizing is realized.

[0028] If the single-chip microcomputer is dead or has a hardware failure, the I / O control output can only be high or low, and since the capacitor C1 has the characteristics of passing AC and blocking DC, the high potential at the left end of the capacitor C1 cannot be transmitted to the right end, the right end of the capacitor C1 is always pulled down to low by R5, the input end A of the flip-flop U1 is a stable low level, the output end Y is also low, and the gate of the MOS tube Q2 is also low, at this time, the MOS tube Q2 is cut off, the relay RL1 is disconnected, and the battery pack 1 cannot realize the battery pack module equalization.

[0029] The above only describes the preferred embodiments of the present application, and does not limit the present application in any form, and any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments are within the scope of the technical scheme of the present application.

Claims

1. A PWM controlled battery pack equalization circuit, characterized by: It includes triode Q1, capacitor C1, diode D1, capacitor C3, flip-flop U1, MOS tube Q2, relay RL1; the collector is connected to capacitor C1, the base receives PWM signal; capacitor C1 is connected to diode D1, diode D1 is connected to capacitor C3 and the input end A of flip-flop U1, the 5th pin of flip-flop U1 is output end Y, output end Y is connected to the gate of MOS tube Q2, the source of MOS tube Q2 is grounded, the drain is connected to the 1st pin of relay RL1, the 3rd pin of relay RL1 is connected to the positive pole of equalization resistance, the 5th pin of relay RL1 is connected to the positive pole of battery pack, the negative pole of battery pack is connected to the negative pole of equalization resistance.

2. The PWM-controlled battery pack equalization circuit of claim 1, wherein: The base of triode Q1 is connected to resistance R2 for receiving PWM signal, and is connected to resistance R3, and resistance R3 is grounded; the collector of triode Q1 is also connected to resistance R1, and resistance R1 is connected to +5V power supply; the emitter of triode Q1 is grounded.

3. The PWM controlled battery pack equalization circuit of claim 1, wherein: Capacitor C1 is also connected to diode D3, and diode D3 is connected to resistance R4, and resistance R4 is grounded.

4. The PWM-controlled battery pack equalization circuit of claim 1, wherein: Diode D1 is also connected to resistance R5, and resistance R5 is connected to capacitor C3 in parallel, and resistance R5 is grounded.

5. The PWM controlled battery pack equalization circuit of claim 1, wherein: The 3rd pin of flip-flop U1 is grounded, and the 5th pin is connected to +5V power supply in one way, and is connected to capacitor C2 in another way, and capacitor C2 is grounded.

6. The PWM controlled battery pack equalization circuit of claim 1, wherein: The gate of MOS tube Q2 is connected to resistance R6, and resistance R6 is grounded.

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