Circuit for preventing airborne instantaneous power supply interruption and suppressing surge

Abstract

A circuit for preventing airborne instantaneous power supply interruption and suppressing surge relates to the technical field of airborne aviation power supplies and comprises a voltage monitoring circuit, a logic control circuit, a pre-charging circuit, an energy storage capacitor and a switching circuit, the pre-charging circuit is connected with the input of an external power supply, and the output of the pre-charging circuit is connected with the switching circuit through the energy storage capacitor. An external power supply input is connected with a pre-charging circuit and a switching circuit through a voltage monitoring circuit and a logic control circuit, an output of the switching circuit is a power supply output end for preventing airborne instantaneous power supply interruption and a surge suppression circuit, and a reverse protection circuit is arranged between the external power supply input and the power supply output end. And the reverse protection circuit is integrally connected with the voltage monitoring circuit, the logic control circuit, the pre-charging circuit, the energy storage capacitor and the switching circuit. The anti-instant-power-down circuit and the control method have the advantages of small size, light weight, low cost and simple control, and meanwhile, the circuit is effective for suppressing surge voltage.

Description

TECHNICAL FIELD

[0001] The utility model relates to airborne aviation power supply technical field especially relates to a circuit for preventing airborne transient power supply interruption and surge suppression. BACKGROUND

[0002] As the power source of airborne electronic equipment, the power supply determines the reliability of the whole machine to a great extent. At present, the on-board low-voltage DC system is mostly powered by 28V, and is powered by the main power supply during normal operation. In the case of engine starting, failure and other special conditions, the auxiliary power supply such as storage battery is used for power supply, and there is a power conversion. According to the national military standard GJB181A-2003, the interruption time during power conversion should not be greater than 50ms. The 28V DC power supply system is mostly used for power supply of communication and data processing equipment, and still needs to maintain normal working state during power supply interruption. Therefore, targeted design measures are needed to make the equipment adapt to 50ms power supply interruption.

[0003] The commonly used solutions are as follows:

[0004] 1. Increase the standby battery, detect the input power failure time, and switch to the standby battery power supply. The main disadvantages of this scheme are as follows:

[0005] a) For equipment with weight requirements, the weight of the equipment will be greatly increased, and even the weight will exceed the standard;

[0006] b) The battery charging time is long, which is not conducive to frequent use;

[0007] c) Limited by the size of the battery, the equipment cannot be miniaturized.

[0008] 2. Parallel capacitors (electrolytic capacitors, solid-state capacitors, super capacitors, etc.) are connected to the power input. The higher the input voltage, the more energy stored, and vice versa. The energy stored in the capacitor cannot be completely released.

[0009] 3. Two-stage topology (main scheme): the front-stage topology adopts a Boost circuit, and the rear-stage is a normal topology such as flyback, half-bridge or full-bridge circuit. The external energy storage capacitor is placed between the two-stage topology, i.e. the output end of the Boost circuit. When the input voltage is low, the Boost circuit raises the low input voltage to a set high voltage value to charge the external energy storage capacitor. When the input voltage is high, the Boost circuit is bypassed, and the high input voltage directly charges the external energy storage capacitor, so that a large voltage-resistant and small-capacity electrolytic capacitor can meet the power failure delay function. When the input voltage is cut off, the external energy storage capacitor can continue to provide energy to the rear stage to realize the power failure holding time. The disadvantages are: 1) the two-stage series circuit topology is complex, which reduces the system reliability; 2) the whole machine efficiency is reduced, which increases the system temperature and reduces the service life.

[0010] 4. The method is realized by using a boost and buck circuit, a set of boost and buck circuits are designed respectively. The buck circuit does not work when the input is normal, the boost circuit works, the input voltage is raised to a relatively high voltage, and the energy is stored in the energy storage capacitor; when the input power fails or is under-voltage, the boost circuit does not work, the buck circuit works, the relatively high voltage stored in the energy storage capacitor is bucked to the working voltage of the load in the later stage, so as to achieve the function of power failure retention. This method has a disadvantage, that is, the buck circuit and the boost circuit each need a power inductor. As a magnetic device, the power inductor accounts for a considerable proportion in the volume and weight of the switching power supply, therefore, this method does not have the advantages of small size, light weight and low cost. Practical new type content

[0011] In view of the above-mentioned defects and deficiencies of the prior art, the utility model provides a kind of circuit for preventing airborne instantaneous power interruption and surge suppression, with small size, light weight, low cost control simple anti instantaneous power failure circuit and control method, while the circuit is effective to suppress surge voltage.

[0012] In order to achieve the above purpose, the main technical scheme adopted by the utility model includes:

[0013] A kind of circuit for preventing airborne instantaneous power interruption and surge suppression, including voltage monitoring circuit, logic control circuit, pre-charging circuit, energy storage capacitor, switching circuit, pre-charging circuit is connected with external power input, the output of pre-charging circuit is connected with switching circuit by energy storage capacitor, external power input is connected with pre-charging circuit and switching circuit by voltage monitoring circuit, logic control circuit, pre-charging circuit and switching circuit are connected, the output of switching circuit is the power output end of the circuit for preventing airborne instantaneous power interruption and surge suppression, reverse protection circuit is arranged between external power input and power output end, reverse protection circuit is connected with voltage monitoring circuit, logic control circuit, pre-charging circuit, energy storage capacitor, switching circuit whole.

[0014] Further, the reverse protection circuit is composed of a fast switching diode D1.

[0015] Further, the voltage monitoring circuit uses precision resistors R4 and R6 to divide voltage and send to the logic control circuit.

[0016] Further, the pre-charge circuit is composed of diode D2, diode D3, triode Q2, triode Q4, capacitor C2, resistor R2, resistor R5 and resistor R7, the 2-pin of triode Q2 is connected with the positive pole of diode D2, the 1-pin of triode Q2 is connected with resistor R2, the other end of resistor R2 is connected with the PWM control of CPU and resistor R7, the other end of resistor R7 is connected with the 1-pin of triode Q4, the 2-pin of triode Q4 is grounded, the 3-pin of triode Q4 is connected with capacitor C2 through resistor R5, the 3-pin of triode Q2 is connected with capacitor C2, the other end of capacitor C2 is connected with the negative pole of diode D2 and the positive pole of diode D3, the negative pole of diode D3 is connected with the energy storage capacitor, and the 2-pin of triode Q2, the positive pole of diode D2 and the 2-pin of triode Q4 are connected with the external power input.

[0017] Further, the energy storage capacitor is electrolytic capacitor C1, the positive pole of capacitor C1 is connected with the output of the pre-charge circuit, and the other end of capacitor C1 is connected with the switching circuit.

[0018] Further, the switching circuit is composed of MOS tube Q1, triode Q3, resistor R1, resistor R3 and diode D5, the energy storage capacitor is connected with the 2-pin of triode Q3 and grounded, the 3-pin of triode Q3 is connected with resistor R1 and the G pole of MOS tube Q1, the other end of resistor R1 is connected with the S pole of MOS tube Q1, the 1-pin of triode Q3 is connected with resistor R3, the other end of R3 is connected with the SWITCH signal of CPU, the D pole of MOS tube Q1 is connected with the positive pole of diode D5, and the negative pole of D5 is output as the input of the next stage.

[0019] The utility model discloses the beneficial effect is:

[0020] 1, the utility model discloses the energy storage capacitor's step -up is not realized with BOOST circuit, all adopts power inductance absorption and release energy in the prior art, the utility model discloses the capacitor as absorption and release's device, uses PWM and carries out control, and it is continuously charged and discharged to it. The utility model discloses the step -up circuit structure is simple and convenient to realize, because not adopting BOOST circuit, need not power inductance, can reduce product volume and weight;

[0021] 2, the prior art is separately increased surge voltage suppression capacitor for surge voltage suppression, and the utility model discloses the energy storage capacitor gives consideration to the function of surge voltage suppression. DRAWINGS

[0022] Figure 1 It is the circuit composition schematic diagram of preventing airborne instantaneous power interruption and surge suppression of the utility model;

[0023] Figure 2 It is the circuit schematic diagram of preventing airborne instantaneous power interruption and surge suppression of the utility model. PREFERRED EMBODIMENT

[0024] In order to better explain the utility model, so as to facilitate understanding, below combining with the drawings, through specific embodiment, the utility model is described in detail.

[0025] The utility model provides a kind of circuit for preventing airborne instantaneous power interruption and surge suppression, as shown in Figure 1 The output of pre-charge circuit is connected with switch circuit through energy storage capacitor, and external power input is connected with pre-charge circuit and switch circuit through voltage monitoring circuit and logic control circuit, and the output of switch circuit is the power output end of the circuit for preventing airborne instantaneous power interruption and surge suppression, reverse protection circuit is arranged between external power input and power output end, and reverse protection circuit is connected with voltage monitoring circuit, logic control circuit, pre-charge circuit, energy storage capacitor and switch circuit as a whole.

[0026] The reverse protection circuit is composed of fast switching diode D1, utilizes the characteristics of forward conduction and reverse cut-off, and is connected in series with diode in main power supply line to prevent energy storage capacitor from discharging and flowing back into external input power, which causes electronic components to burn out.

[0027] The voltage monitoring circuit adopts precision resistor R4 and R6 to divide voltage and send to logic control circuit, and logic control circuit CPU can be ARM, single-chip microcomputer, FPGA and other intelligent chips, to carry out A / D sampling, and control circuit power-off opens capacitor output voltage threshold value.

[0028] External power input is divided into three paths, one path is connected with the negative electrode of diode D5 of switch circuit after being inputted from the positive electrode of diode D1 of reverse protection circuit and outputted from the negative electrode, one path is connected with the negative electrode of diode D4 after being connected with resistor R4 and resistor R6 of voltage monitoring circuit, and then sent to AD sampling, the other end of resistor R6 is connected with the positive electrode of diode D4, one path is connected with the 2 pin of PNP triode Q2 of pre-charge circuit and the positive electrode of diode D2, and the negative electrode of diode D5 of switch circuit and the negative electrode of diode D1 of reverse protection circuit are connected to do next stage input.

[0029] The pre-charge circuit is composed of diode D2, diode D3, triode Q2, triode Q4, capacitor C2, resistor R2, resistor R5 and resistor R7. The 2-pin of triode Q2 is connected with the positive pole of diode D2, the 1-pin of triode Q2 is connected with resistor R2, the other end of resistor R2 is connected with the PWM control of CPU and resistor R7, the other end of resistor R7 is connected with the 1-pin of triode Q4, the 2-pin of triode Q4 is connected with the ground, the 3-pin of triode Q4 is connected with capacitor C2 through resistor R5, the 3-pin of triode Q2 is connected with capacitor C2, the other end of capacitor C2 is connected with the negative pole of diode D2 and the positive pole of diode D3, the negative pole of diode D3 is connected with the energy storage capacitor, and the 2-pin of triode Q2, the positive pole of diode D2 and the 2-pin of triode Q4 are connected with the external power input. Diode D3 mainly prevents the voltage of the energy storage capacitor from flowing back into the input power supply after power failure, so as to prevent the burnout of the idle electronic components. Diode D2 mainly prevents the voltage of capacitor C2 from flowing back into the input power supply after power failure. Diode D5 mainly prevents the main line power supply circuit from charging the energy storage capacitor C1. Resistor R5 mainly limits the charging current of capacitor C2 to prevent the current from being too large.

[0030] The working process of the pre-charge circuit is as follows: when the external power is turned on, the energy storage capacitor C1 is charged through D2 and D3 at the moment of power-on. At this time, the G-level voltage of Q1 (PMOS) is equal to the voltage of C1 capacitor, and Q3 (NPN) is closed to switch the power supply circuit.

[0031] After the power-on control circuit is stable, the voltage is monitored, and the SWITCH is set to low level. At this time, triode Q3 closes Q1 to keep the open state. The PWM output is high level, Q2 (PNP) is cut off, Q4 (NPN) is turned on, the input voltage charges C2 capacitor through D2, C2, R5 and Q4, forming a positive polarity on the top and a negative polarity on the bottom. At this time, the voltage of C2 capacitor is equal to the input voltage. When the PWM output is low level, Q2 is turned on and Q4 is cut off. At this time, the external input charges capacitor C1 through Q2, C2 and D3. Since there is a voltage equal to the input voltage between the two ends of C2, the voltage for charging the energy storage capacitor C1 is twice the external input voltage. Through the control of PWM on Q2 and Q4, the voltage of the energy storage capacitor can be charged to twice the external input voltage.

[0032] Surge voltage suppression: when the surge voltage comes, it is absorbed by the energy storage capacitor through D2 and D3, achieving the purpose of suppressing the surge voltage.

[0033] The energy storage capacitor is electrolytic capacitor C1. The positive pole of capacitor C1 is connected with the output of the pre-charge circuit, and the other end of capacitor C1 is connected with the switching circuit.

[0034] The switching circuit consists of a MOS transistor Q1, a transistor Q3, resistors R1, R3, and a diode D5. A storage capacitor is connected to pin 2 of transistor Q3 and then to ground. Pin 3 of transistor Q3 is connected to resistor R1 and the G terminal of MOS transistor Q1. The other end of resistor R1 is connected to the S terminal of MOS transistor Q1. Pin 1 of transistor Q3 is connected to resistor R3. The other end of R3 is connected to the CPU's SWITCH signal. The D terminal of MOS transistor Q1 is connected to the anode of diode D5, and the cathode of D5 serves as the input for the next stage. When the voltage monitoring circuit detects the power-off threshold, the control circuit sets the SWITCH signal to a high level, turning on Q3 and pulling the G terminal of Q1 (PMOS) to a low level, turning on Q1. The energy storage capacitor C1 provides short-term power to the subsequent circuit via Q1.

[0035] When the voltage monitoring circuit reaches the power-on threshold, the control circuit switches the SWITCH signal to a low level, Q3 is cut off, and the G level of Q1 is high, so Q1 is cut off. At this time, the energy storage capacitor cannot supply power to the outside.

[0036] The working process of the utility model is as follows: when the external power is turned on, the energy storage capacitor C1 is charged through D2 and D3 at the moment of power-on. At this time, since the G-level voltage of Q1 (PMOS) is equal to the capacitor voltage of C1, Q1 is cut off, and the external power supply is supplied to the internal circuit after passing through the diode D1; after the content circuit is powered on, the CPU outputs a SWICH signal to turn off Q3.

[0037] After the internal circuit stabilizes after power-on, the voltage is monitored (R4 and R5 divide the voltage and send it to AD for sampling); when the PWM output is high, Q2 (PNP) is cut off, Q4 (NPN) is turned on, and the input voltage charges the C2 capacitor through D2, C2, R5, and Q4, forming a positive polarity at the top and a negative polarity at the bottom. At this time, the voltage of the C2 capacitor is equal to the external input voltage; when the PWM output is low, Q2 is turned on and Q4 is cut off; at this time, the external input charges the capacitor C1 through Q2, C2, and D3. Since there is a voltage across C2 equal to the external input, the voltage charged to the energy storage capacitor C1 is twice the external input voltage; through PWM control of Q2 and Q4, the energy storage capacitor voltage can be charged to twice the external input voltage.

[0038] When the voltage monitoring circuit detects that the voltage drops to the threshold value, the control circuit sets the SWITCH signal to a high level, Q3 turns on, and pulls the G pole of Q1 (PMOS) to a low level until Q1 turns on. The energy storage capacitor C1 provides short-term power to the subsequent circuit through Q1 and diode D5.

[0039] When the voltage monitoring circuit reaches the power-on threshold, the control circuit switches the SWITCH signal to a low level, Q3 is cut off, and the G level of Q1 is high, so Q1 is cut off. At this time, the energy storage capacitor cannot supply power to the outside.

[0040] The system control logic is as follows: when the system is powered on by external power supply, Q1 is cut off, the external power supply input is supplied to the next stage after D1, after the control circuit is started, the voltage monitoring and the SWITCH signal to low level keep Q1 cut off, when the voltage reaches the power-on threshold value, the PWM output is started, the energy storage capacitor is charged, and the voltage of the energy storage capacitor reaches twice the input voltage; when the voltage monitoring reaches the power-off threshold value, the SWITCH signal to high level, at this time Q1 is turned on, and the energy storage capacitor supplies power to the next stage through Q1 and D5.

[0041] Although the embodiments of the utility model have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the utility model, and the ordinary skilled in the art can make changes, modifications, replacements and changes to the above-mentioned embodiments, which all belong to the range of the utility model.

Claims

1. A circuit for preventing airborne transient power interruptions and surge suppression, characterized by: The voltage monitoring circuit, the logic control circuit, the pre-charge circuit, the energy storage capacitor, the switch circuit, the pre-charge circuit is connected with the external power input, the output of the pre-charge circuit is connected with the switch circuit through the energy storage capacitor, the external power input is connected with the pre-charge circuit and the switch circuit through the voltage monitoring circuit and the logic control circuit, the output of the switch circuit is the power output end of the anti-jamming and surge suppression circuit, the reverse protection circuit is arranged between the external power input and the power output end, and the reverse protection circuit is connected with the voltage monitoring circuit, the logic control circuit, the pre-charge circuit, the energy storage capacitor and the switch circuit as a whole.

2. A circuit for preventing airborne transient power supply interruptions and surge suppression as defined in claim 1, wherein: The reverse protection circuit is composed of a fast switching diode D1.

3. The circuit for preventing airborne transient power supply interruption and surge suppression as claimed in claim 1 wherein: The voltage monitoring circuit adopts precise resistors R4 and R6 for voltage division and then sends to the logic control circuit.

4. The circuit for preventing airborne transient power supply interruption and surge suppression of claim 1, wherein: The pre-charge circuit is composed of a diode D2, a diode D3, a transistor Q2, a transistor Q4, a capacitor C2, a resistor R2, a resistor R5 and a resistor R7, the 2-pin of the transistor Q2 is connected with the positive pole of the diode D2, the 1-pin of the transistor Q2 is connected with the resistor R2, the other end of the resistor R2 is connected with the PWM control of the CPU and the resistor R7, the other end of the resistor R7 is connected with the 1-pin of the transistor Q4, the 2-pin of the transistor Q4 is grounded, the 3-pin of the transistor Q4 is connected with the capacitor C2 through the resistor R5, the 3-pin of the transistor Q2 is connected with the capacitor C2, the other end of the capacitor C2 is connected with the negative pole of the diode D2 and the positive pole of the diode D3, the negative pole of the diode D3 is connected with the energy storage capacitor, and the 2-pin of the transistor Q2, the positive pole of the diode D2 and the 2-pin of the transistor Q4 are connected with the external power input.

5. The circuit for preventing airborne transient power supply interruption and surge suppression as claimed in claim 1, wherein: The energy storage capacitor is an electrolytic capacitor C1, the positive pole of the capacitor C1 is connected with the output of the pre-charge circuit, and the other end of the capacitor C1 is connected with the switch circuit.

6. The circuit for preventing airborne transient power supply interruption and surge suppression of claim 1, wherein: The switch circuit is composed of a MOS transistor Q1, a transistor Q3, a resistor R1, a resistor R3 and a diode D5, the energy storage capacitor is connected with the 2-pin of the transistor Q3 and grounded, the 3-pin of the transistor Q3 is connected with the resistor R1 and the G pole of the MOS transistor Q1, the other end of the resistor R1 is connected with the S pole of the MOS transistor Q1, the 1-pin of the transistor Q3 is connected with the resistor R3, the other end of the resistor R3 is connected with the SWITCH signal of the CPU, the D pole of the MOS transistor Q1 is connected with the positive pole of the diode D5, and the negative pole of the diode D5 is output as the input of the next stage.

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