Transistor and electronic device

Abstract

The embodiment of the utility model relates to a transistor and an electronic device. A MOSFET transistor has a semiconductor body comprising a drain region of a first conductivity type delimited by a front surface and at least one cell comprising: a pair of gate structures laterally offset parallel to a first axis, each gate structure includes a respective gate dielectric region disposed on the front surface and a respective gate conductive region disposed on the respective gate dielectric region; a body structure of a second conductivity type including a body region extending inside the drain region starting from the front surface and contacting a portion of the gate dielectric region, and a reinforcement region extending below the body region; and a pair of source regions of the first conductivity type extending inside the body region starting from the front surface. The body structure includes an enrichment region that extends inside the body region below the source regions and projects laterally parallel to the first axis in both directions with respect to the paired source regions.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to MOSFET transistors with improved body structure to improve robustness and related manufacturing processes. BACKGROUND

[0002] It is known that there exist MOSFET transistors designed to withstand particularly high voltages; in use, these MOSFET transistors can find themselves operating under breakdown conditions for short periods of time. For example, when a MOSFET transistor has an inductive type load, it can have to withstand a drain-source voltage higher than the breakdown voltage, in which case the drain-source diode present in the MOSFET transistor is flowed through by a high reverse current. As a result of this reverse current, the parasitic bipolar transistor formed by the body region, the source region and the drain region of the MOSFET transistor can be turned on, in which case a further increase in the current flowing through the MOSFET transistor can occur, leading to a subsequent damage of the MOSFET transistor. These operating scenarios are precisely reproduced during the so-called "unclamped inductive switching" (UIS) test, which is aimed at verifying the actual robustness of the MOSFET transistor.

[0003] The present disclosure provides a MOSFET transistor capable of withstanding high reverse currents without causing the turn-on of the corresponding parasitic bipolar transistor. SUMMARY

[0004] The present disclosure relates to one or more embodiments to overcome one or more deficiencies present in existing transistors and electronic devices.

[0005] According to one embodiment of the present disclosure, a transistor is provided, comprising: a semiconductor body, the semiconductor body comprising a drain region of a first conductivity type, the drain region being defined by a first surface, the first surface being opposite to a second surface along a first direction; and a plurality of units, the plurality of units being in the semiconductor body. The plurality of units include: a pair of gate structures, the pair of gate structures being laterally offset along a second direction, the second direction being laterally transverse to the first direction, each gate structure including a corresponding gate dielectric region and a corresponding gate conductive region, the corresponding gate dielectric region being arranged on the first surface, the corresponding gate conductive region being arranged on the corresponding gate dielectric region; a body structure of the second conductivity type, the body structure including a body region and a reinforcement region, the body region extending from the first surface along the first direction into the drain region and contacting a portion of the gate dielectric region, the reinforcement region extending from the body region to the second surface along the first direction into the drain region; a pair of source regions of the first conductivity type, the pair of source regions extending from the first surface inside the body region, each source region being coupled to the corresponding gate dielectric region; and an enriched region, the enriched region being in the body structure, the enriched region having a doping level greater than a doping level of the body region, and extending inside the body region between the source region and the reinforcement region, the enriched region having a first dimension along the second direction, the first dimension being greater than a second dimension of the reinforcement region along the second direction.

[0006] According to another embodiment of the present disclosure, an electronic device is provided, comprising: a substrate having a first surface, the first surface being opposite to a second surface along a first direction; a drain region in the substrate, the drain region having a first surface coplanar with the first surface of the substrate, and the drain region having a first conductivity type; a first gate structure on the first surface of the substrate; a second gate structure on the first surface of the substrate, the second gate structure being separated from the first gate structure along a second direction transverse to the first direction; a body structure extending into the drain region; and a plurality of source regions in the body region, each source region having a first surface coplanar with the first surface of the substrate. The body structure comprises: a body region extending into the drain region by a first distance along the first direction; and a reinforcement region having a second depth along the first direction that is greater than the first depth, and a second width along the second direction that is less than the first width. The main region includes: a first surface coplanar with the first surface of the substrate, the first surface having a first width along the second direction; and a maximum width along the second direction that is greater than the first width of the first surface of the main region, the maximum width being a first depth along the first direction, the first depth being between the first surface of the substrate and the second surface of the substrate.

[0007] The above-described embodiments of the present disclosure can realize transistors and electronic devices with improved performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0009] Figure 1 a cross-section of a portion of a MOSFET transistor is schematically shown; and

[0010] Figures 2 to 9 a cross-section of a MOSFET transistor shown in Figure 1 is schematically shown during successive steps of a manufacturing process. DETAILED DESCRIPTION

[0011] Figure 1 An orthogonal reference frame XYZ and a MOSFET transistor 1 are shown, the transistor 1 comprising a semiconductor body 4 (for example formed of silicon, and comprising a substrate 6 and a drain region 8).

[0012] For example, the substrate 6 has an N++ type doping (for example comprised between 1*10 18 cm -3 and 9*10 20 cm -3 and is delimited at the bottom by a bottom surface S bot which is substantially parallel to the XY plane. The drain region 8 has for example an N type doping (for example comprised between 1*10 14 cm -3 and 1*10 17 cm -3 and extends in direct contact above the substrate 6. Moreover, the drain region 8 is delimited at the top by a top surface S top which is substantially parallel to the XY plane.

[0013] Moreover, the MOSFET transistor 1 comprises a plurality of gate structures 10 (two of which are visible in Figure 1 ) and a plurality of body structures 20 (one of which is visible in Figure 1 ).

[0014] The gate structures 10 are substantially equal to each other, extend above the top surface S top and have an elongated shape parallel to the Y axis; moreover, the gate structures 10 are arranged laterally offset parallel to the X axis.

[0015] The body structures 20 are substantially equal to each other, extend inside the drain region 8 starting from the top surface S top and have an elongated shape parallel to the Y axis; moreover, the body structures 20 are arranged laterally offset parallel to the X axis in an alternating manner with respect to the gate structures 10. In other words, parallel to the X axis, each body structure 20 extends between two corresponding gate structures 10, as Figure 1As shown in .

[0016] In practice, each main structure 20 forms a cell 2 of the MOSFET transistor 1 together with the corresponding pair of gate structures 10. Therefore, the MOSFET transistor 1 is composed of a plurality of cells 2 ( Figure 1 The cells 2 are formed in a manner similar to that of the cells 1 (only one of which is visible), the cells 2 being approximately equal to one another and arranged parallel to the X-axis such that adjacent cells share the same gate structure 10.

[0017] In more detail, each gate structure 10 includes a corresponding gate dielectric region 12 , a corresponding gate conductive region 14 , and a corresponding gate insulation region 16 , as described below with reference to a single gate structure 10 .

[0018] In particular, the gate dielectric region 12 is formed on the top surface S top The gate dielectric region 12 extends above the semiconductor body 4, contacts the semiconductor body 4, and is formed of a dielectric material such as, for example, an oxide (eg, thermal oxide).

[0019] The gate conductive region 14 extends over and directly contacts the gate dielectric region 12 and is formed of, for example, polysilicon. The gate conductive region 14 also has a substantially planar shape and is elongated parallel to the Y-axis.

[0020] The gate insulating region 16 is formed of a dielectric material such as, for example, an oxide (e.g., silicon oxide or TEOS), and extends so as to surround the gate dielectric region 12 and the gate conductive region 14 on top and laterally. In particular, a central portion of the gate insulating region 16 extends above the gate conductive region 14, directly contacting the gate conductive region 14; furthermore, two lateral portions of the gate insulating region 16 extend on opposite sides of the gate dielectric region 12 and the gate conductive region 14, so as to laterally cover the gate dielectric region 12 and the gate conductive region 14, directly contacting the gate dielectric region 12 and the gate conductive region 14, until contacting the semiconductor body 4 at the bottom.

[0021] Although not shown, the gate conductive regions 14 are arranged in electrical contact with one another in a manner known per se so as to form a gate terminal of the MOSFET transistor 1. In order to allow the gate terminal to be electrically coupled to the outside world, the MOSFET transistor 1 may, for example, include a gate metallization (not shown) that extends through a portion of at least one gate insulating region 16 so as to electrically contact the corresponding gate conductive region 14. However, these details are not relevant to the operation of the MOSFET transistor 1.

[0022] The MOSFET transistor 1 further includes a drain metallization 37 extending below the substrate 6 in direct contact, and a source metallization 17 extending over the gate insulating regions 16 in direct contact and extending between the gate insulating regions 16 to contact the exposed top surface S of the gate structure 10.top of the body structure 20.

[0023] With reference again to the body structure 20, it comprises a body region 22 and a reinforcement region 24, which will be described in greater detail hereinafter; for this purpose, a symmetry plane H is introduced parallel to the YZ plane and such that the two gate structures 10 corresponding to the body structure 20 are arranged symmetrically with respect to the symmetry plane H. Moreover, without loss of generality, as a first approximation, the body structure 20 has a cross section parallel to the XZ plane, which is invariant for translations along the Y axis.

[0024] In detail, both the body region 22 and the reinforcement region 24 have an elongated shape parallel to the Y axis and are substantially symmetrical with respect to the symmetry plane H. Moreover, the body region 22 and the reinforcement region 24 have a P-type doping (for example, comprised between 1*10 14 cm -3 and 1*10 16 cm -3 .

[0025] In greater detail, the reinforcement region 24 is arranged below the body region 22 and has an approximately parallelepiped shape, whose axes are parallel to the Y axis.

[0026] With regard to the body region 22, it has a circular shape in cross section. In particular, the body region 22 comprises a central portion 25 facing the top surface S top at the top and contacting the reinforcement region 24 at the bottom, and a pair of peripheral portions 26', 26" extending in an approximately symmetrical manner with respect to the symmetry plane on opposite sides with respect to the central portion 25. The peripheral portions 26', 26" protrude laterally with respect to the underlying reinforcement region 24.

[0027] In greater detail, each peripheral portion 26', 26" faces the top surface S top at the top and has a convex profile defining a corresponding recess arranged facing the central portion 25.

[0028] In greater detail, with w(z) we indicate a function representing the variation of the value of the width w (parallel to the X axis) of the body region 22 as a function of the z coordinate taken along the Z axis, the following occurs.

[0029] At the top surface S top , the function w(z) initially equals the value W top ; subsequently, as the value of the z coordinate decreases, thus as the depth inside the semiconductor body 4 increases, the value of the function w(z) increases, up to reaching a maximum value W max; subsequently, as the value of the z coordinate decreases, the value of the function w(z) decreases, until it reaches the value W at the plane where the body region 22 and the reinforcement region 24 are in contact init (which represents the width of the reinforcement region 24). It will also occur that W init < W top < W max .

[0030] In other words, the body region 22 has a width which, as the depth inside the semiconductor body 4 increases, follows a non-monotonic trend which exhibits a maximum value at an intermediate depth with respect to the top surface S top and the reinforcement region 24.

[0031] Each body structure 20 also comprises a corresponding enrichment region 23 having a P+ type doping. In addition, for each body structure 20, the MOSFET transistor 1 comprises a pair of corresponding source regions (two of which are visible in the figure) having an N+ type doping and hereinafter referred to as first source region 30' and second source region 30" respectively. Figure 1

[0032] In detail, the first source region 30' and the second source region 30" have an elongated shape parallel to the Y axis and extend inside the body region 22 starting from the top surface S top in such a way as to be arranged at a distance parallel to the X axis in a substantially symmetrical manner with respect to the plane of symmetry H. Without loss of generality, each of the first source region 30' and the second source region 30" extends partially inside the central portion 25 of the body region 22 and partially inside the corresponding peripheral portion of the pair of peripheral portions 26', 26".

[0033] In more detail, each of the first source region 30' and the second source region 30" extends partially below the corresponding gate structure 10. In particular, each of the first source region 30' and the second source region 30" comprises a respective outer portion which extends below a portion of the gate dielectric region 12 of the corresponding gate structure 10, directly contacting it, an intermediate portion which extends below a lateral portion of the corresponding gate insulating region 16, directly contacting it, and an inner portion which extends below a corresponding portion of the source metallization 17, directly contacting it. Furthermore, the first source region 30' and the second source region 30" are laterally separated by a portion of the central portion 25 of the body region 22.

[0034] The enrichment region 23 extends inside the body region 22 at a distance from the top surface S top and the reinforcement region 24 and below the first source region 30' and the second source region 30"; without loss of generality, at a distance from the central portion 25 of the body region 22. Figure 1 ​In the example shown in the figures, the enrichment region 23 does not contact the first source region 30' and the second source region 30", although embodiments in which the enrichment region 23 contacts the first source region 30' and the second source region 30" (not shown) are also possible.

[0035] In more detail, the enrichment region 23 has an approximately elliptical shape in cross section, symmetrical with respect to the plane of symmetry H, and partially occupies the central portion 25 and the peripheral portions 26', 26" of the body region 22, without contacting the drain region 8; in particular, the enrichment region 23 is laterally surrounded by the body region 22 both at the top and at the bottom.

[0036] In more detail, parallel to the X axis, the enrichment region 23 laterally protrudes with respect to the first source region 30' and the second source region 30"; in particular, with reference to the X axis, the enrichment region 23 protrudes to the left with respect to the first source region 30' and to the right with respect to the second source region 30". Figure 1 In the example shown in the figures, the enrichment region 23 does not contact the first source region 30' and the second source region 30", although embodiments in which the enrichment region 23 contacts the first source region 30' and the second source region 30" (not shown) are also possible.

[0037] In use, when the gate terminal of the MOSFET transistor 1 is biased above the threshold voltage, in each cell 2 a pair of conductive channels is formed inside the corresponding body region 22. In particular, a first conductive channel starts from the first source region 30' and extends parallel to the XY plane, under the corresponding gate dielectric region 12, into the peripheral portion 26' of the body region 22; a second conductive channel starts from the second source region 30" and extends parallel to the XY plane, under the corresponding gate dielectric region 12, into the peripheral portion 26" of the body region 22.

[0038] Therefore, in each cell 2, the current can initially flow in the corresponding conductive channel formed in the respective body region 22; then, the current follows a vertical direction (parallel to the Z axis) inside the drain region 8 towards the drain metallization 37.

[0039] In practice, the MOSFET transistor 1 has a super-junction structure and, as mentioned above, comprises a plurality of cells 2. Moreover, as mentioned above, the MOSFET transistor 1 comprises a plurality of super-junction regions 24, each of which is formed by a plurality of pairs of first and second source regions 30', 30". Figure 1 In the example shown in the figures, with reference to the second source region 30" (but the same considerations also apply to the first source region 30'), the second source region 30" forms the emitter of a parasitic bipolar transistor of the NPN type (qualitatively shown in the figure Figure 1 In the example shown in the figures, with reference to the second source region 30" (but the same considerations also apply to the first source region 30'), the second source region 30" forms the emitter of a parasitic bipolar transistor of the NPN type (qualitatively shown in the figure

[0040] However, due to the fact that the enrichment region 23 is laterally protruding with respect to the second source region 30", it happens that the base of the parasitic bipolar transistor has a high concentration and the distance between the drain and the emitter is large. For these reasons, the parasitic bipolar transistor has a reduced value of the parameter h fe , therefore the value of the current that can flow into the base of the parasitic bipolar transistor before the parasitic bipolar transistor is turned on and the MOSFET transistor 1 is at risk of being destroyed is particularly high. For this reason, the MOSFET transistor 1 is particularly robust, for example if tested with the so-called UIS test.

[0041] Unless otherwise specified, the MOSFET transistor 1 is manufactured by the manufacturing process described hereinafter with reference to a single cell 2.

[0042] As shown in Figure 2 , the semiconductor body 4 is initially formed in a known manner, comprising a substrate 6, a drain region 8, and a reinforcement region 24.

[0043] In particular, the reinforcement region 24 is formed so as to be buried inside the drain region 8, at a distance from the top surface S top . For example, by performing a series of epitaxial growths and ion implantations starting from the substrate 6, the drain region 8 and the reinforcement region 24 can be formed in a manner known per se; the details relating to the manufacture of the drain region 8 and of the reinforcement region 24 are in any case irrelevant for the purposes of manufacturing the MOSFET transistor 1.

[0044] Subsequently, as shown in Figure 3 , a first ion implantation of a P-type doping substance (for example, boron) is performed to form a first thin layer 123 of P+ type between the top surface S top and the reinforcement region 24, which extends into the drain region 8. In particular, the first thin layer 123 extends at a distance from both the top surface S top and the reinforcement region 24.

[0045] In more detail, the aforesaid first implantation is indicated in Figure 3 by the arrow 50 and can be performed with a dose comprised, for example, between 1*10 13 cm -2 and 1*10 15 cm -2 and with an energy comprised, for example, between 100 KeV and 500 KeV and using a beam arranged at a distance from the top surface S topThe first resist mask 40 is formed on the first thin layer 123. In particular, the first mask 40 causes the first thin layer 123 to have an elongated shape parallel to the Y axis; furthermore, the first thin layer 123 has an approximately symmetrical shape about the symmetry plane H and parallel to the X axis, and it protrudes laterally in two directions relative to the reinforcing region 24 of the underlying layer, so that it has a greater width relative to the width of the reinforcing region 24.

[0046] Then, if Figure 4 As shown in FIG, the first mask 40 is removed, and the top surface S top A dielectric layer 112 and a conductive layer 114 are formed thereon.

[0047] The dielectric layer 112 is formed of, for example, a thermally grown oxide and is formed on the top surface S of the semiconductor body 4. top For example, conductive layer 114 is formed by deposition of polysilicon and extends over dielectric layer 112, in direct contact therewith.

[0048] Then, if Figure 5 As shown in FIG, a portion of the conductive layer 114 and a lower portion of the dielectric layer 112 are selectively removed to form a conductive layer facing the top surface S. top Window 99 is formed in the portion of dielectric layer 112. In practice, the remaining portion of dielectric layer 112 forms gate dielectric region 12; the remaining portion of conductive layer 114 forms gate conductive region 14. Furthermore, window 99 extends between two gate dielectric regions 12 and between two gate conductive regions 14; window 99 has a shape that is approximately symmetrical about symmetry plane H.

[0049] In more detail, the window 99 has an elongated shape parallel to the Y axis and covers the reinforcement area 24 at a certain distance. In addition, parallel to the X axis, the window 99 has a width that is smaller than the width of the first thin layer 123. Without loss of generality, Figure 5 In the example shown in , the window 99 has approximately the same width as the reinforcement area 24 .

[0050] Then, if Figure 6 As shown in FIG, a second ion implantation of a P-type dopant (eg, boron) is performed to implant a P-type dopant (eg, boron) on the top surface S. top A P-type second thin layer 125 is formed between the first thin layer 123 and the drain region 8. In particular, the second thin layer 125 is formed between the top surface S top Both extend at a certain distance from the underlying first thin layer 123 .

[0051] In more detail, the aforementioned second injection Figure 6 Indicated by arrow 60, and can be included in 1*10 12 cm -2 and 1*10 14 cm-2 between 60 KeV and 300 KeV. Therefore, the second thin layer 125 has an elongated shape parallel to the Y axis, approximately symmetrical with respect to the plane of symmetry H; moreover, parallel to the X axis, the second thin layer 125 has a smaller width with respect to the width of the first thin layer 123. Therefore, parallel to the X axis, the first thin layer 123 protrudes laterally in both directions with respect to the overlying first thin layer 125. Moreover, without loss of generality, the second thin layer 125 has substantially the same width as the reinforcing region 24.

[0052] Then, a thermal treatment is performed, for example, having a duration comprised between one hour and four hours and at a temperature comprised, for example, between 900°C and 1200°C. In this way, the dopant substances forming the first thin layer 123 and the second thin layer 125 diffuse. In particular, as shown in Figure 7 , the diffusion of the dopant substances forming the first thin layer 123 and the second thin layer 125 causes the formation of the body region 22 and of the enrichment region 23.

[0053] Then, as shown in Figure 8 , a second mask 80 is formed inside the window 99, which laterally delimits a first opening 81 and a second opening 82, laterally offset parallel to the X axis, extending on opposite sides of the second mask 80 and facing the corresponding portions of the top surface S top . In particular, the first opening 81 is laterally delimited by the second mask 80, by one of the two gate dielectric regions 12 and by the overlying gate conductive region 14, while the second opening 82 is laterally delimited by the second mask 80, by the other of the two gate dielectric regions 12 and by the overlying gate conductive region 14.

[0054] Subsequently, as shown in Figure 8 , a third ion implantation of an N-type dopant substance (for example, phosphorus) is performed to form a third thin layer 130' and a fourth thin layer 130" of N+ type, respectively through the first opening 81 and the second opening 82, laterally offset along the X axis and extending into the body region 22, at a distance from the enrichment region 23, between the top surface S top and the enrichment region 23.

[0055] In more detail, the aforesaid third implantation is indicated in Figure 8 by the arrow 90 and can occur with a dose comprised, for example, between 10 15 cm -2 and 10 16 cm -2 and with an energy comprised, for example, between 60 KeV and 150 KeV.

[0056] Then, if Figure 9 , the second mask 80 is removed and a further thermal treatment is performed, for example having a duration comprised between 15 minutes and 60 minutes and at a temperature comprised between 900° C. and 1100° C. In this way, diffusion of the doping substances forming the third thin layer 130′ and the fourth thin layer 130″ takes place, which are transformed into the first source region 30′ and the second source region 30″, respectively. Moreover, as a first approximation, this further thermal treatment has a negligible effect on the body region 22 and the enrichment region 23.

[0057] The manufacturing process can then proceed in a manner known per se and therefore not shown, in order to form the gate insulation region 16 , the source metallization 17 , and the drain metallization 37 .

[0058] As is clear from the foregoing description, the present MOSFET transistor has advantages in reducing the risk of turning on a parasitic bipolar transistor. Furthermore, due to the shape of the body region, the present MOSFET transistor features a reduced electric field beneath the gate dielectric region, resulting in reduced charge injected into the gate-drain capacitor. Furthermore, a reduced Miller effect can be demonstrated, resulting in reduced energy dissipation and increased switching efficiency.

[0059] Finally, it is evident that modifications and variations may be made to the previously described MOSFET transistor and the related manufacturing process without departing from the scope of the present disclosure as defined in the appended claims.

[0060] For example, the doping types may be reversed relative to those described. Furthermore, the materials may be different from those described.

[0061] A MOSFET transistor is generally described as comprising a semiconductor body (4) comprising a front surface (S top ), the MOSFET transistor (1) further comprising at least one unit (2) comprising: a pair of gate structures (10) laterally offset parallel to the first axis (X), and each gate structure comprising a gate electrode arranged on the front surface (S top ) on the corresponding gate dielectric region (12), and a corresponding gate conductive region (14) arranged on the corresponding gate dielectric region (12); a main structure (20) of a second conductive type, which includes a main region (22) and a reinforcement region (24), the main region (22) extending from the front surface (S top) starting inside the drain region (8) and contacting the portion of the gate dielectric region (12), the reinforcement region (24) extending inside the drain region (8) below the body region (22); and a pair of source regions (30', 30") of the first conductivity type, the pair of source regions (30', 30") starting inside the body region (22) and each contacting a corresponding gate dielectric region (12); wherein the body structure (20) comprises an enrichment region (23) having a doping level greater than a doping level of the body region (22) and extending inside the body region (22) below the pair of source regions (30', 30"); and wherein, parallel to the first axis (X), the enrichment region (23) laterally protrudes in both directions with respect to the pair of source regions (30', 30"). top ) starting inside the body region (22) and each contacting a corresponding gate dielectric region (12); wherein the body structure (20) comprises an enrichment region (23) having a doping level greater than a doping level of the body region (22) and extending inside the body region (22) below the pair of source regions (30', 30"); and wherein, parallel to the first axis (X), the enrichment region (23) laterally protrudes in both directions with respect to the pair of source regions (30', 30").

[0062] The body region (22) has a circular shape; and a width of the body region (22) measured parallel to the first axis (X) has a non-monotonic trend as the depth increases and has a maximum value (W max ) at a depth greater than a maximum depth reached by the source regions (30', 30").

[0063] Parallel to the first axis (X), the enrichment region (23) also laterally protrudes in both directions with respect to the reinforcement region (24).

[0064] The gate structure (10), the body structure (20), and the source regions (30', 30") have an elongated shape parallel to a second axis (Y) perpendicular to the first axis (X).

[0065] The reinforcement region (24) has a doping level lower than a doping level of the enrichment region (23).

[0066] The first conductivity type is N-type conductivity; and the second conductivity type is P-type conductivity.

[0067] A process for manufacturing a MOSFET transistor is outlined as comprising: forming a semiconductor body (4) comprising a drain region (8) of a first conductivity type delimited by a front surface (S top ); and forming at least one cell (2) comprising: forming a pair of gate structures (10) laterally offset parallel to a first axis (X) and each comprising a corresponding gate dielectric region (12) arranged on the front surface (S top ), and a corresponding gate conductive region (14) arranged on the corresponding gate dielectric region (12); forming a body structure (20) of a second conductivity type, wherein forming the body structure (20) comprises: forming a body region (22) starting from the front surface (S top ); and forming a reinforcement region (24) starting inside the drain region (8) and contacting the portion of the gate dielectric region (12), the reinforcement region (24) extending inside the drain region (8) below the body region (22); and a pair of source regions (30', 30") of the first conductivity type, the pair of source regions (30', 30") starting inside the body region (22) and each contacting a corresponding gate dielectric region (12); wherein the body structure (20) comprises an enrichment region (23) having a doping level greater than a doping level of the body region (22) and extending inside the body region (22) below the pair of source regions (30', 30"); and wherein, parallel to the first axis (X), the enrichment region (23) laterally protrudes in both directions with respect to the pair of source regions (30', 30").) starting inside the drain region (8) and contacting the gate dielectric region (12), the reinforcement region (24) extending inside the drain region (8) below the body region (22); and forming a pair of source regions (30', 30") of the first conductivity type, the pair of source regions (30', 30") extending inside the body region (22) from the front surface (S top ) starting inside the body region (22) and each contacting a corresponding gate dielectric region (12); and wherein forming the body structure (20) further comprises forming an enrichment region (23) having a doping level greater than that of the body region (22) and extending inside the body region (22) below the source regions (30', 30"); and wherein, parallel to the first axis (X), the enrichment region (23) laterally protrudes in both directions with respect to the pair of source regions (30', 30").

[0068] The manufacturing process comprises, after forming the reinforcement region (24) and before forming the gate structure (10), forming, by a first implant of a doping species of the second conductivity type, between the front surface (S top ) and the reinforcement region (24), a first implanted layer (123) extending into the drain region (8); subsequently forming the gate dielectric region (12) and the gate conductive region (14); subsequently forming, by a second implant of a doping species of the second conductivity type, between the front surface (S top ) and the first implanted layer (123), a second implanted layer (125) extending into the drain region (8); and subsequently performing a first heat treatment so as to cause diffusion of the doping species of the first and second implanted layers (123, 125) and subsequent formation of the body region (22) and the enrichment region (23).

[0069] Said second implant is performed through a window (99) formed by the gate dielectric region (12) and the gate conductive region (14).

[0070] Forming the first implanted layer (123) comprises performing said first implant through a mask (40) arranged on the front surface (S top ) and such that, parallel to the first axis (X), the first implanted layer (123) laterally protrudes in both directions with respect to the reinforcement region (24).

[0071] Forming the second implanted layer (125) comprises forming the second implanted layer (125) such that, parallel to the first axis (X), the first implanted layer (123) laterally protrudes in both directions with respect to the second implanted layer (125).

[0072] Forming the pair of source regions (30', 30") includes, after the first heat treatment, forming third and fourth implant layers (130', 130") by a third implant of a dopant species of the first conductivity type, the third and fourth implant layers (130', 130") extending within the body region (22) above the enrichment region (23); and subsequently performing a second heat treatment to cause diffusion of the dopant species of the third and fourth implant layers (130', 130") and subsequent formation of the source regions (30', 30").

[0073] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of different embodiments can be modified and / or combined to provide additional embodiments.

[0074] These and other changes can be made to the embodiments in light of the above Detailed Description. The terms used in the following claims should not be construed to limit the claims present application to the specific embodiments disclosed in the specification and the claims. The scope of the claims should be interpreted by the specification and the appended claims are intended to cover all changes that come within the meaning and range of equivalents. Accordingly, the claims are not limited by the disclosure.

Claims

1. A transistor, comprising: comprises: a semiconductor body including a drain region of a first conductivity type, the drain region being bounded by a first surface, the first surface being opposite a second surface along a first direction; and a plurality of cells in the semiconductor body, the plurality of cells including: a pair of gate structures, the pair of gate structures being laterally offset along a second direction, the second direction being transverse to the first direction, each gate structure including a respective gate dielectric region and a respective gate conductive region, the respective gate dielectric region being disposed on the first surface, the respective gate conductive region being disposed on the corresponding gate dielectric region; a body structure of a second conductivity type, the body structure including a body region and a reinforcement region, the body region extending into the drain region from the first surface along the first direction and contacting portions of the gate dielectric regions, the reinforcement region extending into the drain region along the first direction between the body region and the second surface; a pair of source regions of the first conductivity type, the pair of source regions extending within the body region from the first surface, each source region being coupled to a corresponding gate dielectric region; and an enrichment region in the body structure, the enrichment region having a doping level greater than a doping level of the body region and extending within the body region between the source regions and the reinforcement region, the enrichment region having a first dimension along the second direction that is greater than a second dimension of the reinforcement region along the second direction.

2. The transistor of claim 1, wherein the body region has a circular shape; and wherein a width of the body region along the second direction has a non-monotonic trend as a depth along the first direction increases and has a maximum width along the second direction at a depth along the first direction that is greater than a maximum depth reached by the source regions along the first direction.

3. The transistor of claim 1, wherein along the second direction, the enrichment region laterally protrudes further than a maximum width along the second direction between a first source region of the pair of source regions and a second source region of the pair of source regions.

4. The transistor of claim 1, wherein the gate structures, the body structure, and the source regions have an elongated shape in a third direction, the third direction being transverse to the first direction and the second direction.

5. The transistor of claim 1, wherein the reinforcement region has a doping level that is lower than a doping level of the enrichment region.

6. The transistor of claim 1, wherein the first conductivity type is N-type conductivity; and wherein the second conductivity type is P-type conductivity.

7. An electronic device, characterized by comprises: a substrate having a first surface, the first surface being opposite a second surface along a first direction; a drain region in the substrate, the drain region having a first surface that is coplanar with the first surface of the substrate, the drain region having a first conductivity type; a first gate structure on the first surface of the substrate; a second gate structure on the first surface of the substrate, the second gate structure being separated from the first gate structure along a second direction that is transverse to the first direction; a body structure extending into the drain region, the body structure comprising: a body region extending into the drain region along the first direction by a first distance, the body region comprising: a first surface coplanar with the first surface of the substrate, the first surface having a first width along the second direction; and a maximum width along the second direction greater than the first width of the first surface of the body region, the maximum width being a first depth along the first direction, the first depth being between the first surface of the substrate and the second surface of the substrate; and a reinforcement region having a second depth along the first direction greater than the first depth, the reinforcement region having a second width along the second direction less than the first width; and a plurality of source regions in the body region, each source region having a first surface coplanar with the first surface of the substrate.

8. Electronic device according to claim 7, characterized in that the first gate structure comprises: a first gate dielectric region on the first surface of the substrate; a first gate conductive region on the first gate dielectric region; and a first gate insulating region directly on the first gate dielectric region and the first surface of the substrate.

9. Electronic device according to claim 8, characterized in that both the first gate dielectric region and the first gate insulating region are in direct contact with a corresponding source region of the plurality of source regions.

10. Electronic device according to claim 8, characterized in that the first gate dielectric region comprises an oxide and the first gate conductive region comprises polysilicon.

11. The electronic device of claim 8, wherein, the first gate conductive region of the first gate structure is electrically coupled to a second gate conductive region of the second gate structure.

12. The electronic device of claim 7, wherein, the body region has a second conductivity type different from the first conductivity type.

13. The electronic device of claim 7, wherein, the plurality of source regions have a maximum depth along the first direction less than a first depth.

14. Electronic device according to claim 13, characterized in that a further comprising an enrichment region in the body region, the enrichment region having a fourth width greater than the second width of the reinforcement region.

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